atomic.hh revision 3349:fec4a86fa212 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_ATOMIC_HH__
32#define __CPU_SIMPLE_ATOMIC_HH__
33
34#include "cpu/simple/base.hh"
35
36class AtomicSimpleCPU : public BaseSimpleCPU
37{
38  public:
39
40    struct Params : public BaseSimpleCPU::Params {
41        int width;
42        bool simulate_stalls;
43    };
44
45    AtomicSimpleCPU(Params *params);
46    virtual ~AtomicSimpleCPU();
47
48    virtual void init();
49
50  public:
51    //
52    enum Status {
53        Running,
54        Idle,
55        SwitchedOut
56    };
57
58  protected:
59    Status _status;
60
61    Status status() const { return _status; }
62
63  private:
64
65    struct TickEvent : public Event
66    {
67        AtomicSimpleCPU *cpu;
68
69        TickEvent(AtomicSimpleCPU *c);
70        void process();
71        const char *description();
72    };
73
74    TickEvent tickEvent;
75
76    const int width;
77    const bool simulate_stalls;
78
79    // main simulation loop (one cycle)
80    void tick();
81
82    class CpuPort : public Port
83    {
84
85        AtomicSimpleCPU *cpu;
86
87      public:
88
89        CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
90            : Port(_name), cpu(_cpu)
91        { }
92
93      protected:
94
95        virtual bool recvTiming(PacketPtr pkt);
96
97        virtual Tick recvAtomic(PacketPtr pkt);
98
99        virtual void recvFunctional(PacketPtr pkt);
100
101        virtual void recvStatusChange(Status status);
102
103        virtual void recvRetry();
104
105        virtual void getDeviceAddressRanges(AddrRangeList &resp,
106            AddrRangeList &snoop)
107        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
108
109    };
110    CpuPort icachePort;
111    CpuPort dcachePort;
112
113    Request  *ifetch_req;
114    PacketPtr ifetch_pkt;
115    Request  *data_read_req;
116    PacketPtr data_read_pkt;
117    Request  *data_write_req;
118    PacketPtr data_write_pkt;
119
120    bool dcache_access;
121    Tick dcache_latency;
122
123  public:
124
125    virtual Port *getPort(const std::string &if_name, int idx = -1);
126
127    virtual void serialize(std::ostream &os);
128    virtual void unserialize(Checkpoint *cp, const std::string &section);
129    virtual void resume();
130
131    void switchOut();
132    void takeOverFrom(BaseCPU *oldCPU);
133
134    virtual void activateContext(int thread_num, int delay);
135    virtual void suspendContext(int thread_num);
136
137    template <class T>
138    Fault read(Addr addr, T &data, unsigned flags);
139
140    template <class T>
141    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
142};
143
144#endif // __CPU_SIMPLE_ATOMIC_HH__
145