atomic.hh revision 2923:db8a876258df
16657Snate@binkert.org/* 26657Snate@binkert.org * Copyright (c) 2002-2005 The Regents of The University of Michigan 36657Snate@binkert.org * All rights reserved. 46657Snate@binkert.org * 56657Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66657Snate@binkert.org * modification, are permitted provided that the following conditions are 76657Snate@binkert.org * met: redistributions of source code must retain the above copyright 86657Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96657Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106657Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116657Snate@binkert.org * documentation and/or other materials provided with the distribution; 126657Snate@binkert.org * neither the name of the copyright holders nor the names of its 136657Snate@binkert.org * contributors may be used to endorse or promote products derived from 146657Snate@binkert.org * this software without specific prior written permission. 156657Snate@binkert.org * 166657Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176657Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186657Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196657Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206657Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216657Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226657Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236657Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246657Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256657Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266657Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276657Snate@binkert.org * 2812563Sgabeblack@google.com * Authors: Steve Reinhardt 2912563Sgabeblack@google.com */ 306657Snate@binkert.org 316657Snate@binkert.org#ifndef __CPU_SIMPLE_ATOMIC_HH__ 326657Snate@binkert.org#define __CPU_SIMPLE_ATOMIC_HH__ 336657Snate@binkert.org 346657Snate@binkert.org#include "cpu/simple/base.hh" 3512765Sjason@lowepower.com 366657Snate@binkert.orgclass AtomicSimpleCPU : public BaseSimpleCPU 376657Snate@binkert.org{ 386657Snate@binkert.org public: 396657Snate@binkert.org 406657Snate@binkert.org struct Params : public BaseSimpleCPU::Params { 416657Snate@binkert.org int width; 4212765Sjason@lowepower.com bool simulate_stalls; 4312765Sjason@lowepower.com }; 4412765Sjason@lowepower.com 4512765Sjason@lowepower.com AtomicSimpleCPU(Params *params); 4612765Sjason@lowepower.com virtual ~AtomicSimpleCPU(); 4712765Sjason@lowepower.com 486657Snate@binkert.org virtual void init(); 496657Snate@binkert.org 506657Snate@binkert.org public: 516657Snate@binkert.org // 526657Snate@binkert.org enum Status { 536657Snate@binkert.org Running, 546657Snate@binkert.org Idle, 556657Snate@binkert.org SwitchedOut 5612563Sgabeblack@google.com }; 576657Snate@binkert.org 586657Snate@binkert.org protected: 596657Snate@binkert.org Status _status; 606657Snate@binkert.org 616657Snate@binkert.org Status status() const { return _status; } 6212765Sjason@lowepower.com 636657Snate@binkert.org private: 646657Snate@binkert.org 656657Snate@binkert.org struct TickEvent : public Event 666657Snate@binkert.org { 676657Snate@binkert.org AtomicSimpleCPU *cpu; 686657Snate@binkert.org 696657Snate@binkert.org TickEvent(AtomicSimpleCPU *c); 7012765Sjason@lowepower.com void process(); 716657Snate@binkert.org const char *description(); 728453Snate@binkert.org }; 738453Snate@binkert.org 746657Snate@binkert.org TickEvent tickEvent; 756657Snate@binkert.org 766657Snate@binkert.org const int width; 776657Snate@binkert.org const bool simulate_stalls; 788454Snate@binkert.org 796657Snate@binkert.org // main simulation loop (one cycle) 806657Snate@binkert.org void tick(); 816657Snate@binkert.org 8212765Sjason@lowepower.com class CpuPort : public Port 8312765Sjason@lowepower.com { 8412765Sjason@lowepower.com 8512765Sjason@lowepower.com AtomicSimpleCPU *cpu; 8612765Sjason@lowepower.com 8712765Sjason@lowepower.com public: 886657Snate@binkert.org 896657Snate@binkert.org CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu) 906657Snate@binkert.org : Port(_name), cpu(_cpu) 918453Snate@binkert.org { } 928453Snate@binkert.org 9314184Sgabeblack@google.com protected: 9414184Sgabeblack@google.com 9512765Sjason@lowepower.com virtual bool recvTiming(Packet *pkt); 9612765Sjason@lowepower.com 9712765Sjason@lowepower.com virtual Tick recvAtomic(Packet *pkt); 986657Snate@binkert.org 996657Snate@binkert.org virtual void recvFunctional(Packet *pkt); 1006714Ssteve.reinhardt@amd.com 10112563Sgabeblack@google.com virtual void recvStatusChange(Status status); 1026657Snate@binkert.org 1038453Snate@binkert.org virtual void recvRetry(); 1048453Snate@binkert.org 1056657Snate@binkert.org virtual void getDeviceAddressRanges(AddrRangeList &resp, 1066657Snate@binkert.org AddrRangeList &snoop) 1078453Snate@binkert.org { resp.clear(); snoop.clear(); } 1086657Snate@binkert.org }; 1096657Snate@binkert.org 11012765Sjason@lowepower.com CpuPort icachePort; 11112765Sjason@lowepower.com CpuPort dcachePort; 11212765Sjason@lowepower.com 11312765Sjason@lowepower.com Request *ifetch_req; 1148453Snate@binkert.org Packet *ifetch_pkt; 1156657Snate@binkert.org Request *data_read_req; 1166657Snate@binkert.org Packet *data_read_pkt; 1176657Snate@binkert.org Request *data_write_req; 118 Packet *data_write_pkt; 119 120 bool dcache_access; 121 Tick dcache_latency; 122 123 public: 124 125 virtual Port *getPort(const std::string &if_name, int idx = -1); 126 127 virtual void serialize(std::ostream &os); 128 virtual void unserialize(Checkpoint *cp, const std::string §ion); 129 virtual void resume(); 130 131 virtual void resume(); 132 void switchOut(); 133 void takeOverFrom(BaseCPU *oldCPU); 134 135 virtual void activateContext(int thread_num, int delay); 136 virtual void suspendContext(int thread_num); 137 138 template <class T> 139 Fault read(Addr addr, T &data, unsigned flags); 140 141 template <class T> 142 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 143}; 144 145#endif // __CPU_SIMPLE_ATOMIC_HH__ 146