atomic.hh revision 11303:f694764d656d 
1/*
2 * Copyright (c) 2012-2013,2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __CPU_SIMPLE_ATOMIC_HH__
44#define __CPU_SIMPLE_ATOMIC_HH__
45
46#include "cpu/simple/base.hh"
47#include "cpu/simple/exec_context.hh"
48#include "params/AtomicSimpleCPU.hh"
49#include "sim/probe/probe.hh"
50
51class AtomicSimpleCPU : public BaseSimpleCPU
52{
53  public:
54
55    AtomicSimpleCPU(AtomicSimpleCPUParams *params);
56    virtual ~AtomicSimpleCPU();
57
58    void init() override;
59
60  private:
61
62    struct TickEvent : public Event
63    {
64        AtomicSimpleCPU *cpu;
65
66        TickEvent(AtomicSimpleCPU *c);
67        void process();
68        const char *description() const;
69    };
70
71    TickEvent tickEvent;
72
73    const int width;
74    bool locked;
75    const bool simulate_data_stalls;
76    const bool simulate_inst_stalls;
77
78    // main simulation loop (one cycle)
79    void tick();
80
81    /**
82     * Check if a system is in a drained state.
83     *
84     * We need to drain if:
85     * <ul>
86     * <li>We are in the middle of a microcode sequence as some CPUs
87     *     (e.g., HW accelerated CPUs) can't be started in the middle
88     *     of a gem5 microcode sequence.
89     *
90     * <li>The CPU is in a LLSC region. This shouldn't normally happen
91     *     as these are executed atomically within a single tick()
92     *     call. The only way this can happen at the moment is if
93     *     there is an event in the PC event queue that affects the
94     *     CPU state while it is in an LLSC region.
95     *
96     * <li>Stay at PC is true.
97     * </ul>
98     */
99    bool isDrained() {
100        SimpleExecContext &t_info = *threadInfo[curThread];
101
102        return t_info.thread->microPC() == 0 &&
103            !locked &&
104            !t_info.stayAtPC;
105    }
106
107    /**
108     * Try to complete a drain request.
109     *
110     * @returns true if the CPU is drained, false otherwise.
111     */
112    bool tryCompleteDrain();
113
114    /**
115     * An AtomicCPUPort overrides the default behaviour of the
116     * recvAtomicSnoop and ignores the packet instead of panicking. It
117     * also provides an implementation for the purely virtual timing
118     * functions and panics on either of these.
119     */
120    class AtomicCPUPort : public MasterPort
121    {
122
123      public:
124
125        AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
126            : MasterPort(_name, _cpu)
127        { }
128
129      protected:
130        virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
131
132        bool recvTimingResp(PacketPtr pkt)
133        {
134            panic("Atomic CPU doesn't expect recvTimingResp!\n");
135            return true;
136        }
137
138        void recvReqRetry()
139        {
140            panic("Atomic CPU doesn't expect recvRetry!\n");
141        }
142
143    };
144
145    class AtomicCPUDPort : public AtomicCPUPort
146    {
147
148      public:
149
150        AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
151            : AtomicCPUPort(_name, _cpu), cpu(_cpu)
152        {
153            cacheBlockMask = ~(cpu->cacheLineSize() - 1);
154        }
155
156        bool isSnooping() const { return true; }
157
158        Addr cacheBlockMask;
159      protected:
160        BaseSimpleCPU *cpu;
161
162        virtual Tick recvAtomicSnoop(PacketPtr pkt);
163        virtual void recvFunctionalSnoop(PacketPtr pkt);
164    };
165
166
167    AtomicCPUPort icachePort;
168    AtomicCPUDPort dcachePort;
169
170    bool fastmem;
171    Request ifetch_req;
172    Request data_read_req;
173    Request data_write_req;
174
175    bool dcache_access;
176    Tick dcache_latency;
177
178    /** Probe Points. */
179    ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
180
181  protected:
182
183    /** Return a reference to the data port. */
184    MasterPort &getDataPort() override { return dcachePort; }
185
186    /** Return a reference to the instruction port. */
187    MasterPort &getInstPort() override { return icachePort; }
188
189    /** Perform snoop for other cpu-local thread contexts. */
190    void threadSnoop(PacketPtr pkt, ThreadID sender);
191
192  public:
193
194    DrainState drain() override;
195    void drainResume() override;
196
197    void switchOut() override;
198    void takeOverFrom(BaseCPU *oldCPU) override;
199
200    void verifyMemoryMode() const override;
201
202    void activateContext(ThreadID thread_num) override;
203    void suspendContext(ThreadID thread_num) override;
204
205    Fault readMem(Addr addr, uint8_t *data, unsigned size,
206                  unsigned flags) override;
207
208    Fault initiateMemRead(Addr addr, unsigned size, unsigned flags) override;
209
210    Fault writeMem(uint8_t *data, unsigned size,
211                   Addr addr, unsigned flags, uint64_t *res) override;
212
213    void regProbePoints() override;
214
215    /**
216     * Print state of address in memory system via PrintReq (for
217     * debugging).
218     */
219    void printAddr(Addr a);
220};
221
222#endif // __CPU_SIMPLE_ATOMIC_HH__
223