atomic.hh revision 10030 
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __CPU_SIMPLE_ATOMIC_HH__
44#define __CPU_SIMPLE_ATOMIC_HH__
45
46#include "base/hashmap.hh"
47#include "cpu/simple/base.hh"
48#include "params/AtomicSimpleCPU.hh"
49
50/**
51 *  Start and end address of basic block for SimPoint profiling.
52 *  This structure is used to look up the hash table of BBVs.
53 *  - first: PC of first inst in basic block
54 *  - second: PC of last inst in basic block
55 */
56typedef std::pair<Addr, Addr> BasicBlockRange;
57
58/** Overload hash function for BasicBlockRange type */
59__hash_namespace_begin
60template <>
61struct hash<BasicBlockRange>
62{
63  public:
64    size_t operator()(const BasicBlockRange &bb) const {
65        return hash<Addr>()(bb.first + bb.second);
66    }
67};
68__hash_namespace_end
69
70
71class AtomicSimpleCPU : public BaseSimpleCPU
72{
73  public:
74
75    AtomicSimpleCPU(AtomicSimpleCPUParams *params);
76    virtual ~AtomicSimpleCPU();
77
78    virtual void init();
79
80  private:
81
82    struct TickEvent : public Event
83    {
84        AtomicSimpleCPU *cpu;
85
86        TickEvent(AtomicSimpleCPU *c);
87        void process();
88        const char *description() const;
89    };
90
91    TickEvent tickEvent;
92
93    const int width;
94    bool locked;
95    const bool simulate_data_stalls;
96    const bool simulate_inst_stalls;
97
98    /**
99     * Drain manager to use when signaling drain completion
100     *
101     * This pointer is non-NULL when draining and NULL otherwise.
102     */
103    DrainManager *drain_manager;
104
105    // main simulation loop (one cycle)
106    void tick();
107
108    /**
109     * Check if a system is in a drained state.
110     *
111     * We need to drain if:
112     * <ul>
113     * <li>We are in the middle of a microcode sequence as some CPUs
114     *     (e.g., HW accelerated CPUs) can't be started in the middle
115     *     of a gem5 microcode sequence.
116     *
117     * <li>The CPU is in a LLSC region. This shouldn't normally happen
118     *     as these are executed atomically within a single tick()
119     *     call. The only way this can happen at the moment is if
120     *     there is an event in the PC event queue that affects the
121     *     CPU state while it is in an LLSC region.
122     *
123     * <li>Stay at PC is true.
124     * </ul>
125     */
126    bool isDrained() {
127        return microPC() == 0 &&
128            !locked &&
129            !stayAtPC;
130    }
131
132    /**
133     * Try to complete a drain request.
134     *
135     * @returns true if the CPU is drained, false otherwise.
136     */
137    bool tryCompleteDrain();
138
139    /**
140     * An AtomicCPUPort overrides the default behaviour of the
141     * recvAtomicSnoop and ignores the packet instead of panicking. It
142     * also provides an implementation for the purely virtual timing
143     * functions and panics on either of these.
144     */
145    class AtomicCPUPort : public MasterPort
146    {
147
148      public:
149
150        AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
151            : MasterPort(_name, _cpu)
152        { }
153
154      protected:
155        virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
156
157        bool recvTimingResp(PacketPtr pkt)
158        {
159            panic("Atomic CPU doesn't expect recvTimingResp!\n");
160            return true;
161        }
162
163        void recvRetry()
164        {
165            panic("Atomic CPU doesn't expect recvRetry!\n");
166        }
167
168    };
169
170    class AtomicCPUDPort : public AtomicCPUPort
171    {
172
173      public:
174
175        AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
176            : AtomicCPUPort(_name, _cpu), cpu(_cpu)
177        {
178            cacheBlockMask = ~(cpu->cacheLineSize() - 1);
179        }
180
181        bool isSnooping() const { return true; }
182
183        Addr cacheBlockMask;
184      protected:
185        BaseSimpleCPU *cpu;
186
187        virtual Tick recvAtomicSnoop(PacketPtr pkt);
188        virtual void recvFunctionalSnoop(PacketPtr pkt);
189    };
190
191
192    AtomicCPUPort icachePort;
193    AtomicCPUDPort dcachePort;
194
195    bool fastmem;
196    Request ifetch_req;
197    Request data_read_req;
198    Request data_write_req;
199
200    bool dcache_access;
201    Tick dcache_latency;
202
203    /**
204     * Profile basic blocks for SimPoints.
205     * Called at every macro inst to increment basic block inst counts and
206     * to profile block if end of block.
207     */
208    void profileSimPoint();
209
210    /** Data structures for SimPoints BBV generation
211     *  @{
212     */
213
214    /** Whether SimPoint BBV profiling is enabled */
215    const bool simpoint;
216    /** SimPoint profiling interval size in instructions */
217    const uint64_t intervalSize;
218
219    /** Inst count in current basic block */
220    uint64_t intervalCount;
221    /** Excess inst count from previous interval*/
222    uint64_t intervalDrift;
223    /** Pointer to SimPoint BBV output stream */
224    std::ostream *simpointStream;
225
226    /** Basic Block information */
227    struct BBInfo {
228        /** Unique ID */
229        uint64_t id;
230        /** Num of static insts in BB */
231        uint64_t insts;
232        /** Accumulated dynamic inst count executed by BB */
233        uint64_t count;
234    };
235
236    /** Hash table containing all previously seen basic blocks */
237    m5::hash_map<BasicBlockRange, BBInfo> bbMap;
238    /** Currently executing basic block */
239    BasicBlockRange currentBBV;
240    /** inst count in current basic block */
241    uint64_t currentBBVInstCount;
242
243    /** @}
244     *  End of data structures for SimPoints BBV generation
245     */
246
247  protected:
248
249    /** Return a reference to the data port. */
250    virtual MasterPort &getDataPort() { return dcachePort; }
251
252    /** Return a reference to the instruction port. */
253    virtual MasterPort &getInstPort() { return icachePort; }
254
255  public:
256
257    unsigned int drain(DrainManager *drain_manager);
258    void drainResume();
259
260    void switchOut();
261    void takeOverFrom(BaseCPU *oldCPU);
262
263    void verifyMemoryMode() const;
264
265    virtual void activateContext(ThreadID thread_num, Cycles delay);
266    virtual void suspendContext(ThreadID thread_num);
267
268    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
269
270    Fault writeMem(uint8_t *data, unsigned size,
271                   Addr addr, unsigned flags, uint64_t *res);
272
273    /**
274     * Print state of address in memory system via PrintReq (for
275     * debugging).
276     */
277    void printAddr(Addr a);
278};
279
280#endif // __CPU_SIMPLE_ATOMIC_HH__
281