atomic.hh revision 9443
12623SN/A/* 28926Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 432623SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 442623SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 452623SN/A 462623SN/A#include "cpu/simple/base.hh" 475529Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 482623SN/A 492623SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 502623SN/A{ 512623SN/A public: 522623SN/A 535529Snate@binkert.org AtomicSimpleCPU(AtomicSimpleCPUParams *params); 542623SN/A virtual ~AtomicSimpleCPU(); 552623SN/A 562623SN/A virtual void init(); 572623SN/A 582623SN/A private: 592623SN/A 602623SN/A struct TickEvent : public Event 612623SN/A { 622623SN/A AtomicSimpleCPU *cpu; 632623SN/A 642623SN/A TickEvent(AtomicSimpleCPU *c); 652623SN/A void process(); 665336Shines@cs.fsu.edu const char *description() const; 672623SN/A }; 682623SN/A 692623SN/A TickEvent tickEvent; 702623SN/A 712623SN/A const int width; 726078Sgblack@eecs.umich.edu bool locked; 735487Snate@binkert.org const bool simulate_data_stalls; 745487Snate@binkert.org const bool simulate_inst_stalls; 752623SN/A 769443SAndreas.Sandberg@ARM.com /** 779443SAndreas.Sandberg@ARM.com * Drain manager to use when signaling drain completion 789443SAndreas.Sandberg@ARM.com * 799443SAndreas.Sandberg@ARM.com * This pointer is non-NULL when draining and NULL otherwise. 809443SAndreas.Sandberg@ARM.com */ 819443SAndreas.Sandberg@ARM.com DrainManager *drain_manager; 829443SAndreas.Sandberg@ARM.com 832623SN/A // main simulation loop (one cycle) 842623SN/A void tick(); 852623SN/A 868707Sandreas.hansson@arm.com /** 879443SAndreas.Sandberg@ARM.com * Check if a system is in a drained state. 889443SAndreas.Sandberg@ARM.com * 899443SAndreas.Sandberg@ARM.com * We need to drain if: 909443SAndreas.Sandberg@ARM.com * <ul> 919443SAndreas.Sandberg@ARM.com * <li>We are in the middle of a microcode sequence as some CPUs 929443SAndreas.Sandberg@ARM.com * (e.g., HW accelerated CPUs) can't be started in the middle 939443SAndreas.Sandberg@ARM.com * of a gem5 microcode sequence. 949443SAndreas.Sandberg@ARM.com * 959443SAndreas.Sandberg@ARM.com * <li>The CPU is in a LLSC region. This shouldn't normally happen 969443SAndreas.Sandberg@ARM.com * as these are executed atomically within a single tick() 979443SAndreas.Sandberg@ARM.com * call. The only way this can happen at the moment is if 989443SAndreas.Sandberg@ARM.com * there is an event in the PC event queue that affects the 999443SAndreas.Sandberg@ARM.com * CPU state while it is in an LLSC region. 1009443SAndreas.Sandberg@ARM.com * 1019443SAndreas.Sandberg@ARM.com * <li>Stay at PC is true. 1029443SAndreas.Sandberg@ARM.com * </ul> 1039443SAndreas.Sandberg@ARM.com */ 1049443SAndreas.Sandberg@ARM.com bool isDrained() { 1059443SAndreas.Sandberg@ARM.com return microPC() == 0 && 1069443SAndreas.Sandberg@ARM.com !locked && 1079443SAndreas.Sandberg@ARM.com !stayAtPC; 1089443SAndreas.Sandberg@ARM.com } 1099443SAndreas.Sandberg@ARM.com 1109443SAndreas.Sandberg@ARM.com /** 1119443SAndreas.Sandberg@ARM.com * Try to complete a drain request. 1129443SAndreas.Sandberg@ARM.com * 1139443SAndreas.Sandberg@ARM.com * @returns true if the CPU is drained, false otherwise. 1149443SAndreas.Sandberg@ARM.com */ 1159443SAndreas.Sandberg@ARM.com bool tryCompleteDrain(); 1169443SAndreas.Sandberg@ARM.com 1179443SAndreas.Sandberg@ARM.com /** 1188707Sandreas.hansson@arm.com * An AtomicCPUPort overrides the default behaviour of the 1198707Sandreas.hansson@arm.com * recvAtomic and ignores the packet instead of panicking. 1208707Sandreas.hansson@arm.com */ 1218707Sandreas.hansson@arm.com class AtomicCPUPort : public CpuPort 1222623SN/A { 1238707Sandreas.hansson@arm.com 1242623SN/A public: 1252623SN/A 1268707Sandreas.hansson@arm.com AtomicCPUPort(const std::string &_name, BaseCPU* _cpu) 1278707Sandreas.hansson@arm.com : CpuPort(_name, _cpu) 1282623SN/A { } 1292623SN/A 1302623SN/A protected: 1312623SN/A 1328948Sandreas.hansson@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt) 1338707Sandreas.hansson@arm.com { 1348707Sandreas.hansson@arm.com // Snooping a coherence request, just return 1358707Sandreas.hansson@arm.com return 0; 1368707Sandreas.hansson@arm.com } 1373192Srdreslin@umich.edu 1382623SN/A }; 1394192Sktlim@umich.edu 1408707Sandreas.hansson@arm.com AtomicCPUPort icachePort; 1418707Sandreas.hansson@arm.com AtomicCPUPort dcachePort; 1422623SN/A 1438926Sandreas.hansson@arm.com bool fastmem; 1444870Sstever@eecs.umich.edu Request ifetch_req; 1454870Sstever@eecs.umich.edu Request data_read_req; 1464870Sstever@eecs.umich.edu Request data_write_req; 1472623SN/A 1482623SN/A bool dcache_access; 1492662Sstever@eecs.umich.edu Tick dcache_latency; 1502623SN/A 1518850Sandreas.hansson@arm.com protected: 1528850Sandreas.hansson@arm.com 1538850Sandreas.hansson@arm.com /** Return a reference to the data port. */ 1548850Sandreas.hansson@arm.com virtual CpuPort &getDataPort() { return dcachePort; } 1558850Sandreas.hansson@arm.com 1568850Sandreas.hansson@arm.com /** Return a reference to the instruction port. */ 1578850Sandreas.hansson@arm.com virtual CpuPort &getInstPort() { return icachePort; } 1588850Sandreas.hansson@arm.com 1592623SN/A public: 1602623SN/A 1619342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *drain_manager); 1629342SAndreas.Sandberg@arm.com void drainResume(); 1632623SN/A 1642798Sktlim@umich.edu void switchOut(); 1652623SN/A void takeOverFrom(BaseCPU *oldCPU); 1662623SN/A 1679180Sandreas.hansson@arm.com virtual void activateContext(ThreadID thread_num, Cycles delay); 1688737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num); 1692623SN/A 1708444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1717520Sgblack@eecs.umich.edu 1728444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 1738444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 1747520Sgblack@eecs.umich.edu 1755315Sstever@gmail.com /** 1765315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 1775315Sstever@gmail.com * debugging). 1785315Sstever@gmail.com */ 1795315Sstever@gmail.com void printAddr(Addr a); 1802623SN/A}; 1812623SN/A 1822623SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 183