atomic.hh revision 5529
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IN NO EVENT SHALL THE COPYRIGHT 2011104Spower.jg@gmail.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111104Spower.jg@gmail.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211104Spower.jg@gmail.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311104Spower.jg@gmail.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411104Spower.jg@gmail.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511104Spower.jg@gmail.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611104Spower.jg@gmail.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711104Spower.jg@gmail.com * 2811104Spower.jg@gmail.com * Authors: Steve Reinhardt 2911104Spower.jg@gmail.com */ 3011104Spower.jg@gmail.com 3111104Spower.jg@gmail.com#ifndef __CPU_SIMPLE_ATOMIC_HH__ 3211104Spower.jg@gmail.com#define __CPU_SIMPLE_ATOMIC_HH__ 3311104Spower.jg@gmail.com 3411104Spower.jg@gmail.com#include "cpu/simple/base.hh" 3511104Spower.jg@gmail.com#include "params/AtomicSimpleCPU.hh" 3611104Spower.jg@gmail.com 3711104Spower.jg@gmail.comclass AtomicSimpleCPU : public BaseSimpleCPU 3811104Spower.jg@gmail.com{ 3911104Spower.jg@gmail.com public: 4012564Sgabeblack@google.com 4113774Sandreas.sandberg@arm.com AtomicSimpleCPU(AtomicSimpleCPUParams *params); 4213774Sandreas.sandberg@arm.com virtual ~AtomicSimpleCPU(); 4312564Sgabeblack@google.com 4411104Spower.jg@gmail.com virtual void init(); 4511104Spower.jg@gmail.com 4611104Spower.jg@gmail.com private: 4711104Spower.jg@gmail.com 4811104Spower.jg@gmail.com struct TickEvent : public Event 4911104Spower.jg@gmail.com { 5011104Spower.jg@gmail.com AtomicSimpleCPU *cpu; 5111104Spower.jg@gmail.com 5211104Spower.jg@gmail.com TickEvent(AtomicSimpleCPU *c); 5311104Spower.jg@gmail.com void process(); 5411104Spower.jg@gmail.com const char *description() const; 5511104Spower.jg@gmail.com }; 5611104Spower.jg@gmail.com 5711104Spower.jg@gmail.com TickEvent tickEvent; 5811104Spower.jg@gmail.com 5911104Spower.jg@gmail.com const int width; 6011104Spower.jg@gmail.com const bool simulate_data_stalls; 6111104Spower.jg@gmail.com const bool simulate_inst_stalls; 6211104Spower.jg@gmail.com 6311104Spower.jg@gmail.com // main simulation loop (one cycle) 6411104Spower.jg@gmail.com void tick(); 6511104Spower.jg@gmail.com 6611104Spower.jg@gmail.com class CpuPort : public Port 6711104Spower.jg@gmail.com { 6811104Spower.jg@gmail.com public: 6911104Spower.jg@gmail.com 7011104Spower.jg@gmail.com CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu) 7111104Spower.jg@gmail.com : Port(_name, _cpu), cpu(_cpu) 7211104Spower.jg@gmail.com { } 7311104Spower.jg@gmail.com 7411104Spower.jg@gmail.com bool snoopRangeSent; 7511104Spower.jg@gmail.com 7611104Spower.jg@gmail.com protected: 7711154Sandreas.hansson@arm.com 7811154Sandreas.hansson@arm.com AtomicSimpleCPU *cpu; 7911154Sandreas.hansson@arm.com 8011104Spower.jg@gmail.com virtual bool recvTiming(PacketPtr pkt); 8111104Spower.jg@gmail.com 8211837Swendy.elsasser@arm.com virtual Tick recvAtomic(PacketPtr pkt); 8311104Spower.jg@gmail.com 8411104Spower.jg@gmail.com virtual void recvFunctional(PacketPtr pkt); 8511104Spower.jg@gmail.com 8611104Spower.jg@gmail.com virtual void recvStatusChange(Status status); 8711104Spower.jg@gmail.com 8811104Spower.jg@gmail.com virtual void recvRetry(); 8911104Spower.jg@gmail.com 9011104Spower.jg@gmail.com virtual void getDeviceAddressRanges(AddrRangeList &resp, 9111104Spower.jg@gmail.com bool &snoop) 9213839Sjason@lowepower.com { resp.clear(); snoop = true; } 9313839Sjason@lowepower.com 9413839Sjason@lowepower.com }; 9513839Sjason@lowepower.com CpuPort icachePort; 9613839Sjason@lowepower.com 9711104Spower.jg@gmail.com class DcachePort : public CpuPort 9811104Spower.jg@gmail.com { 9911851Sbrandon.potter@amd.com public: 10011104Spower.jg@gmail.com DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu) 10111104Spower.jg@gmail.com : CpuPort(_name, _cpu) 10211104Spower.jg@gmail.com { } 10311104Spower.jg@gmail.com 10411104Spower.jg@gmail.com virtual void setPeer(Port *port); 10511104Spower.jg@gmail.com }; 10611104Spower.jg@gmail.com DcachePort dcachePort; 10711104Spower.jg@gmail.com 10811104Spower.jg@gmail.com CpuPort physmemPort; 10911104Spower.jg@gmail.com bool hasPhysMemPort; 11011104Spower.jg@gmail.com Request ifetch_req; 11111104Spower.jg@gmail.com Request data_read_req; 11212564Sgabeblack@google.com Request data_write_req; 11311104Spower.jg@gmail.com 11412564Sgabeblack@google.com bool dcache_access; 115 Tick dcache_latency; 116 117 Range<Addr> physMemAddr; 118 119 public: 120 121 virtual Port *getPort(const std::string &if_name, int idx = -1); 122 123 virtual void serialize(std::ostream &os); 124 virtual void unserialize(Checkpoint *cp, const std::string §ion); 125 virtual void resume(); 126 127 void switchOut(); 128 void takeOverFrom(BaseCPU *oldCPU); 129 130 virtual void activateContext(int thread_num, int delay); 131 virtual void suspendContext(int thread_num); 132 133 template <class T> 134 Fault read(Addr addr, T &data, unsigned flags); 135 136 template <class T> 137 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 138 139 Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 140 int size, unsigned flags); 141 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 142 int size, unsigned flags); 143 144 /** 145 * Print state of address in memory system via PrintReq (for 146 * debugging). 147 */ 148 void printAddr(Addr a); 149}; 150 151#endif // __CPU_SIMPLE_ATOMIC_HH__ 152