atomic.hh revision 5487
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 322623SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 332623SN/A 342623SN/A#include "cpu/simple/base.hh" 352623SN/A 362623SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 372623SN/A{ 382623SN/A public: 392623SN/A 402623SN/A struct Params : public BaseSimpleCPU::Params { 412623SN/A int width; 425487Snate@binkert.org bool simulate_data_stalls; 435487Snate@binkert.org bool simulate_inst_stalls; 442623SN/A }; 452623SN/A 462623SN/A AtomicSimpleCPU(Params *params); 472623SN/A virtual ~AtomicSimpleCPU(); 482623SN/A 492623SN/A virtual void init(); 502623SN/A 512623SN/A public: 522623SN/A // 532623SN/A enum Status { 542623SN/A Running, 552623SN/A Idle, 562623SN/A SwitchedOut 572623SN/A }; 582623SN/A 592623SN/A protected: 602623SN/A Status _status; 612623SN/A 622623SN/A Status status() const { return _status; } 632623SN/A 642623SN/A private: 652623SN/A 662623SN/A struct TickEvent : public Event 672623SN/A { 682623SN/A AtomicSimpleCPU *cpu; 692623SN/A 702623SN/A TickEvent(AtomicSimpleCPU *c); 712623SN/A void process(); 725336Shines@cs.fsu.edu const char *description() const; 732623SN/A }; 742623SN/A 752623SN/A TickEvent tickEvent; 762623SN/A 772623SN/A const int width; 785487Snate@binkert.org const bool simulate_data_stalls; 795487Snate@binkert.org const bool simulate_inst_stalls; 802623SN/A 812623SN/A // main simulation loop (one cycle) 822623SN/A void tick(); 832623SN/A 842623SN/A class CpuPort : public Port 852623SN/A { 862623SN/A public: 872623SN/A 882640Sstever@eecs.umich.edu CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu) 893401Sktlim@umich.edu : Port(_name, _cpu), cpu(_cpu) 902623SN/A { } 912623SN/A 923647Srdreslin@umich.edu bool snoopRangeSent; 933647Srdreslin@umich.edu 942623SN/A protected: 952623SN/A 964192Sktlim@umich.edu AtomicSimpleCPU *cpu; 974192Sktlim@umich.edu 983349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 992623SN/A 1003349Sbinkertn@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1012623SN/A 1023349Sbinkertn@umich.edu virtual void recvFunctional(PacketPtr pkt); 1032623SN/A 1042623SN/A virtual void recvStatusChange(Status status); 1052623SN/A 1062657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1072623SN/A 1082623SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 1094475Sstever@eecs.umich.edu bool &snoop) 1104475Sstever@eecs.umich.edu { resp.clear(); snoop = true; } 1113192Srdreslin@umich.edu 1122623SN/A }; 1132623SN/A CpuPort icachePort; 1144192Sktlim@umich.edu 1154192Sktlim@umich.edu class DcachePort : public CpuPort 1164192Sktlim@umich.edu { 1174192Sktlim@umich.edu public: 1184192Sktlim@umich.edu DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu) 1194192Sktlim@umich.edu : CpuPort(_name, _cpu) 1204192Sktlim@umich.edu { } 1214192Sktlim@umich.edu 1224192Sktlim@umich.edu virtual void setPeer(Port *port); 1234192Sktlim@umich.edu }; 1244192Sktlim@umich.edu DcachePort dcachePort; 1252623SN/A 1264968Sacolyte@umich.edu CpuPort physmemPort; 1274968Sacolyte@umich.edu bool hasPhysMemPort; 1284870Sstever@eecs.umich.edu Request ifetch_req; 1294870Sstever@eecs.umich.edu Request data_read_req; 1304870Sstever@eecs.umich.edu Request data_write_req; 1312623SN/A 1322623SN/A bool dcache_access; 1332662Sstever@eecs.umich.edu Tick dcache_latency; 1342623SN/A 1354968Sacolyte@umich.edu Range<Addr> physMemAddr; 1364968Sacolyte@umich.edu 1372623SN/A public: 1382623SN/A 1392856Srdreslin@umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 1402856Srdreslin@umich.edu 1412623SN/A virtual void serialize(std::ostream &os); 1422623SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1432915Sktlim@umich.edu virtual void resume(); 1442623SN/A 1452798Sktlim@umich.edu void switchOut(); 1462623SN/A void takeOverFrom(BaseCPU *oldCPU); 1472623SN/A 1482623SN/A virtual void activateContext(int thread_num, int delay); 1492623SN/A virtual void suspendContext(int thread_num); 1502623SN/A 1512623SN/A template <class T> 1522623SN/A Fault read(Addr addr, T &data, unsigned flags); 1532623SN/A 1542623SN/A template <class T> 1552623SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1565177Sgblack@eecs.umich.edu 1575177Sgblack@eecs.umich.edu Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 1585177Sgblack@eecs.umich.edu int size, unsigned flags); 1595177Sgblack@eecs.umich.edu Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 1605177Sgblack@eecs.umich.edu int size, unsigned flags); 1615315Sstever@gmail.com 1625315Sstever@gmail.com /** 1635315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 1645315Sstever@gmail.com * debugging). 1655315Sstever@gmail.com */ 1665315Sstever@gmail.com void printAddr(Addr a); 1672623SN/A}; 1682623SN/A 1692623SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 170