atomic.hh revision 3846
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 322623SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 332623SN/A 342623SN/A#include "cpu/simple/base.hh" 352623SN/A 362623SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 372623SN/A{ 382623SN/A public: 392623SN/A 402623SN/A struct Params : public BaseSimpleCPU::Params { 412623SN/A int width; 422623SN/A bool simulate_stalls; 432623SN/A }; 442623SN/A 452623SN/A AtomicSimpleCPU(Params *params); 462623SN/A virtual ~AtomicSimpleCPU(); 472623SN/A 482623SN/A virtual void init(); 492623SN/A 502623SN/A public: 512623SN/A // 522623SN/A enum Status { 532623SN/A Running, 542623SN/A Idle, 552623SN/A SwitchedOut 562623SN/A }; 572623SN/A 582623SN/A protected: 592623SN/A Status _status; 602623SN/A 612623SN/A Status status() const { return _status; } 622623SN/A 632623SN/A private: 642623SN/A 652623SN/A struct TickEvent : public Event 662623SN/A { 672623SN/A AtomicSimpleCPU *cpu; 682623SN/A 692623SN/A TickEvent(AtomicSimpleCPU *c); 702623SN/A void process(); 712623SN/A const char *description(); 722623SN/A }; 732623SN/A 742623SN/A TickEvent tickEvent; 752623SN/A 762623SN/A const int width; 772623SN/A const bool simulate_stalls; 782623SN/A 792623SN/A // main simulation loop (one cycle) 802623SN/A void tick(); 812623SN/A 822623SN/A class CpuPort : public Port 832623SN/A { 842623SN/A 852623SN/A AtomicSimpleCPU *cpu; 862623SN/A 872623SN/A public: 882623SN/A 892640Sstever@eecs.umich.edu CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu) 903401Sktlim@umich.edu : Port(_name, _cpu), cpu(_cpu) 912623SN/A { } 922623SN/A 933647Srdreslin@umich.edu bool snoopRangeSent; 943647Srdreslin@umich.edu 952623SN/A protected: 962623SN/A 973349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 982623SN/A 993349Sbinkertn@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1002623SN/A 1013349Sbinkertn@umich.edu virtual void recvFunctional(PacketPtr pkt); 1022623SN/A 1032623SN/A virtual void recvStatusChange(Status status); 1042623SN/A 1052657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1062623SN/A 1072623SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 1082623SN/A AddrRangeList &snoop) 1093846Shsul@eecs.umich.edu { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } 1103192Srdreslin@umich.edu 1112623SN/A }; 1122623SN/A CpuPort icachePort; 1132623SN/A CpuPort dcachePort; 1142623SN/A 1153349Sbinkertn@umich.edu Request *ifetch_req; 1163349Sbinkertn@umich.edu PacketPtr ifetch_pkt; 1173349Sbinkertn@umich.edu Request *data_read_req; 1183349Sbinkertn@umich.edu PacketPtr data_read_pkt; 1193349Sbinkertn@umich.edu Request *data_write_req; 1203349Sbinkertn@umich.edu PacketPtr data_write_pkt; 1212623SN/A 1222623SN/A bool dcache_access; 1232662Sstever@eecs.umich.edu Tick dcache_latency; 1242623SN/A 1252623SN/A public: 1262623SN/A 1272856Srdreslin@umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 1282856Srdreslin@umich.edu 1292623SN/A virtual void serialize(std::ostream &os); 1302623SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1312915Sktlim@umich.edu virtual void resume(); 1322623SN/A 1332798Sktlim@umich.edu void switchOut(); 1342623SN/A void takeOverFrom(BaseCPU *oldCPU); 1352623SN/A 1362623SN/A virtual void activateContext(int thread_num, int delay); 1372623SN/A virtual void suspendContext(int thread_num); 1382623SN/A 1392623SN/A template <class T> 1402623SN/A Fault read(Addr addr, T &data, unsigned flags); 1412623SN/A 1422623SN/A template <class T> 1432623SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1442623SN/A}; 1452623SN/A 1462623SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 147