atomic.hh revision 3192
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 312855Sgabeblack@google.com * All rights reserved. 412855Sgabeblack@google.com * 512855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412855Sgabeblack@google.com * this software without specific prior written permission. 1512855Sgabeblack@google.com * 1612855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712855Sgabeblack@google.com * 2812855Sgabeblack@google.com * Authors: Steve Reinhardt 2912855Sgabeblack@google.com */ 3012855Sgabeblack@google.com 3112855Sgabeblack@google.com#ifndef __CPU_SIMPLE_ATOMIC_HH__ 3212855Sgabeblack@google.com#define __CPU_SIMPLE_ATOMIC_HH__ 3312855Sgabeblack@google.com 3412855Sgabeblack@google.com#include "cpu/simple/base.hh" 3512855Sgabeblack@google.com 3612855Sgabeblack@google.comclass AtomicSimpleCPU : public BaseSimpleCPU 3712855Sgabeblack@google.com{ 3812855Sgabeblack@google.com public: 3912855Sgabeblack@google.com 4012855Sgabeblack@google.com struct Params : public BaseSimpleCPU::Params { 4112855Sgabeblack@google.com int width; 4212855Sgabeblack@google.com bool simulate_stalls; 4312855Sgabeblack@google.com }; 4412855Sgabeblack@google.com 4512855Sgabeblack@google.com AtomicSimpleCPU(Params *params); 4612855Sgabeblack@google.com virtual ~AtomicSimpleCPU(); 4712855Sgabeblack@google.com 4812855Sgabeblack@google.com virtual void init(); 4912855Sgabeblack@google.com 5012855Sgabeblack@google.com public: 5112855Sgabeblack@google.com // 5212855Sgabeblack@google.com enum Status { 5312855Sgabeblack@google.com Running, 5412855Sgabeblack@google.com Idle, 5512855Sgabeblack@google.com SwitchedOut 56 }; 57 58 protected: 59 Status _status; 60 61 Status status() const { return _status; } 62 63 private: 64 65 struct TickEvent : public Event 66 { 67 AtomicSimpleCPU *cpu; 68 69 TickEvent(AtomicSimpleCPU *c); 70 void process(); 71 const char *description(); 72 }; 73 74 TickEvent tickEvent; 75 76 const int width; 77 const bool simulate_stalls; 78 79 // main simulation loop (one cycle) 80 void tick(); 81 82 class CpuPort : public Port 83 { 84 85 AtomicSimpleCPU *cpu; 86 87 public: 88 89 CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu) 90 : Port(_name), cpu(_cpu) 91 { } 92 93 protected: 94 95 virtual bool recvTiming(Packet *pkt); 96 97 virtual Tick recvAtomic(Packet *pkt); 98 99 virtual void recvFunctional(Packet *pkt); 100 101 virtual void recvStatusChange(Status status); 102 103 virtual void recvRetry(); 104 105 virtual void getDeviceAddressRanges(AddrRangeList &resp, 106 AddrRangeList &snoop) 107 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); } 108 109 }; 110 CpuPort icachePort; 111 CpuPort dcachePort; 112 113 Request *ifetch_req; 114 Packet *ifetch_pkt; 115 Request *data_read_req; 116 Packet *data_read_pkt; 117 Request *data_write_req; 118 Packet *data_write_pkt; 119 120 bool dcache_access; 121 Tick dcache_latency; 122 123 public: 124 125 virtual Port *getPort(const std::string &if_name, int idx = -1); 126 127 virtual void serialize(std::ostream &os); 128 virtual void unserialize(Checkpoint *cp, const std::string §ion); 129 virtual void resume(); 130 131 void switchOut(); 132 void takeOverFrom(BaseCPU *oldCPU); 133 134 virtual void activateContext(int thread_num, int delay); 135 virtual void suspendContext(int thread_num); 136 137 template <class T> 138 Fault read(Addr addr, T &data, unsigned flags); 139 140 template <class T> 141 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 142}; 143 144#endif // __CPU_SIMPLE_ATOMIC_HH__ 145