atomic.hh revision 2662
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272623SN/A */ 282623SN/A 292623SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 302623SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 312623SN/A 322623SN/A#include "cpu/simple/base.hh" 332623SN/A 342623SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 352623SN/A{ 362623SN/A public: 372623SN/A 382623SN/A struct Params : public BaseSimpleCPU::Params { 392623SN/A int width; 402623SN/A bool simulate_stalls; 412623SN/A }; 422623SN/A 432623SN/A AtomicSimpleCPU(Params *params); 442623SN/A virtual ~AtomicSimpleCPU(); 452623SN/A 462623SN/A virtual void init(); 472623SN/A 482623SN/A public: 492623SN/A // 502623SN/A enum Status { 512623SN/A Running, 522623SN/A Idle, 532623SN/A SwitchedOut 542623SN/A }; 552623SN/A 562623SN/A protected: 572623SN/A Status _status; 582623SN/A 592623SN/A Status status() const { return _status; } 602623SN/A 612623SN/A private: 622623SN/A 632623SN/A struct TickEvent : public Event 642623SN/A { 652623SN/A AtomicSimpleCPU *cpu; 662623SN/A 672623SN/A TickEvent(AtomicSimpleCPU *c); 682623SN/A void process(); 692623SN/A const char *description(); 702623SN/A }; 712623SN/A 722623SN/A TickEvent tickEvent; 732623SN/A 742623SN/A const int width; 752623SN/A const bool simulate_stalls; 762623SN/A 772623SN/A // main simulation loop (one cycle) 782623SN/A void tick(); 792623SN/A 802623SN/A class CpuPort : public Port 812623SN/A { 822623SN/A 832623SN/A AtomicSimpleCPU *cpu; 842623SN/A 852623SN/A public: 862623SN/A 872640Sstever@eecs.umich.edu CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu) 882640Sstever@eecs.umich.edu : Port(_name), cpu(_cpu) 892623SN/A { } 902623SN/A 912623SN/A protected: 922623SN/A 932630SN/A virtual bool recvTiming(Packet *pkt); 942623SN/A 952630SN/A virtual Tick recvAtomic(Packet *pkt); 962623SN/A 972630SN/A virtual void recvFunctional(Packet *pkt); 982623SN/A 992623SN/A virtual void recvStatusChange(Status status); 1002623SN/A 1012657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1022623SN/A 1032623SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 1042623SN/A AddrRangeList &snoop) 1052623SN/A { resp.clear(); snoop.clear(); } 1062623SN/A }; 1072623SN/A 1082623SN/A CpuPort icachePort; 1092623SN/A CpuPort dcachePort; 1102623SN/A 1112623SN/A Request *ifetch_req; 1122623SN/A Packet *ifetch_pkt; 1132623SN/A Request *data_read_req; 1142623SN/A Packet *data_read_pkt; 1152623SN/A Request *data_write_req; 1162623SN/A Packet *data_write_pkt; 1172623SN/A 1182623SN/A bool dcache_access; 1192662Sstever@eecs.umich.edu Tick dcache_latency; 1202623SN/A 1212623SN/A public: 1222623SN/A 1232623SN/A virtual void serialize(std::ostream &os); 1242623SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1252623SN/A 1262623SN/A void switchOut(Sampler *s); 1272623SN/A void takeOverFrom(BaseCPU *oldCPU); 1282623SN/A 1292623SN/A virtual void activateContext(int thread_num, int delay); 1302623SN/A virtual void suspendContext(int thread_num); 1312623SN/A 1322623SN/A template <class T> 1332623SN/A Fault read(Addr addr, T &data, unsigned flags); 1342623SN/A 1352623SN/A template <class T> 1362623SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1372623SN/A}; 1382623SN/A 1392623SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 140