atomic.hh revision 11608
12623SN/A/* 211147Smitch.hayenga@arm.com * Copyright (c) 2012-2013,2015 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 432623SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 442623SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 452623SN/A 462623SN/A#include "cpu/simple/base.hh" 4711147Smitch.hayenga@arm.com#include "cpu/simple/exec_context.hh" 4811608Snikos.nikoleris@arm.com#include "mem/request.hh" 495529Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 5010381Sdam.sunwoo@arm.com#include "sim/probe/probe.hh" 519647Sdam.sunwoo@arm.com 522623SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 532623SN/A{ 542623SN/A public: 552623SN/A 565529Snate@binkert.org AtomicSimpleCPU(AtomicSimpleCPUParams *params); 572623SN/A virtual ~AtomicSimpleCPU(); 582623SN/A 5911169Sandreas.hansson@arm.com void init() override; 602623SN/A 612623SN/A private: 622623SN/A 632623SN/A struct TickEvent : public Event 642623SN/A { 652623SN/A AtomicSimpleCPU *cpu; 662623SN/A 672623SN/A TickEvent(AtomicSimpleCPU *c); 682623SN/A void process(); 695336Shines@cs.fsu.edu const char *description() const; 702623SN/A }; 712623SN/A 722623SN/A TickEvent tickEvent; 732623SN/A 742623SN/A const int width; 756078Sgblack@eecs.umich.edu bool locked; 765487Snate@binkert.org const bool simulate_data_stalls; 775487Snate@binkert.org const bool simulate_inst_stalls; 782623SN/A 792623SN/A // main simulation loop (one cycle) 802623SN/A void tick(); 812623SN/A 828707Sandreas.hansson@arm.com /** 839443SAndreas.Sandberg@ARM.com * Check if a system is in a drained state. 849443SAndreas.Sandberg@ARM.com * 859443SAndreas.Sandberg@ARM.com * We need to drain if: 869443SAndreas.Sandberg@ARM.com * <ul> 879443SAndreas.Sandberg@ARM.com * <li>We are in the middle of a microcode sequence as some CPUs 889443SAndreas.Sandberg@ARM.com * (e.g., HW accelerated CPUs) can't be started in the middle 899443SAndreas.Sandberg@ARM.com * of a gem5 microcode sequence. 909443SAndreas.Sandberg@ARM.com * 919443SAndreas.Sandberg@ARM.com * <li>The CPU is in a LLSC region. This shouldn't normally happen 929443SAndreas.Sandberg@ARM.com * as these are executed atomically within a single tick() 939443SAndreas.Sandberg@ARM.com * call. The only way this can happen at the moment is if 949443SAndreas.Sandberg@ARM.com * there is an event in the PC event queue that affects the 959443SAndreas.Sandberg@ARM.com * CPU state while it is in an LLSC region. 969443SAndreas.Sandberg@ARM.com * 979443SAndreas.Sandberg@ARM.com * <li>Stay at PC is true. 989443SAndreas.Sandberg@ARM.com * </ul> 999443SAndreas.Sandberg@ARM.com */ 1009443SAndreas.Sandberg@ARM.com bool isDrained() { 10111147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 10211147Smitch.hayenga@arm.com 10311147Smitch.hayenga@arm.com return t_info.thread->microPC() == 0 && 1049443SAndreas.Sandberg@ARM.com !locked && 10511147Smitch.hayenga@arm.com !t_info.stayAtPC; 1069443SAndreas.Sandberg@ARM.com } 1079443SAndreas.Sandberg@ARM.com 1089443SAndreas.Sandberg@ARM.com /** 1099443SAndreas.Sandberg@ARM.com * Try to complete a drain request. 1109443SAndreas.Sandberg@ARM.com * 1119443SAndreas.Sandberg@ARM.com * @returns true if the CPU is drained, false otherwise. 1129443SAndreas.Sandberg@ARM.com */ 1139443SAndreas.Sandberg@ARM.com bool tryCompleteDrain(); 1149443SAndreas.Sandberg@ARM.com 1159443SAndreas.Sandberg@ARM.com /** 1168707Sandreas.hansson@arm.com * An AtomicCPUPort overrides the default behaviour of the 1179608Sandreas.hansson@arm.com * recvAtomicSnoop and ignores the packet instead of panicking. It 1189608Sandreas.hansson@arm.com * also provides an implementation for the purely virtual timing 1199608Sandreas.hansson@arm.com * functions and panics on either of these. 1208707Sandreas.hansson@arm.com */ 1219608Sandreas.hansson@arm.com class AtomicCPUPort : public MasterPort 1222623SN/A { 1238707Sandreas.hansson@arm.com 1242623SN/A public: 1252623SN/A 12610030SAli.Saidi@ARM.com AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) 1279608Sandreas.hansson@arm.com : MasterPort(_name, _cpu) 1282623SN/A { } 1292623SN/A 1302623SN/A protected: 1313192Srdreslin@umich.edu 1329608Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) 1339608Sandreas.hansson@arm.com { 1349608Sandreas.hansson@arm.com panic("Atomic CPU doesn't expect recvTimingResp!\n"); 1359608Sandreas.hansson@arm.com return true; 1369608Sandreas.hansson@arm.com } 1379608Sandreas.hansson@arm.com 13810713Sandreas.hansson@arm.com void recvReqRetry() 1399608Sandreas.hansson@arm.com { 1409608Sandreas.hansson@arm.com panic("Atomic CPU doesn't expect recvRetry!\n"); 1419608Sandreas.hansson@arm.com } 1429608Sandreas.hansson@arm.com 1432623SN/A }; 1444192Sktlim@umich.edu 14510030SAli.Saidi@ARM.com class AtomicCPUDPort : public AtomicCPUPort 14610030SAli.Saidi@ARM.com { 14710030SAli.Saidi@ARM.com 14810030SAli.Saidi@ARM.com public: 14910030SAli.Saidi@ARM.com 15010030SAli.Saidi@ARM.com AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) 15110030SAli.Saidi@ARM.com : AtomicCPUPort(_name, _cpu), cpu(_cpu) 15210030SAli.Saidi@ARM.com { 15310030SAli.Saidi@ARM.com cacheBlockMask = ~(cpu->cacheLineSize() - 1); 15410030SAli.Saidi@ARM.com } 15510030SAli.Saidi@ARM.com 15610030SAli.Saidi@ARM.com bool isSnooping() const { return true; } 15710030SAli.Saidi@ARM.com 15810030SAli.Saidi@ARM.com Addr cacheBlockMask; 15910030SAli.Saidi@ARM.com protected: 16010030SAli.Saidi@ARM.com BaseSimpleCPU *cpu; 16110030SAli.Saidi@ARM.com 16210030SAli.Saidi@ARM.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 16310030SAli.Saidi@ARM.com virtual void recvFunctionalSnoop(PacketPtr pkt); 16410030SAli.Saidi@ARM.com }; 16510030SAli.Saidi@ARM.com 16610030SAli.Saidi@ARM.com 1678707Sandreas.hansson@arm.com AtomicCPUPort icachePort; 16810030SAli.Saidi@ARM.com AtomicCPUDPort dcachePort; 1692623SN/A 1708926Sandreas.hansson@arm.com bool fastmem; 1714870Sstever@eecs.umich.edu Request ifetch_req; 1724870Sstever@eecs.umich.edu Request data_read_req; 1734870Sstever@eecs.umich.edu Request data_write_req; 1742623SN/A 1752623SN/A bool dcache_access; 1762662Sstever@eecs.umich.edu Tick dcache_latency; 1772623SN/A 17810381Sdam.sunwoo@arm.com /** Probe Points. */ 17910381Sdam.sunwoo@arm.com ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit; 1809647Sdam.sunwoo@arm.com 1818850Sandreas.hansson@arm.com protected: 1828850Sandreas.hansson@arm.com 1838850Sandreas.hansson@arm.com /** Return a reference to the data port. */ 18411169Sandreas.hansson@arm.com MasterPort &getDataPort() override { return dcachePort; } 1858850Sandreas.hansson@arm.com 1868850Sandreas.hansson@arm.com /** Return a reference to the instruction port. */ 18711169Sandreas.hansson@arm.com MasterPort &getInstPort() override { return icachePort; } 1888850Sandreas.hansson@arm.com 18911148Smitch.hayenga@arm.com /** Perform snoop for other cpu-local thread contexts. */ 19011148Smitch.hayenga@arm.com void threadSnoop(PacketPtr pkt, ThreadID sender); 19111148Smitch.hayenga@arm.com 1922623SN/A public: 1932623SN/A 19411168Sandreas.hansson@arm.com DrainState drain() override; 19511168Sandreas.hansson@arm.com void drainResume() override; 1962623SN/A 19711169Sandreas.hansson@arm.com void switchOut() override; 19811169Sandreas.hansson@arm.com void takeOverFrom(BaseCPU *oldCPU) override; 1992623SN/A 20011169Sandreas.hansson@arm.com void verifyMemoryMode() const override; 2019523SAndreas.Sandberg@ARM.com 20211169Sandreas.hansson@arm.com void activateContext(ThreadID thread_num) override; 20311169Sandreas.hansson@arm.com void suspendContext(ThreadID thread_num) override; 2042623SN/A 20511169Sandreas.hansson@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, 20611608Snikos.nikoleris@arm.com Request::Flags flags) override; 2077520Sgblack@eecs.umich.edu 20811608Snikos.nikoleris@arm.com Fault initiateMemRead(Addr addr, unsigned size, 20911608Snikos.nikoleris@arm.com Request::Flags flags) override; 21011303Ssteve.reinhardt@amd.com 2118444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 21211608Snikos.nikoleris@arm.com Addr addr, Request::Flags flags, uint64_t *res) override; 2137520Sgblack@eecs.umich.edu 21411169Sandreas.hansson@arm.com void regProbePoints() override; 21510381Sdam.sunwoo@arm.com 2165315Sstever@gmail.com /** 2175315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 2185315Sstever@gmail.com * debugging). 2195315Sstever@gmail.com */ 2205315Sstever@gmail.com void printAddr(Addr a); 2212623SN/A}; 2222623SN/A 2232623SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 224