atomic.hh revision 11148
12623SN/A/* 211147Smitch.hayenga@arm.com * Copyright (c) 2012-2013,2015 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 432623SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 442623SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 452623SN/A 462623SN/A#include "cpu/simple/base.hh" 4711147Smitch.hayenga@arm.com#include "cpu/simple/exec_context.hh" 485529Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 4910381Sdam.sunwoo@arm.com#include "sim/probe/probe.hh" 509647Sdam.sunwoo@arm.com 512623SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 522623SN/A{ 532623SN/A public: 542623SN/A 555529Snate@binkert.org AtomicSimpleCPU(AtomicSimpleCPUParams *params); 562623SN/A virtual ~AtomicSimpleCPU(); 572623SN/A 582623SN/A virtual void init(); 592623SN/A 602623SN/A private: 612623SN/A 622623SN/A struct TickEvent : public Event 632623SN/A { 642623SN/A AtomicSimpleCPU *cpu; 652623SN/A 662623SN/A TickEvent(AtomicSimpleCPU *c); 672623SN/A void process(); 685336Shines@cs.fsu.edu const char *description() const; 692623SN/A }; 702623SN/A 712623SN/A TickEvent tickEvent; 722623SN/A 732623SN/A const int width; 746078Sgblack@eecs.umich.edu bool locked; 755487Snate@binkert.org const bool simulate_data_stalls; 765487Snate@binkert.org const bool simulate_inst_stalls; 772623SN/A 782623SN/A // main simulation loop (one cycle) 792623SN/A void tick(); 802623SN/A 818707Sandreas.hansson@arm.com /** 829443SAndreas.Sandberg@ARM.com * Check if a system is in a drained state. 839443SAndreas.Sandberg@ARM.com * 849443SAndreas.Sandberg@ARM.com * We need to drain if: 859443SAndreas.Sandberg@ARM.com * <ul> 869443SAndreas.Sandberg@ARM.com * <li>We are in the middle of a microcode sequence as some CPUs 879443SAndreas.Sandberg@ARM.com * (e.g., HW accelerated CPUs) can't be started in the middle 889443SAndreas.Sandberg@ARM.com * of a gem5 microcode sequence. 899443SAndreas.Sandberg@ARM.com * 909443SAndreas.Sandberg@ARM.com * <li>The CPU is in a LLSC region. This shouldn't normally happen 919443SAndreas.Sandberg@ARM.com * as these are executed atomically within a single tick() 929443SAndreas.Sandberg@ARM.com * call. The only way this can happen at the moment is if 939443SAndreas.Sandberg@ARM.com * there is an event in the PC event queue that affects the 949443SAndreas.Sandberg@ARM.com * CPU state while it is in an LLSC region. 959443SAndreas.Sandberg@ARM.com * 969443SAndreas.Sandberg@ARM.com * <li>Stay at PC is true. 979443SAndreas.Sandberg@ARM.com * </ul> 989443SAndreas.Sandberg@ARM.com */ 999443SAndreas.Sandberg@ARM.com bool isDrained() { 10011147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 10111147Smitch.hayenga@arm.com 10211147Smitch.hayenga@arm.com return t_info.thread->microPC() == 0 && 1039443SAndreas.Sandberg@ARM.com !locked && 10411147Smitch.hayenga@arm.com !t_info.stayAtPC; 1059443SAndreas.Sandberg@ARM.com } 1069443SAndreas.Sandberg@ARM.com 1079443SAndreas.Sandberg@ARM.com /** 1089443SAndreas.Sandberg@ARM.com * Try to complete a drain request. 1099443SAndreas.Sandberg@ARM.com * 1109443SAndreas.Sandberg@ARM.com * @returns true if the CPU is drained, false otherwise. 1119443SAndreas.Sandberg@ARM.com */ 1129443SAndreas.Sandberg@ARM.com bool tryCompleteDrain(); 1139443SAndreas.Sandberg@ARM.com 1149443SAndreas.Sandberg@ARM.com /** 1158707Sandreas.hansson@arm.com * An AtomicCPUPort overrides the default behaviour of the 1169608Sandreas.hansson@arm.com * recvAtomicSnoop and ignores the packet instead of panicking. It 1179608Sandreas.hansson@arm.com * also provides an implementation for the purely virtual timing 1189608Sandreas.hansson@arm.com * functions and panics on either of these. 1198707Sandreas.hansson@arm.com */ 1209608Sandreas.hansson@arm.com class AtomicCPUPort : public MasterPort 1212623SN/A { 1228707Sandreas.hansson@arm.com 1232623SN/A public: 1242623SN/A 12510030SAli.Saidi@ARM.com AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) 1269608Sandreas.hansson@arm.com : MasterPort(_name, _cpu) 1272623SN/A { } 1282623SN/A 1292623SN/A protected: 13010030SAli.Saidi@ARM.com virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; } 1313192Srdreslin@umich.edu 1329608Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) 1339608Sandreas.hansson@arm.com { 1349608Sandreas.hansson@arm.com panic("Atomic CPU doesn't expect recvTimingResp!\n"); 1359608Sandreas.hansson@arm.com return true; 1369608Sandreas.hansson@arm.com } 1379608Sandreas.hansson@arm.com 13810713Sandreas.hansson@arm.com void recvReqRetry() 1399608Sandreas.hansson@arm.com { 1409608Sandreas.hansson@arm.com panic("Atomic CPU doesn't expect recvRetry!\n"); 1419608Sandreas.hansson@arm.com } 1429608Sandreas.hansson@arm.com 1432623SN/A }; 1444192Sktlim@umich.edu 14510030SAli.Saidi@ARM.com class AtomicCPUDPort : public AtomicCPUPort 14610030SAli.Saidi@ARM.com { 14710030SAli.Saidi@ARM.com 14810030SAli.Saidi@ARM.com public: 14910030SAli.Saidi@ARM.com 15010030SAli.Saidi@ARM.com AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) 15110030SAli.Saidi@ARM.com : AtomicCPUPort(_name, _cpu), cpu(_cpu) 15210030SAli.Saidi@ARM.com { 15310030SAli.Saidi@ARM.com cacheBlockMask = ~(cpu->cacheLineSize() - 1); 15410030SAli.Saidi@ARM.com } 15510030SAli.Saidi@ARM.com 15610030SAli.Saidi@ARM.com bool isSnooping() const { return true; } 15710030SAli.Saidi@ARM.com 15810030SAli.Saidi@ARM.com Addr cacheBlockMask; 15910030SAli.Saidi@ARM.com protected: 16010030SAli.Saidi@ARM.com BaseSimpleCPU *cpu; 16110030SAli.Saidi@ARM.com 16210030SAli.Saidi@ARM.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 16310030SAli.Saidi@ARM.com virtual void recvFunctionalSnoop(PacketPtr pkt); 16410030SAli.Saidi@ARM.com }; 16510030SAli.Saidi@ARM.com 16610030SAli.Saidi@ARM.com 1678707Sandreas.hansson@arm.com AtomicCPUPort icachePort; 16810030SAli.Saidi@ARM.com AtomicCPUDPort dcachePort; 1692623SN/A 1708926Sandreas.hansson@arm.com bool fastmem; 1714870Sstever@eecs.umich.edu Request ifetch_req; 1724870Sstever@eecs.umich.edu Request data_read_req; 1734870Sstever@eecs.umich.edu Request data_write_req; 1742623SN/A 1752623SN/A bool dcache_access; 1762662Sstever@eecs.umich.edu Tick dcache_latency; 1772623SN/A 17810381Sdam.sunwoo@arm.com /** Probe Points. */ 17910381Sdam.sunwoo@arm.com ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit; 1809647Sdam.sunwoo@arm.com 1818850Sandreas.hansson@arm.com protected: 1828850Sandreas.hansson@arm.com 1838850Sandreas.hansson@arm.com /** Return a reference to the data port. */ 1849608Sandreas.hansson@arm.com virtual MasterPort &getDataPort() { return dcachePort; } 1858850Sandreas.hansson@arm.com 1868850Sandreas.hansson@arm.com /** Return a reference to the instruction port. */ 1879608Sandreas.hansson@arm.com virtual MasterPort &getInstPort() { return icachePort; } 1888850Sandreas.hansson@arm.com 18911148Smitch.hayenga@arm.com /** Perform snoop for other cpu-local thread contexts. */ 19011148Smitch.hayenga@arm.com void threadSnoop(PacketPtr pkt, ThreadID sender); 19111148Smitch.hayenga@arm.com 1922623SN/A public: 1932623SN/A 19410913Sandreas.sandberg@arm.com DrainState drain() M5_ATTR_OVERRIDE; 19510913Sandreas.sandberg@arm.com void drainResume() M5_ATTR_OVERRIDE; 1962623SN/A 1972798Sktlim@umich.edu void switchOut(); 1982623SN/A void takeOverFrom(BaseCPU *oldCPU); 1992623SN/A 2009523SAndreas.Sandberg@ARM.com void verifyMemoryMode() const; 2019523SAndreas.Sandberg@ARM.com 20210407Smitch.hayenga@arm.com virtual void activateContext(ThreadID thread_num); 2038737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num); 2042623SN/A 2058444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 2067520Sgblack@eecs.umich.edu 2078444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 2088444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 2097520Sgblack@eecs.umich.edu 21010381Sdam.sunwoo@arm.com virtual void regProbePoints(); 21110381Sdam.sunwoo@arm.com 2125315Sstever@gmail.com /** 2135315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 2145315Sstever@gmail.com * debugging). 2155315Sstever@gmail.com */ 2165315Sstever@gmail.com void printAddr(Addr a); 2172623SN/A}; 2182623SN/A 2192623SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 220