atomic.hh revision 10913
12623SN/A/* 29608Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 432623SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 442623SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 452623SN/A 462623SN/A#include "cpu/simple/base.hh" 475529Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 4810381Sdam.sunwoo@arm.com#include "sim/probe/probe.hh" 499647Sdam.sunwoo@arm.com 502623SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 512623SN/A{ 522623SN/A public: 532623SN/A 545529Snate@binkert.org AtomicSimpleCPU(AtomicSimpleCPUParams *params); 552623SN/A virtual ~AtomicSimpleCPU(); 562623SN/A 572623SN/A virtual void init(); 582623SN/A 592623SN/A private: 602623SN/A 612623SN/A struct TickEvent : public Event 622623SN/A { 632623SN/A AtomicSimpleCPU *cpu; 642623SN/A 652623SN/A TickEvent(AtomicSimpleCPU *c); 662623SN/A void process(); 675336Shines@cs.fsu.edu const char *description() const; 682623SN/A }; 692623SN/A 702623SN/A TickEvent tickEvent; 712623SN/A 722623SN/A const int width; 736078Sgblack@eecs.umich.edu bool locked; 745487Snate@binkert.org const bool simulate_data_stalls; 755487Snate@binkert.org const bool simulate_inst_stalls; 762623SN/A 772623SN/A // main simulation loop (one cycle) 782623SN/A void tick(); 792623SN/A 808707Sandreas.hansson@arm.com /** 819443SAndreas.Sandberg@ARM.com * Check if a system is in a drained state. 829443SAndreas.Sandberg@ARM.com * 839443SAndreas.Sandberg@ARM.com * We need to drain if: 849443SAndreas.Sandberg@ARM.com * <ul> 859443SAndreas.Sandberg@ARM.com * <li>We are in the middle of a microcode sequence as some CPUs 869443SAndreas.Sandberg@ARM.com * (e.g., HW accelerated CPUs) can't be started in the middle 879443SAndreas.Sandberg@ARM.com * of a gem5 microcode sequence. 889443SAndreas.Sandberg@ARM.com * 899443SAndreas.Sandberg@ARM.com * <li>The CPU is in a LLSC region. This shouldn't normally happen 909443SAndreas.Sandberg@ARM.com * as these are executed atomically within a single tick() 919443SAndreas.Sandberg@ARM.com * call. The only way this can happen at the moment is if 929443SAndreas.Sandberg@ARM.com * there is an event in the PC event queue that affects the 939443SAndreas.Sandberg@ARM.com * CPU state while it is in an LLSC region. 949443SAndreas.Sandberg@ARM.com * 959443SAndreas.Sandberg@ARM.com * <li>Stay at PC is true. 969443SAndreas.Sandberg@ARM.com * </ul> 979443SAndreas.Sandberg@ARM.com */ 989443SAndreas.Sandberg@ARM.com bool isDrained() { 999443SAndreas.Sandberg@ARM.com return microPC() == 0 && 1009443SAndreas.Sandberg@ARM.com !locked && 1019443SAndreas.Sandberg@ARM.com !stayAtPC; 1029443SAndreas.Sandberg@ARM.com } 1039443SAndreas.Sandberg@ARM.com 1049443SAndreas.Sandberg@ARM.com /** 1059443SAndreas.Sandberg@ARM.com * Try to complete a drain request. 1069443SAndreas.Sandberg@ARM.com * 1079443SAndreas.Sandberg@ARM.com * @returns true if the CPU is drained, false otherwise. 1089443SAndreas.Sandberg@ARM.com */ 1099443SAndreas.Sandberg@ARM.com bool tryCompleteDrain(); 1109443SAndreas.Sandberg@ARM.com 1119443SAndreas.Sandberg@ARM.com /** 1128707Sandreas.hansson@arm.com * An AtomicCPUPort overrides the default behaviour of the 1139608Sandreas.hansson@arm.com * recvAtomicSnoop and ignores the packet instead of panicking. It 1149608Sandreas.hansson@arm.com * also provides an implementation for the purely virtual timing 1159608Sandreas.hansson@arm.com * functions and panics on either of these. 1168707Sandreas.hansson@arm.com */ 1179608Sandreas.hansson@arm.com class AtomicCPUPort : public MasterPort 1182623SN/A { 1198707Sandreas.hansson@arm.com 1202623SN/A public: 1212623SN/A 12210030SAli.Saidi@ARM.com AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) 1239608Sandreas.hansson@arm.com : MasterPort(_name, _cpu) 1242623SN/A { } 1252623SN/A 1262623SN/A protected: 12710030SAli.Saidi@ARM.com virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; } 1283192Srdreslin@umich.edu 1299608Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) 1309608Sandreas.hansson@arm.com { 1319608Sandreas.hansson@arm.com panic("Atomic CPU doesn't expect recvTimingResp!\n"); 1329608Sandreas.hansson@arm.com return true; 1339608Sandreas.hansson@arm.com } 1349608Sandreas.hansson@arm.com 13510713Sandreas.hansson@arm.com void recvReqRetry() 1369608Sandreas.hansson@arm.com { 1379608Sandreas.hansson@arm.com panic("Atomic CPU doesn't expect recvRetry!\n"); 1389608Sandreas.hansson@arm.com } 1399608Sandreas.hansson@arm.com 1402623SN/A }; 1414192Sktlim@umich.edu 14210030SAli.Saidi@ARM.com class AtomicCPUDPort : public AtomicCPUPort 14310030SAli.Saidi@ARM.com { 14410030SAli.Saidi@ARM.com 14510030SAli.Saidi@ARM.com public: 14610030SAli.Saidi@ARM.com 14710030SAli.Saidi@ARM.com AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) 14810030SAli.Saidi@ARM.com : AtomicCPUPort(_name, _cpu), cpu(_cpu) 14910030SAli.Saidi@ARM.com { 15010030SAli.Saidi@ARM.com cacheBlockMask = ~(cpu->cacheLineSize() - 1); 15110030SAli.Saidi@ARM.com } 15210030SAli.Saidi@ARM.com 15310030SAli.Saidi@ARM.com bool isSnooping() const { return true; } 15410030SAli.Saidi@ARM.com 15510030SAli.Saidi@ARM.com Addr cacheBlockMask; 15610030SAli.Saidi@ARM.com protected: 15710030SAli.Saidi@ARM.com BaseSimpleCPU *cpu; 15810030SAli.Saidi@ARM.com 15910030SAli.Saidi@ARM.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 16010030SAli.Saidi@ARM.com virtual void recvFunctionalSnoop(PacketPtr pkt); 16110030SAli.Saidi@ARM.com }; 16210030SAli.Saidi@ARM.com 16310030SAli.Saidi@ARM.com 1648707Sandreas.hansson@arm.com AtomicCPUPort icachePort; 16510030SAli.Saidi@ARM.com AtomicCPUDPort dcachePort; 1662623SN/A 1678926Sandreas.hansson@arm.com bool fastmem; 1684870Sstever@eecs.umich.edu Request ifetch_req; 1694870Sstever@eecs.umich.edu Request data_read_req; 1704870Sstever@eecs.umich.edu Request data_write_req; 1712623SN/A 1722623SN/A bool dcache_access; 1732662Sstever@eecs.umich.edu Tick dcache_latency; 1742623SN/A 17510381Sdam.sunwoo@arm.com /** Probe Points. */ 17610381Sdam.sunwoo@arm.com ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit; 1779647Sdam.sunwoo@arm.com 1788850Sandreas.hansson@arm.com protected: 1798850Sandreas.hansson@arm.com 1808850Sandreas.hansson@arm.com /** Return a reference to the data port. */ 1819608Sandreas.hansson@arm.com virtual MasterPort &getDataPort() { return dcachePort; } 1828850Sandreas.hansson@arm.com 1838850Sandreas.hansson@arm.com /** Return a reference to the instruction port. */ 1849608Sandreas.hansson@arm.com virtual MasterPort &getInstPort() { return icachePort; } 1858850Sandreas.hansson@arm.com 1862623SN/A public: 1872623SN/A 18810913Sandreas.sandberg@arm.com DrainState drain() M5_ATTR_OVERRIDE; 18910913Sandreas.sandberg@arm.com void drainResume() M5_ATTR_OVERRIDE; 1902623SN/A 1912798Sktlim@umich.edu void switchOut(); 1922623SN/A void takeOverFrom(BaseCPU *oldCPU); 1932623SN/A 1949523SAndreas.Sandberg@ARM.com void verifyMemoryMode() const; 1959523SAndreas.Sandberg@ARM.com 19610407Smitch.hayenga@arm.com virtual void activateContext(ThreadID thread_num); 1978737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num); 1982623SN/A 1998444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 2007520Sgblack@eecs.umich.edu 2018444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 2028444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 2037520Sgblack@eecs.umich.edu 20410381Sdam.sunwoo@arm.com virtual void regProbePoints(); 20510381Sdam.sunwoo@arm.com 2065315Sstever@gmail.com /** 2075315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 2085315Sstever@gmail.com * debugging). 2095315Sstever@gmail.com */ 2105315Sstever@gmail.com void printAddr(Addr a); 2112623SN/A}; 2122623SN/A 2132623SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 214