AtomicSimpleCPU.py revision 5529
12124SN/A# Copyright (c) 2007 The Regents of The University of Michigan 22124SN/A# All rights reserved. 35268Sksewell@umich.edu# 45268Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without 55268Sksewell@umich.edu# modification, are permitted provided that the following conditions are 65268Sksewell@umich.edu# met: redistributions of source code must retain the above copyright 75268Sksewell@umich.edu# notice, this list of conditions and the following disclaimer; 85268Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright 95268Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the 105268Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 115268Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 125268Sksewell@umich.edu# contributors may be used to endorse or promote products derived from 135268Sksewell@umich.edu# this software without specific prior written permission. 145268Sksewell@umich.edu# 155268Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165268Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175268Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185268Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195268Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205268Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215268Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225268Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235268Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245268Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255268Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265268Sksewell@umich.edu# 275268Sksewell@umich.edu# Authors: Nathan Binkert 285268Sksewell@umich.edu 295268Sksewell@umich.edufrom m5.params import * 305268Sksewell@umich.edufrom m5 import build_env 312022SN/Afrom BaseSimpleCPU import BaseSimpleCPU 322649Ssaidi@eecs.umich.edu 332649Ssaidi@eecs.umich.educlass AtomicSimpleCPU(BaseSimpleCPU): 342706Sksewell@umich.edu type = 'AtomicSimpleCPU' 352649Ssaidi@eecs.umich.edu width = Param.Int(1, "CPU width") 362649Ssaidi@eecs.umich.edu simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 372022SN/A simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") 382124SN/A function_trace = Param.Bool(False, "Enable function trace") 392124SN/A function_trace_start = Param.Tick(0, "Cycle to start function trace") 402124SN/A if build_env['FULL_SYSTEM']: 412124SN/A profile = Param.Latency('0ns', "trace the kernel stack") 422124SN/A icache_port = Port("Instruction Port") 432124SN/A dcache_port = Port("Data Port") 442124SN/A physmem_port = Port("Physical Memory Port") 455736Snate@binkert.org _mem_ports = BaseSimpleCPU._mem_ports + \ 462239SN/A ['icache_port', 'dcache_port', 'physmem_port'] 472124SN/A