AtomicSimpleCPU.py revision 5487
12440SN/A# Copyright (c) 2007 The Regents of The University of Michigan 22440SN/A# All rights reserved. 32440SN/A# 42440SN/A# Redistribution and use in source and binary forms, with or without 52440SN/A# modification, are permitted provided that the following conditions are 62440SN/A# met: redistributions of source code must retain the above copyright 72440SN/A# notice, this list of conditions and the following disclaimer; 82440SN/A# redistributions in binary form must reproduce the above copyright 92440SN/A# notice, this list of conditions and the following disclaimer in the 102440SN/A# documentation and/or other materials provided with the distribution; 112440SN/A# neither the name of the copyright holders nor the names of its 122440SN/A# contributors may be used to endorse or promote products derived from 132440SN/A# this software without specific prior written permission. 142440SN/A# 152440SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162440SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172440SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182440SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192440SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202440SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212440SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222440SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232440SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242440SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252440SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262440SN/A# 272665Ssaidi@eecs.umich.edu# Authors: Nathan Binkert 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edufrom m5.params import * 302440SN/Afrom m5 import build_env 312440SN/Afrom BaseCPU import BaseCPU 322440SN/A 332440SN/Aclass AtomicSimpleCPU(BaseCPU): 342440SN/A type = 'AtomicSimpleCPU' 352440SN/A width = Param.Int(1, "CPU width") 362972Sgblack@eecs.umich.edu simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 376330Sgblack@eecs.umich.edu simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") 382440SN/A function_trace = Param.Bool(False, "Enable function trace") 395569Snate@binkert.org function_trace_start = Param.Tick(0, "Cycle to start function trace") 407720Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 413120Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 422440SN/A icache_port = Port("Instruction Port") 435569Snate@binkert.org dcache_port = Port("Data Port") 445569Snate@binkert.org physmem_port = Port("Physical Memory Port") 457720Sgblack@eecs.umich.edu _mem_ports = BaseCPU._mem_ports + \ 467720Sgblack@eecs.umich.edu ['icache_port', 'dcache_port', 'physmem_port'] 477720Sgblack@eecs.umich.edu