op_class.hh revision 10814
12SN/A/* 27760SGiacomo.Gabrielli@arm.com * Copyright (c) 2010 ARM Limited 37760SGiacomo.Gabrielli@arm.com * All rights reserved 47760SGiacomo.Gabrielli@arm.com * 57760SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67760SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77760SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87760SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97760SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107760SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117760SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127760SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137760SGiacomo.Gabrielli@arm.com * 141762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 404762Snate@binkert.org * Authors: Nathan Binkert 412SN/A */ 422SN/A 432410SN/A#ifndef __CPU__OP_CLASS_HH__ 442410SN/A#define __CPU__OP_CLASS_HH__ 452SN/A 464762Snate@binkert.org#include "enums/OpClass.hh" 474762Snate@binkert.org 484762Snate@binkert.org/* 494762Snate@binkert.org * Do a bunch of wonky stuff to maintain backward compatability so I 504762Snate@binkert.org * don't have to change code in a zillion places. 512SN/A */ 524762Snate@binkert.orgusing Enums::OpClass; 534762Snate@binkert.orgusing Enums::No_OpClass; 542SN/A 5510814Sandreas.hansson@arm.comstatic const OpClass IntAluOp = Enums::IntAlu; 5610814Sandreas.hansson@arm.comstatic const OpClass IntMultOp = Enums::IntMult; 5710814Sandreas.hansson@arm.comstatic const OpClass IntDivOp = Enums::IntDiv; 5810814Sandreas.hansson@arm.comstatic const OpClass FloatAddOp = Enums::FloatAdd; 5910814Sandreas.hansson@arm.comstatic const OpClass FloatCmpOp = Enums::FloatCmp; 6010814Sandreas.hansson@arm.comstatic const OpClass FloatCvtOp = Enums::FloatCvt; 6110814Sandreas.hansson@arm.comstatic const OpClass FloatMultOp = Enums::FloatMult; 6210814Sandreas.hansson@arm.comstatic const OpClass FloatDivOp = Enums::FloatDiv; 6310814Sandreas.hansson@arm.comstatic const OpClass FloatSqrtOp = Enums::FloatSqrt; 6410814Sandreas.hansson@arm.comstatic const OpClass SimdAddOp = Enums::SimdAdd; 6510814Sandreas.hansson@arm.comstatic const OpClass SimdAddAccOp = Enums::SimdAddAcc; 6610814Sandreas.hansson@arm.comstatic const OpClass SimdAluOp = Enums::SimdAlu; 6710814Sandreas.hansson@arm.comstatic const OpClass SimdCmpOp = Enums::SimdCmp; 6810814Sandreas.hansson@arm.comstatic const OpClass SimdCvtOp = Enums::SimdCvt; 6910814Sandreas.hansson@arm.comstatic const OpClass SimdMiscOp = Enums::SimdMisc; 7010814Sandreas.hansson@arm.comstatic const OpClass SimdMultOp = Enums::SimdMult; 7110814Sandreas.hansson@arm.comstatic const OpClass SimdMultAccOp = Enums::SimdMultAcc; 7210814Sandreas.hansson@arm.comstatic const OpClass SimdShiftOp = Enums::SimdShift; 7310814Sandreas.hansson@arm.comstatic const OpClass SimdShiftAccOp = Enums::SimdShiftAcc; 7410814Sandreas.hansson@arm.comstatic const OpClass SimdSqrtOp = Enums::SimdSqrt; 7510814Sandreas.hansson@arm.comstatic const OpClass SimdFloatAddOp = Enums::SimdFloatAdd; 7610814Sandreas.hansson@arm.comstatic const OpClass SimdFloatAluOp = Enums::SimdFloatAlu; 7710814Sandreas.hansson@arm.comstatic const OpClass SimdFloatCmpOp = Enums::SimdFloatCmp; 7810814Sandreas.hansson@arm.comstatic const OpClass SimdFloatCvtOp = Enums::SimdFloatCvt; 7910814Sandreas.hansson@arm.comstatic const OpClass SimdFloatDivOp = Enums::SimdFloatDiv; 8010814Sandreas.hansson@arm.comstatic const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc; 8110814Sandreas.hansson@arm.comstatic const OpClass SimdFloatMultOp = Enums::SimdFloatMult; 8210814Sandreas.hansson@arm.comstatic const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc; 8310814Sandreas.hansson@arm.comstatic const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt; 8410814Sandreas.hansson@arm.comstatic const OpClass MemReadOp = Enums::MemRead; 8510814Sandreas.hansson@arm.comstatic const OpClass MemWriteOp = Enums::MemWrite; 8610814Sandreas.hansson@arm.comstatic const OpClass IprAccessOp = Enums::IprAccess; 8710814Sandreas.hansson@arm.comstatic const OpClass InstPrefetchOp = Enums::InstPrefetch; 8810814Sandreas.hansson@arm.comstatic const OpClass Num_OpClasses = Enums::Num_OpClass; 892SN/A 902410SN/A#endif // __CPU__OP_CLASS_HH__ 91