thread_context.hh revision 8777:dd43f1c9fa0a
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 32#define __CPU_O3_THREAD_CONTEXT_HH__ 33 34#include "config/the_isa.hh" 35#include "cpu/o3/isa_specific.hh" 36#include "cpu/thread_context.hh" 37 38class EndQuiesceEvent; 39namespace Kernel { 40 class Statistics; 41}; 42 43class TranslatingPort; 44 45/** 46 * Derived ThreadContext class for use with the O3CPU. It 47 * provides the interface for any external objects to access a 48 * single thread's state and some general CPU state. Any time 49 * external objects try to update state through this interface, 50 * the CPU will create an event to squash all in-flight 51 * instructions in order to ensure state is maintained correctly. 52 * It must be defined specifically for the O3CPU because 53 * not all architectural state is located within the O3ThreadState 54 * (such as the commit PC, and registers), and specific actions 55 * must be taken when using this interface (such as squashing all 56 * in-flight instructions when doing a write to this interface). 57 */ 58template <class Impl> 59class O3ThreadContext : public ThreadContext 60{ 61 public: 62 typedef typename Impl::O3CPU O3CPU; 63 64 /** Pointer to the CPU. */ 65 O3CPU *cpu; 66 67 /** Pointer to the thread state that this TC corrseponds to. */ 68 O3ThreadState<Impl> *thread; 69 70 /** Returns a pointer to the ITB. */ 71 TheISA::TLB *getITBPtr() { return cpu->itb; } 72 73 /** Returns a pointer to the DTB. */ 74 TheISA::TLB *getDTBPtr() { return cpu->dtb; } 75 76 Decoder *getDecoderPtr() { return &cpu->fetch.decoder; } 77 78 /** Returns a pointer to this CPU. */ 79 virtual BaseCPU *getCpuPtr() { return cpu; } 80 81 /** Reads this CPU's ID. */ 82 virtual int cpuId() { return cpu->cpuId(); } 83 84 virtual int contextId() { return thread->contextId(); } 85 86 virtual void setContextId(int id) { thread->setContextId(id); } 87 88 /** Returns this thread's ID number. */ 89 virtual int threadId() { return thread->threadId(); } 90 virtual void setThreadId(int id) { return thread->setThreadId(id); } 91 92 /** Returns a pointer to the system. */ 93 virtual System *getSystemPtr() { return cpu->system; } 94 95 /** Returns a pointer to this thread's kernel statistics. */ 96 virtual TheISA::Kernel::Statistics *getKernelStats() 97 { return thread->kernelStats; } 98 99 virtual void connectMemPorts(ThreadContext *tc) 100 { thread->connectMemPorts(tc); } 101 102 /** Returns a pointer to this thread's process. */ 103 virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 104 105 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } 106 107 virtual VirtualPort *getVirtPort(); 108 109 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } 110 111 /** Returns this thread's status. */ 112 virtual Status status() const { return thread->status(); } 113 114 /** Sets this thread's status. */ 115 virtual void setStatus(Status new_status) 116 { thread->setStatus(new_status); } 117 118 /** Set the status to Active. Optional delay indicates number of 119 * cycles to wait before beginning execution. */ 120 virtual void activate(int delay = 1); 121 122 /** Set the status to Suspended. */ 123 virtual void suspend(int delay = 0); 124 125 /** Set the status to Halted. */ 126 virtual void halt(int delay = 0); 127 128 /** Dumps the function profiling information. 129 * @todo: Implement. 130 */ 131 virtual void dumpFuncProfile(); 132 133 /** Takes over execution of a thread from another CPU. */ 134 virtual void takeOverFrom(ThreadContext *old_context); 135 136 /** Registers statistics associated with this TC. */ 137 virtual void regStats(const std::string &name); 138 139 /** Serializes state. */ 140 virtual void serialize(std::ostream &os); 141 /** Unserializes state. */ 142 virtual void unserialize(Checkpoint *cp, const std::string §ion); 143 144 /** Reads the last tick that this thread was activated on. */ 145 virtual Tick readLastActivate(); 146 /** Reads the last tick that this thread was suspended on. */ 147 virtual Tick readLastSuspend(); 148 149 /** Clears the function profiling information. */ 150 virtual void profileClear(); 151 /** Samples the function profiling information. */ 152 virtual void profileSample(); 153 154 /** Copies the architectural registers from another TC into this TC. */ 155 virtual void copyArchRegs(ThreadContext *tc); 156 157 /** Resets all architectural registers to 0. */ 158 virtual void clearArchRegs(); 159 160 /** Reads an integer register. */ 161 virtual uint64_t readIntReg(int reg_idx); 162 163 virtual FloatReg readFloatReg(int reg_idx); 164 165 virtual FloatRegBits readFloatRegBits(int reg_idx); 166 167 /** Sets an integer register to a value. */ 168 virtual void setIntReg(int reg_idx, uint64_t val); 169 170 virtual void setFloatReg(int reg_idx, FloatReg val); 171 172 virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 173 174 /** Reads this thread's PC state. */ 175 virtual TheISA::PCState pcState() 176 { return cpu->pcState(thread->threadId()); } 177 178 /** Sets this thread's PC state. */ 179 virtual void pcState(const TheISA::PCState &val); 180 181 /** Reads this thread's PC. */ 182 virtual Addr instAddr() 183 { return cpu->instAddr(thread->threadId()); } 184 185 /** Reads this thread's next PC. */ 186 virtual Addr nextInstAddr() 187 { return cpu->nextInstAddr(thread->threadId()); } 188 189 /** Reads this thread's next PC. */ 190 virtual MicroPC microPC() 191 { return cpu->microPC(thread->threadId()); } 192 193 /** Reads a miscellaneous register. */ 194 virtual MiscReg readMiscRegNoEffect(int misc_reg) 195 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 196 197 /** Reads a misc. register, including any side-effects the 198 * read might have as defined by the architecture. */ 199 virtual MiscReg readMiscReg(int misc_reg) 200 { return cpu->readMiscReg(misc_reg, thread->threadId()); } 201 202 /** Sets a misc. register. */ 203 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 204 205 /** Sets a misc. register, including any side-effects the 206 * write might have as defined by the architecture. */ 207 virtual void setMiscReg(int misc_reg, const MiscReg &val); 208 209 virtual int flattenIntIndex(int reg); 210 virtual int flattenFloatIndex(int reg); 211 212 /** Returns the number of consecutive store conditional failures. */ 213 // @todo: Figure out where these store cond failures should go. 214 virtual unsigned readStCondFailures() 215 { return thread->storeCondFailures; } 216 217 /** Sets the number of consecutive store conditional failures. */ 218 virtual void setStCondFailures(unsigned sc_failures) 219 { thread->storeCondFailures = sc_failures; } 220 221 // Only really makes sense for old CPU model. Lots of code 222 // outside the CPU still checks this function, so it will 223 // always return false to keep everything working. 224 /** Checks if the thread is misspeculating. Because it is 225 * very difficult to determine if the thread is 226 * misspeculating, this is set as false. */ 227 virtual bool misspeculating() { return false; } 228 229 /** Executes a syscall in SE mode. */ 230 virtual void syscall(int64_t callnum) 231 { return cpu->syscall(callnum, thread->threadId()); } 232 233 /** Reads the funcExeInst counter. */ 234 virtual Counter readFuncExeInst() { return thread->funcExeInst; } 235 236 /** Returns pointer to the quiesce event. */ 237 virtual EndQuiesceEvent *getQuiesceEvent() 238 { 239 return this->thread->quiesceEvent; 240 } 241 242}; 243 244#endif 245