thread_context.hh revision 7720:65d338a8dba4
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_THREAD_CONTEXT_HH__
32#define __CPU_O3_THREAD_CONTEXT_HH__
33
34#include "config/the_isa.hh"
35#include "cpu/thread_context.hh"
36#include "cpu/o3/isa_specific.hh"
37
38class EndQuiesceEvent;
39namespace Kernel {
40    class Statistics;
41};
42
43class TranslatingPort;
44
45/**
46 * Derived ThreadContext class for use with the O3CPU.  It
47 * provides the interface for any external objects to access a
48 * single thread's state and some general CPU state.  Any time
49 * external objects try to update state through this interface,
50 * the CPU will create an event to squash all in-flight
51 * instructions in order to ensure state is maintained correctly.
52 * It must be defined specifically for the O3CPU because
53 * not all architectural state is located within the O3ThreadState
54 * (such as the commit PC, and registers), and specific actions
55 * must be taken when using this interface (such as squashing all
56 * in-flight instructions when doing a write to this interface).
57 */
58template <class Impl>
59class O3ThreadContext : public ThreadContext
60{
61  public:
62    typedef typename Impl::O3CPU O3CPU;
63
64   /** Pointer to the CPU. */
65    O3CPU *cpu;
66
67    /** Pointer to the thread state that this TC corrseponds to. */
68    O3ThreadState<Impl> *thread;
69
70    /** Returns a pointer to the ITB. */
71    TheISA::TLB *getITBPtr() { return cpu->itb; }
72
73    /** Returns a pointer to the DTB. */
74    TheISA::TLB *getDTBPtr() { return cpu->dtb; }
75
76    /** Returns a pointer to this CPU. */
77    virtual BaseCPU *getCpuPtr() { return cpu; }
78
79    /** Reads this CPU's ID. */
80    virtual int cpuId() { return cpu->cpuId(); }
81
82    virtual int contextId() { return thread->contextId(); }
83
84    virtual void setContextId(int id) { thread->setContextId(id); }
85
86    /** Returns this thread's ID number. */
87    virtual int threadId() { return thread->threadId(); }
88    virtual void setThreadId(int id) { return thread->setThreadId(id); }
89
90    /** Returns a pointer to the system. */
91    virtual System *getSystemPtr() { return cpu->system; }
92
93#if FULL_SYSTEM
94    /** Returns a pointer to this thread's kernel statistics. */
95    virtual TheISA::Kernel::Statistics *getKernelStats()
96    { return thread->kernelStats; }
97
98    virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
99
100    virtual VirtualPort *getVirtPort();
101
102    virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
103#else
104    virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
105
106    /** Returns a pointer to this thread's process. */
107    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
108#endif
109    /** Returns this thread's status. */
110    virtual Status status() const { return thread->status(); }
111
112    /** Sets this thread's status. */
113    virtual void setStatus(Status new_status)
114    { thread->setStatus(new_status); }
115
116    /** Set the status to Active.  Optional delay indicates number of
117     * cycles to wait before beginning execution. */
118    virtual void activate(int delay = 1);
119
120    /** Set the status to Suspended. */
121    virtual void suspend(int delay = 0);
122
123    /** Set the status to Halted. */
124    virtual void halt(int delay = 0);
125
126#if FULL_SYSTEM
127    /** Dumps the function profiling information.
128     * @todo: Implement.
129     */
130    virtual void dumpFuncProfile();
131#endif
132    /** Takes over execution of a thread from another CPU. */
133    virtual void takeOverFrom(ThreadContext *old_context);
134
135    /** Registers statistics associated with this TC. */
136    virtual void regStats(const std::string &name);
137
138    /** Serializes state. */
139    virtual void serialize(std::ostream &os);
140    /** Unserializes state. */
141    virtual void unserialize(Checkpoint *cp, const std::string &section);
142
143#if FULL_SYSTEM
144    /** Reads the last tick that this thread was activated on. */
145    virtual Tick readLastActivate();
146    /** Reads the last tick that this thread was suspended on. */
147    virtual Tick readLastSuspend();
148
149    /** Clears the function profiling information. */
150    virtual void profileClear();
151    /** Samples the function profiling information. */
152    virtual void profileSample();
153#endif
154
155    /** Copies the architectural registers from another TC into this TC. */
156    virtual void copyArchRegs(ThreadContext *tc);
157
158    /** Resets all architectural registers to 0. */
159    virtual void clearArchRegs();
160
161    /** Reads an integer register. */
162    virtual uint64_t readIntReg(int reg_idx);
163
164    virtual FloatReg readFloatReg(int reg_idx);
165
166    virtual FloatRegBits readFloatRegBits(int reg_idx);
167
168    /** Sets an integer register to a value. */
169    virtual void setIntReg(int reg_idx, uint64_t val);
170
171    virtual void setFloatReg(int reg_idx, FloatReg val);
172
173    virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
174
175    /** Reads this thread's PC state. */
176    virtual TheISA::PCState pcState()
177    { return cpu->pcState(thread->threadId()); }
178
179    /** Sets this thread's PC state. */
180    virtual void pcState(const TheISA::PCState &val);
181
182    /** Reads this thread's PC. */
183    virtual Addr instAddr()
184    { return cpu->instAddr(thread->threadId()); }
185
186    /** Reads this thread's next PC. */
187    virtual Addr nextInstAddr()
188    { return cpu->nextInstAddr(thread->threadId()); }
189
190    /** Reads this thread's next PC. */
191    virtual MicroPC microPC()
192    { return cpu->microPC(thread->threadId()); }
193
194    /** Reads a miscellaneous register. */
195    virtual MiscReg readMiscRegNoEffect(int misc_reg)
196    { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
197
198    /** Reads a misc. register, including any side-effects the
199     * read might have as defined by the architecture. */
200    virtual MiscReg readMiscReg(int misc_reg)
201    { return cpu->readMiscReg(misc_reg, thread->threadId()); }
202
203    /** Sets a misc. register. */
204    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
205
206    /** Sets a misc. register, including any side-effects the
207     * write might have as defined by the architecture. */
208    virtual void setMiscReg(int misc_reg, const MiscReg &val);
209
210    virtual int flattenIntIndex(int reg);
211    virtual int flattenFloatIndex(int reg);
212
213    /** Returns the number of consecutive store conditional failures. */
214    // @todo: Figure out where these store cond failures should go.
215    virtual unsigned readStCondFailures()
216    { return thread->storeCondFailures; }
217
218    /** Sets the number of consecutive store conditional failures. */
219    virtual void setStCondFailures(unsigned sc_failures)
220    { thread->storeCondFailures = sc_failures; }
221
222    // Only really makes sense for old CPU model.  Lots of code
223    // outside the CPU still checks this function, so it will
224    // always return false to keep everything working.
225    /** Checks if the thread is misspeculating.  Because it is
226     * very difficult to determine if the thread is
227     * misspeculating, this is set as false. */
228    virtual bool misspeculating() { return false; }
229
230#if !FULL_SYSTEM
231    /** Executes a syscall in SE mode. */
232    virtual void syscall(int64_t callnum)
233    { return cpu->syscall(callnum, thread->threadId()); }
234
235    /** Reads the funcExeInst counter. */
236    virtual Counter readFuncExeInst() { return thread->funcExeInst; }
237#else
238    /** Returns pointer to the quiesce event. */
239    virtual EndQuiesceEvent *getQuiesceEvent()
240    {
241        return this->thread->quiesceEvent;
242    }
243#endif
244
245};
246
247#endif
248