thread_context.hh revision 6314:781969fbeca9
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_THREAD_CONTEXT_HH__
32#define __CPU_O3_THREAD_CONTEXT_HH__
33
34#include "cpu/thread_context.hh"
35#include "cpu/o3/isa_specific.hh"
36
37class EndQuiesceEvent;
38namespace Kernel {
39    class Statistics;
40};
41
42class TranslatingPort;
43
44/**
45 * Derived ThreadContext class for use with the O3CPU.  It
46 * provides the interface for any external objects to access a
47 * single thread's state and some general CPU state.  Any time
48 * external objects try to update state through this interface,
49 * the CPU will create an event to squash all in-flight
50 * instructions in order to ensure state is maintained correctly.
51 * It must be defined specifically for the O3CPU because
52 * not all architectural state is located within the O3ThreadState
53 * (such as the commit PC, and registers), and specific actions
54 * must be taken when using this interface (such as squashing all
55 * in-flight instructions when doing a write to this interface).
56 */
57template <class Impl>
58class O3ThreadContext : public ThreadContext
59{
60  public:
61    typedef typename Impl::O3CPU O3CPU;
62
63   /** Pointer to the CPU. */
64    O3CPU *cpu;
65
66    /** Pointer to the thread state that this TC corrseponds to. */
67    O3ThreadState<Impl> *thread;
68
69    /** Returns a pointer to the ITB. */
70    TheISA::TLB *getITBPtr() { return cpu->itb; }
71
72    /** Returns a pointer to the DTB. */
73    TheISA::TLB *getDTBPtr() { return cpu->dtb; }
74
75    /** Returns a pointer to this CPU. */
76    virtual BaseCPU *getCpuPtr() { return cpu; }
77
78    /** Reads this CPU's ID. */
79    virtual int cpuId() { return cpu->cpuId(); }
80
81    virtual int contextId() { return thread->contextId(); }
82
83    virtual void setContextId(int id) { thread->setContextId(id); }
84
85    /** Returns this thread's ID number. */
86    virtual int threadId() { return thread->threadId(); }
87    virtual void setThreadId(int id) { return thread->setThreadId(id); }
88
89    /** Returns a pointer to the system. */
90    virtual System *getSystemPtr() { return cpu->system; }
91
92#if FULL_SYSTEM
93    /** Returns a pointer to physical memory. */
94    virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
95
96    /** Returns a pointer to this thread's kernel statistics. */
97    virtual TheISA::Kernel::Statistics *getKernelStats()
98    { return thread->kernelStats; }
99
100    virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
101
102    virtual VirtualPort *getVirtPort();
103
104    virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
105#else
106    virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
107
108    /** Returns a pointer to this thread's process. */
109    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
110#endif
111    /** Returns this thread's status. */
112    virtual Status status() const { return thread->status(); }
113
114    /** Sets this thread's status. */
115    virtual void setStatus(Status new_status)
116    { thread->setStatus(new_status); }
117
118    /** Set the status to Active.  Optional delay indicates number of
119     * cycles to wait before beginning execution. */
120    virtual void activate(int delay = 1);
121
122    /** Set the status to Suspended. */
123    virtual void suspend(int delay = 0);
124
125    /** Set the status to Halted. */
126    virtual void halt(int delay = 0);
127
128#if FULL_SYSTEM
129    /** Dumps the function profiling information.
130     * @todo: Implement.
131     */
132    virtual void dumpFuncProfile();
133#endif
134    /** Takes over execution of a thread from another CPU. */
135    virtual void takeOverFrom(ThreadContext *old_context);
136
137    /** Registers statistics associated with this TC. */
138    virtual void regStats(const std::string &name);
139
140    /** Serializes state. */
141    virtual void serialize(std::ostream &os);
142    /** Unserializes state. */
143    virtual void unserialize(Checkpoint *cp, const std::string &section);
144
145#if FULL_SYSTEM
146    /** Reads the last tick that this thread was activated on. */
147    virtual Tick readLastActivate();
148    /** Reads the last tick that this thread was suspended on. */
149    virtual Tick readLastSuspend();
150
151    /** Clears the function profiling information. */
152    virtual void profileClear();
153    /** Samples the function profiling information. */
154    virtual void profileSample();
155#endif
156    /** Returns the instruction this thread is currently committing.
157     *  Only used when an instruction faults.
158     */
159    virtual TheISA::MachInst getInst();
160
161    /** Copies the architectural registers from another TC into this TC. */
162    virtual void copyArchRegs(ThreadContext *tc);
163
164    /** Resets all architectural registers to 0. */
165    virtual void clearArchRegs();
166
167    /** Reads an integer register. */
168    virtual uint64_t readIntReg(int reg_idx);
169
170    virtual FloatReg readFloatReg(int reg_idx);
171
172    virtual FloatRegBits readFloatRegBits(int reg_idx);
173
174    /** Sets an integer register to a value. */
175    virtual void setIntReg(int reg_idx, uint64_t val);
176
177    virtual void setFloatReg(int reg_idx, FloatReg val);
178
179    virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
180
181    /** Reads this thread's PC. */
182    virtual uint64_t readPC()
183    { return cpu->readPC(thread->threadId()); }
184
185    /** Sets this thread's PC. */
186    virtual void setPC(uint64_t val);
187
188    /** Reads this thread's next PC. */
189    virtual uint64_t readNextPC()
190    { return cpu->readNextPC(thread->threadId()); }
191
192    /** Sets this thread's next PC. */
193    virtual void setNextPC(uint64_t val);
194
195    virtual uint64_t readMicroPC()
196    { return cpu->readMicroPC(thread->threadId()); }
197
198    virtual void setMicroPC(uint64_t val);
199
200    virtual uint64_t readNextMicroPC()
201    { return cpu->readNextMicroPC(thread->threadId()); }
202
203    virtual void setNextMicroPC(uint64_t val);
204
205    /** Reads a miscellaneous register. */
206    virtual MiscReg readMiscRegNoEffect(int misc_reg)
207    { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
208
209    /** Reads a misc. register, including any side-effects the
210     * read might have as defined by the architecture. */
211    virtual MiscReg readMiscReg(int misc_reg)
212    { return cpu->readMiscReg(misc_reg, thread->threadId()); }
213
214    /** Sets a misc. register. */
215    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
216
217    /** Sets a misc. register, including any side-effects the
218     * write might have as defined by the architecture. */
219    virtual void setMiscReg(int misc_reg, const MiscReg &val);
220
221    virtual int flattenIntIndex(int reg);
222    virtual int flattenFloatIndex(int reg);
223
224    /** Returns the number of consecutive store conditional failures. */
225    // @todo: Figure out where these store cond failures should go.
226    virtual unsigned readStCondFailures()
227    { return thread->storeCondFailures; }
228
229    /** Sets the number of consecutive store conditional failures. */
230    virtual void setStCondFailures(unsigned sc_failures)
231    { thread->storeCondFailures = sc_failures; }
232
233    // Only really makes sense for old CPU model.  Lots of code
234    // outside the CPU still checks this function, so it will
235    // always return false to keep everything working.
236    /** Checks if the thread is misspeculating.  Because it is
237     * very difficult to determine if the thread is
238     * misspeculating, this is set as false. */
239    virtual bool misspeculating() { return false; }
240
241#if !FULL_SYSTEM
242    /** Executes a syscall in SE mode. */
243    virtual void syscall(int64_t callnum)
244    { return cpu->syscall(callnum, thread->threadId()); }
245
246    /** Reads the funcExeInst counter. */
247    virtual Counter readFuncExeInst() { return thread->funcExeInst; }
248#else
249    /** Returns pointer to the quiesce event. */
250    virtual EndQuiesceEvent *getQuiesceEvent()
251    {
252        return this->thread->quiesceEvent;
253    }
254#endif
255
256    virtual uint64_t readNextNPC()
257    {
258        return this->cpu->readNextNPC(this->thread->threadId());
259    }
260
261    virtual void setNextNPC(uint64_t val)
262    {
263        this->cpu->setNextNPC(val, this->thread->threadId());
264    }
265};
266
267#endif
268