thread_context.hh revision 5712
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_THREAD_CONTEXT_HH__
32#define __CPU_O3_THREAD_CONTEXT_HH__
33
34#include "cpu/thread_context.hh"
35#include "cpu/o3/isa_specific.hh"
36
37class EndQuiesceEvent;
38namespace Kernel {
39    class Statistics;
40};
41
42class TranslatingPort;
43
44/**
45 * Derived ThreadContext class for use with the O3CPU.  It
46 * provides the interface for any external objects to access a
47 * single thread's state and some general CPU state.  Any time
48 * external objects try to update state through this interface,
49 * the CPU will create an event to squash all in-flight
50 * instructions in order to ensure state is maintained correctly.
51 * It must be defined specifically for the O3CPU because
52 * not all architectural state is located within the O3ThreadState
53 * (such as the commit PC, and registers), and specific actions
54 * must be taken when using this interface (such as squashing all
55 * in-flight instructions when doing a write to this interface).
56 */
57template <class Impl>
58class O3ThreadContext : public ThreadContext
59{
60  public:
61    typedef typename Impl::O3CPU O3CPU;
62
63   /** Pointer to the CPU. */
64    O3CPU *cpu;
65
66    /** Pointer to the thread state that this TC corrseponds to. */
67    O3ThreadState<Impl> *thread;
68
69    /** Returns a pointer to the ITB. */
70    TheISA::ITB *getITBPtr() { return cpu->itb; }
71
72    /** Returns a pointer to the DTB. */
73    TheISA::DTB *getDTBPtr() { return cpu->dtb; }
74
75    /** Returns a pointer to this CPU. */
76    virtual BaseCPU *getCpuPtr() { return cpu; }
77
78    /** Reads this CPU's ID. */
79    virtual int cpuId() { return cpu->cpuId(); }
80
81#if FULL_SYSTEM
82    /** Returns a pointer to the system. */
83    virtual System *getSystemPtr() { return cpu->system; }
84
85    /** Returns a pointer to physical memory. */
86    virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
87
88    /** Returns a pointer to this thread's kernel statistics. */
89    virtual TheISA::Kernel::Statistics *getKernelStats()
90    { return thread->kernelStats; }
91
92    virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
93
94    virtual VirtualPort *getVirtPort();
95
96    virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
97#else
98    virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
99
100    /** Returns a pointer to this thread's process. */
101    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
102#endif
103    /** Returns this thread's status. */
104    virtual Status status() const { return thread->status(); }
105
106    /** Sets this thread's status. */
107    virtual void setStatus(Status new_status)
108    { thread->setStatus(new_status); }
109
110    /** Set the status to Active.  Optional delay indicates number of
111     * cycles to wait before beginning execution. */
112    virtual void activate(int delay = 1);
113
114    /** Set the status to Suspended. */
115    virtual void suspend(int delay = 0);
116
117    /** Set the status to Unallocated. */
118    virtual void deallocate(int delay = 0);
119
120    /** Set the status to Halted. */
121    virtual void halt(int delay = 0);
122
123#if FULL_SYSTEM
124    /** Dumps the function profiling information.
125     * @todo: Implement.
126     */
127    virtual void dumpFuncProfile();
128#endif
129    /** Takes over execution of a thread from another CPU. */
130    virtual void takeOverFrom(ThreadContext *old_context);
131
132    /** Registers statistics associated with this TC. */
133    virtual void regStats(const std::string &name);
134
135    /** Serializes state. */
136    virtual void serialize(std::ostream &os);
137    /** Unserializes state. */
138    virtual void unserialize(Checkpoint *cp, const std::string &section);
139
140#if FULL_SYSTEM
141    /** Reads the last tick that this thread was activated on. */
142    virtual Tick readLastActivate();
143    /** Reads the last tick that this thread was suspended on. */
144    virtual Tick readLastSuspend();
145
146    /** Clears the function profiling information. */
147    virtual void profileClear();
148    /** Samples the function profiling information. */
149    virtual void profileSample();
150#endif
151    /** Returns this thread's ID number. */
152    virtual int getThreadNum() { return thread->readTid(); }
153
154    /** Returns the instruction this thread is currently committing.
155     *  Only used when an instruction faults.
156     */
157    virtual TheISA::MachInst getInst();
158
159    /** Copies the architectural registers from another TC into this TC. */
160    virtual void copyArchRegs(ThreadContext *tc);
161
162    /** Resets all architectural registers to 0. */
163    virtual void clearArchRegs();
164
165    /** Reads an integer register. */
166    virtual uint64_t readIntReg(int reg_idx);
167
168    virtual FloatReg readFloatReg(int reg_idx, int width);
169
170    virtual FloatReg readFloatReg(int reg_idx);
171
172    virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
173
174    virtual FloatRegBits readFloatRegBits(int reg_idx);
175
176    /** Sets an integer register to a value. */
177    virtual void setIntReg(int reg_idx, uint64_t val);
178
179    virtual void setFloatReg(int reg_idx, FloatReg val, int width);
180
181    virtual void setFloatReg(int reg_idx, FloatReg val);
182
183    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
184
185    virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
186
187    /** Reads this thread's PC. */
188    virtual uint64_t readPC()
189    { return cpu->readPC(thread->readTid()); }
190
191    /** Sets this thread's PC. */
192    virtual void setPC(uint64_t val);
193
194    /** Reads this thread's next PC. */
195    virtual uint64_t readNextPC()
196    { return cpu->readNextPC(thread->readTid()); }
197
198    /** Sets this thread's next PC. */
199    virtual void setNextPC(uint64_t val);
200
201    virtual uint64_t readMicroPC()
202    { return cpu->readMicroPC(thread->readTid()); }
203
204    virtual void setMicroPC(uint64_t val);
205
206    virtual uint64_t readNextMicroPC()
207    { return cpu->readNextMicroPC(thread->readTid()); }
208
209    virtual void setNextMicroPC(uint64_t val);
210
211    /** Reads a miscellaneous register. */
212    virtual MiscReg readMiscRegNoEffect(int misc_reg)
213    { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
214
215    /** Reads a misc. register, including any side-effects the
216     * read might have as defined by the architecture. */
217    virtual MiscReg readMiscReg(int misc_reg)
218    { return cpu->readMiscReg(misc_reg, thread->readTid()); }
219
220    /** Sets a misc. register. */
221    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
222
223    /** Sets a misc. register, including any side-effects the
224     * write might have as defined by the architecture. */
225    virtual void setMiscReg(int misc_reg, const MiscReg &val);
226
227    /** Returns the number of consecutive store conditional failures. */
228    // @todo: Figure out where these store cond failures should go.
229    virtual unsigned readStCondFailures()
230    { return thread->storeCondFailures; }
231
232    /** Sets the number of consecutive store conditional failures. */
233    virtual void setStCondFailures(unsigned sc_failures)
234    { thread->storeCondFailures = sc_failures; }
235
236    // Only really makes sense for old CPU model.  Lots of code
237    // outside the CPU still checks this function, so it will
238    // always return false to keep everything working.
239    /** Checks if the thread is misspeculating.  Because it is
240     * very difficult to determine if the thread is
241     * misspeculating, this is set as false. */
242    virtual bool misspeculating() { return false; }
243
244#if !FULL_SYSTEM
245    /** Gets a syscall argument by index. */
246    virtual IntReg getSyscallArg(int i);
247
248    /** Sets a syscall argument. */
249    virtual void setSyscallArg(int i, IntReg val);
250
251    /** Sets the syscall return value. */
252    virtual void setSyscallReturn(SyscallReturn return_value);
253
254    /** Executes a syscall in SE mode. */
255    virtual void syscall(int64_t callnum)
256    { return cpu->syscall(callnum, thread->readTid()); }
257
258    /** Reads the funcExeInst counter. */
259    virtual Counter readFuncExeInst() { return thread->funcExeInst; }
260#else
261    /** Returns pointer to the quiesce event. */
262    virtual EndQuiesceEvent *getQuiesceEvent()
263    {
264        return this->thread->quiesceEvent;
265    }
266#endif
267
268    virtual uint64_t readNextNPC()
269    {
270        return this->cpu->readNextNPC(this->thread->readTid());
271    }
272
273    virtual void setNextNPC(uint64_t val)
274    {
275#if THE_ISA == ALPHA_ISA
276        panic("Not supported on Alpha!");
277#endif
278        this->cpu->setNextNPC(val, this->thread->readTid());
279    }
280
281    /** This function exits the thread context in the CPU and returns
282     * 1 if the CPU has no more active threads (meaning it's OK to exit);
283     * Used in syscall-emulation mode when a thread executes the 'exit'
284     * syscall.
285     */
286    virtual int exit()
287    {
288        this->deallocate();
289
290        // If there are still threads executing in the system
291        if (this->cpu->numActiveThreads())
292            return 0; // don't exit simulation
293        else
294            return 1; // exit simulation
295    }
296};
297
298#endif
299