thread_context.hh revision 13582 
1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_THREAD_CONTEXT_HH__
45#define __CPU_O3_THREAD_CONTEXT_HH__
46
47#include "config/the_isa.hh"
48#include "cpu/o3/isa_specific.hh"
49#include "cpu/thread_context.hh"
50
51class EndQuiesceEvent;
52namespace Kernel {
53    class Statistics;
54}
55
56/**
57 * Derived ThreadContext class for use with the O3CPU.  It
58 * provides the interface for any external objects to access a
59 * single thread's state and some general CPU state.  Any time
60 * external objects try to update state through this interface,
61 * the CPU will create an event to squash all in-flight
62 * instructions in order to ensure state is maintained correctly.
63 * It must be defined specifically for the O3CPU because
64 * not all architectural state is located within the O3ThreadState
65 * (such as the commit PC, and registers), and specific actions
66 * must be taken when using this interface (such as squashing all
67 * in-flight instructions when doing a write to this interface).
68 */
69template <class Impl>
70class O3ThreadContext : public ThreadContext
71{
72  public:
73    typedef typename Impl::O3CPU O3CPU;
74
75   /** Pointer to the CPU. */
76    O3CPU *cpu;
77
78    /** Pointer to the thread state that this TC corrseponds to. */
79    O3ThreadState<Impl> *thread;
80
81    /** Returns a pointer to the ITB. */
82    BaseTLB *getITBPtr() { return cpu->itb; }
83
84    /** Returns a pointer to the DTB. */
85    BaseTLB *getDTBPtr() { return cpu->dtb; }
86
87    CheckerCPU *getCheckerCpuPtr() { return NULL; }
88
89    TheISA::Decoder *
90    getDecoderPtr()
91    {
92        return cpu->fetch.decoder[thread->threadId()];
93    }
94
95    /** Returns a pointer to this CPU. */
96    virtual BaseCPU *getCpuPtr() { return cpu; }
97
98    /** Reads this CPU's ID. */
99    virtual int cpuId() const { return cpu->cpuId(); }
100
101    /** Reads this CPU's Socket ID. */
102    virtual uint32_t socketId() const { return cpu->socketId(); }
103
104    virtual ContextID contextId() const { return thread->contextId(); }
105
106    virtual void setContextId(int id) { thread->setContextId(id); }
107
108    /** Returns this thread's ID number. */
109    virtual int threadId() const { return thread->threadId(); }
110    virtual void setThreadId(int id) { return thread->setThreadId(id); }
111
112    /** Returns a pointer to the system. */
113    virtual System *getSystemPtr() { return cpu->system; }
114
115    /** Returns a pointer to this thread's kernel statistics. */
116    virtual TheISA::Kernel::Statistics *getKernelStats()
117    { return thread->kernelStats; }
118
119    /** Returns a pointer to this thread's process. */
120    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
121
122    virtual void setProcessPtr(Process *p) { thread->setProcessPtr(p); }
123
124    virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
125
126    virtual FSTranslatingPortProxy &getVirtProxy();
127
128    virtual void initMemProxies(ThreadContext *tc)
129    { thread->initMemProxies(tc); }
130
131    virtual SETranslatingPortProxy &getMemProxy()
132    { return thread->getMemProxy(); }
133
134    /** Returns this thread's status. */
135    virtual Status status() const { return thread->status(); }
136
137    /** Sets this thread's status. */
138    virtual void setStatus(Status new_status)
139    { thread->setStatus(new_status); }
140
141    /** Set the status to Active. */
142    virtual void activate();
143
144    /** Set the status to Suspended. */
145    virtual void suspend();
146
147    /** Set the status to Halted. */
148    virtual void halt();
149
150    /** Dumps the function profiling information.
151     * @todo: Implement.
152     */
153    virtual void dumpFuncProfile();
154
155    /** Takes over execution of a thread from another CPU. */
156    virtual void takeOverFrom(ThreadContext *old_context);
157
158    /** Registers statistics associated with this TC. */
159    virtual void regStats(const std::string &name);
160
161    /** Reads the last tick that this thread was activated on. */
162    virtual Tick readLastActivate();
163    /** Reads the last tick that this thread was suspended on. */
164    virtual Tick readLastSuspend();
165
166    /** Clears the function profiling information. */
167    virtual void profileClear();
168    /** Samples the function profiling information. */
169    virtual void profileSample();
170
171    /** Copies the architectural registers from another TC into this TC. */
172    virtual void copyArchRegs(ThreadContext *tc);
173
174    /** Resets all architectural registers to 0. */
175    virtual void clearArchRegs();
176
177    /** Reads an integer register. */
178    virtual RegVal
179    readReg(int reg_idx)
180    {
181        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
182                                                 reg_idx)).index());
183    }
184    virtual RegVal
185    readIntReg(int reg_idx)
186    {
187        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
188                                                 reg_idx)).index());
189    }
190
191    virtual RegVal
192    readFloatRegBits(int reg_idx)
193    {
194        return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
195                                                 reg_idx)).index());
196    }
197
198    virtual const VecRegContainer &
199    readVecReg(const RegId& id) const
200    {
201        return readVecRegFlat(flattenRegId(id).index());
202    }
203
204    /**
205     * Read vector register operand for modification, hierarchical indexing.
206     */
207    virtual VecRegContainer &
208    getWritableVecReg(const RegId& id)
209    {
210        return getWritableVecRegFlat(flattenRegId(id).index());
211    }
212
213    /** Vector Register Lane Interfaces. */
214    /** @{ */
215    /** Reads source vector 8bit operand. */
216    virtual ConstVecLane8
217    readVec8BitLaneReg(const RegId& id) const
218    {
219        return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
220                    id.elemIndex());
221    }
222
223    /** Reads source vector 16bit operand. */
224    virtual ConstVecLane16
225    readVec16BitLaneReg(const RegId& id) const
226    {
227        return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
228                    id.elemIndex());
229    }
230
231    /** Reads source vector 32bit operand. */
232    virtual ConstVecLane32
233    readVec32BitLaneReg(const RegId& id) const
234    {
235        return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
236                    id.elemIndex());
237    }
238
239    /** Reads source vector 64bit operand. */
240    virtual ConstVecLane64
241    readVec64BitLaneReg(const RegId& id) const
242    {
243        return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
244                    id.elemIndex());
245    }
246
247    /** Write a lane of the destination vector register. */
248    virtual void setVecLane(const RegId& reg,
249            const LaneData<LaneSize::Byte>& val)
250    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
251    virtual void setVecLane(const RegId& reg,
252            const LaneData<LaneSize::TwoByte>& val)
253    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
254    virtual void setVecLane(const RegId& reg,
255            const LaneData<LaneSize::FourByte>& val)
256    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
257    virtual void setVecLane(const RegId& reg,
258            const LaneData<LaneSize::EightByte>& val)
259    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
260    /** @} */
261
262    virtual const VecElem& readVecElem(const RegId& reg) const {
263        return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
264    }
265
266    virtual CCReg readCCReg(int reg_idx) {
267        return readCCRegFlat(flattenRegId(RegId(CCRegClass,
268                                                 reg_idx)).index());
269    }
270
271    /** Sets an integer register to a value. */
272    virtual void
273    setIntReg(int reg_idx, RegVal val)
274    {
275        setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
276    }
277
278    virtual void
279    setFloatRegBits(int reg_idx, RegVal val)
280    {
281        setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
282                                               reg_idx)).index(), val);
283    }
284
285    virtual void
286    setVecReg(const RegId& reg, const VecRegContainer& val)
287    {
288        setVecRegFlat(flattenRegId(reg).index(), val);
289    }
290
291    virtual void
292    setVecElem(const RegId& reg, const VecElem& val)
293    {
294        setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
295    }
296
297    virtual void
298    setCCReg(int reg_idx, CCReg val)
299    {
300        setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
301    }
302
303    /** Reads this thread's PC state. */
304    virtual TheISA::PCState pcState()
305    { return cpu->pcState(thread->threadId()); }
306
307    /** Sets this thread's PC state. */
308    virtual void pcState(const TheISA::PCState &val);
309
310    virtual void pcStateNoRecord(const TheISA::PCState &val);
311
312    /** Reads this thread's PC. */
313    virtual Addr instAddr()
314    { return cpu->instAddr(thread->threadId()); }
315
316    /** Reads this thread's next PC. */
317    virtual Addr nextInstAddr()
318    { return cpu->nextInstAddr(thread->threadId()); }
319
320    /** Reads this thread's next PC. */
321    virtual MicroPC microPC()
322    { return cpu->microPC(thread->threadId()); }
323
324    /** Reads a miscellaneous register. */
325    virtual RegVal readMiscRegNoEffect(int misc_reg) const
326    { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
327
328    /** Reads a misc. register, including any side-effects the
329     * read might have as defined by the architecture. */
330    virtual RegVal readMiscReg(int misc_reg)
331    { return cpu->readMiscReg(misc_reg, thread->threadId()); }
332
333    /** Sets a misc. register. */
334    virtual void setMiscRegNoEffect(int misc_reg, RegVal val);
335
336    /** Sets a misc. register, including any side-effects the
337     * write might have as defined by the architecture. */
338    virtual void setMiscReg(int misc_reg, RegVal val);
339
340    virtual RegId flattenRegId(const RegId& regId) const;
341
342    /** Returns the number of consecutive store conditional failures. */
343    // @todo: Figure out where these store cond failures should go.
344    virtual unsigned readStCondFailures()
345    { return thread->storeCondFailures; }
346
347    /** Sets the number of consecutive store conditional failures. */
348    virtual void setStCondFailures(unsigned sc_failures)
349    { thread->storeCondFailures = sc_failures; }
350
351    /** Executes a syscall in SE mode. */
352    virtual void syscall(int64_t callnum, Fault *fault)
353    { return cpu->syscall(callnum, thread->threadId(), fault); }
354
355    /** Reads the funcExeInst counter. */
356    virtual Counter readFuncExeInst() { return thread->funcExeInst; }
357
358    /** Returns pointer to the quiesce event. */
359    virtual EndQuiesceEvent *
360    getQuiesceEvent()
361    {
362        return this->thread->quiesceEvent;
363    }
364    /** check if the cpu is currently in state update mode and squash if not.
365     * This function will return true if a trap is pending or if a fault or
366     * similar is currently writing to the thread context and doesn't want
367     * reset all the state (see noSquashFromTC).
368     */
369    inline void
370    conditionalSquash()
371    {
372        if (!thread->trapPending && !thread->noSquashFromTC)
373            cpu->squashFromTC(thread->threadId());
374    }
375
376    virtual RegVal readIntRegFlat(int idx);
377    virtual void setIntRegFlat(int idx, RegVal val);
378
379    virtual RegVal readFloatRegBitsFlat(int idx);
380    virtual void setFloatRegBitsFlat(int idx, RegVal val);
381
382    virtual const VecRegContainer& readVecRegFlat(int idx) const;
383    /** Read vector register operand for modification, flat indexing. */
384    virtual VecRegContainer& getWritableVecRegFlat(int idx);
385    virtual void setVecRegFlat(int idx, const VecRegContainer& val);
386
387    template <typename VecElem>
388    VecLaneT<VecElem, true>
389    readVecLaneFlat(int idx, int lId) const
390    {
391        return cpu->template readArchVecLane<VecElem>(idx, lId,
392                thread->threadId());
393    }
394
395    template <typename LD>
396    void setVecLaneFlat(int idx, int lId, const LD& val)
397    {
398        cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
399    }
400
401    virtual const VecElem& readVecElemFlat(const RegIndex& idx,
402                                           const ElemIndex& elemIndex) const;
403    virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
404                                const VecElem& val);
405
406    virtual CCReg readCCRegFlat(int idx);
407    virtual void setCCRegFlat(int idx, CCReg val);
408};
409
410#endif
411