thread_context.hh revision 12106:7784fac1b159
15794SN/A/* 25794SN/A * Copyright (c) 2011-2012 ARM Limited 35794SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 45794SN/A * All rights reserved 55794SN/A * 65794SN/A * The license below extends only to copyright in the software and shall 75794SN/A * not be construed as granting a license to any other intellectual 85794SN/A * property including but not limited to intellectual property relating 95794SN/A * to a hardware implementation of the functionality of the software 105794SN/A * licensed hereunder. You may use the software subject to the license 115794SN/A * terms below provided that you ensure that this notice is replicated 125794SN/A * unmodified and in its entirety in all distributions of the software, 135794SN/A * modified or unmodified, in source code or in binary form. 145794SN/A * 155794SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 165794SN/A * All rights reserved. 175794SN/A * 185794SN/A * Redistribution and use in source and binary forms, with or without 195794SN/A * modification, are permitted provided that the following conditions are 205794SN/A * met: redistributions of source code must retain the above copyright 215794SN/A * notice, this list of conditions and the following disclaimer; 225794SN/A * redistributions in binary form must reproduce the above copyright 235794SN/A * notice, this list of conditions and the following disclaimer in the 245794SN/A * documentation and/or other materials provided with the distribution; 255794SN/A * neither the name of the copyright holders nor the names of its 265794SN/A * contributors may be used to endorse or promote products derived from 275794SN/A * this software without specific prior written permission. 285794SN/A * 295794SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305794SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315794SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3213665Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3313665Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345794SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355794SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365794SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711261Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 388841SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395794SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405794SN/A * 415794SN/A * Authors: Kevin Lim 425794SN/A */ 435794SN/A 445794SN/A#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 455794SN/A#define __CPU_O3_THREAD_CONTEXT_HH__ 465794SN/A 475794SN/A#include "config/the_isa.hh" 485794SN/A#include "cpu/o3/isa_specific.hh" 495794SN/A#include "cpu/thread_context.hh" 505794SN/A 515794SN/Aclass EndQuiesceEvent; 525794SN/Anamespace Kernel { 535794SN/A class Statistics; 545794SN/A} 555794SN/A 565794SN/A/** 575794SN/A * Derived ThreadContext class for use with the O3CPU. It 585794SN/A * provides the interface for any external objects to access a 595794SN/A * single thread's state and some general CPU state. Any time 605794SN/A * external objects try to update state through this interface, 61 * the CPU will create an event to squash all in-flight 62 * instructions in order to ensure state is maintained correctly. 63 * It must be defined specifically for the O3CPU because 64 * not all architectural state is located within the O3ThreadState 65 * (such as the commit PC, and registers), and specific actions 66 * must be taken when using this interface (such as squashing all 67 * in-flight instructions when doing a write to this interface). 68 */ 69template <class Impl> 70class O3ThreadContext : public ThreadContext 71{ 72 public: 73 typedef typename Impl::O3CPU O3CPU; 74 75 /** Pointer to the CPU. */ 76 O3CPU *cpu; 77 78 /** Pointer to the thread state that this TC corrseponds to. */ 79 O3ThreadState<Impl> *thread; 80 81 /** Returns a pointer to the ITB. */ 82 TheISA::TLB *getITBPtr() { return cpu->itb; } 83 84 /** Returns a pointer to the DTB. */ 85 TheISA::TLB *getDTBPtr() { return cpu->dtb; } 86 87 CheckerCPU *getCheckerCpuPtr() { return NULL; } 88 89 TheISA::Decoder * 90 getDecoderPtr() 91 { 92 return cpu->fetch.decoder[thread->threadId()]; 93 } 94 95 /** Returns a pointer to this CPU. */ 96 virtual BaseCPU *getCpuPtr() { return cpu; } 97 98 /** Reads this CPU's ID. */ 99 virtual int cpuId() const { return cpu->cpuId(); } 100 101 /** Reads this CPU's Socket ID. */ 102 virtual uint32_t socketId() const { return cpu->socketId(); } 103 104 virtual ContextID contextId() const { return thread->contextId(); } 105 106 virtual void setContextId(int id) { thread->setContextId(id); } 107 108 /** Returns this thread's ID number. */ 109 virtual int threadId() const { return thread->threadId(); } 110 virtual void setThreadId(int id) { return thread->setThreadId(id); } 111 112 /** Returns a pointer to the system. */ 113 virtual System *getSystemPtr() { return cpu->system; } 114 115 /** Returns a pointer to this thread's kernel statistics. */ 116 virtual TheISA::Kernel::Statistics *getKernelStats() 117 { return thread->kernelStats; } 118 119 /** Returns a pointer to this thread's process. */ 120 virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 121 122 virtual void setProcessPtr(Process *p) { thread->setProcessPtr(p); } 123 124 virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); } 125 126 virtual FSTranslatingPortProxy &getVirtProxy(); 127 128 virtual void initMemProxies(ThreadContext *tc) 129 { thread->initMemProxies(tc); } 130 131 virtual SETranslatingPortProxy &getMemProxy() 132 { return thread->getMemProxy(); } 133 134 /** Returns this thread's status. */ 135 virtual Status status() const { return thread->status(); } 136 137 /** Sets this thread's status. */ 138 virtual void setStatus(Status new_status) 139 { thread->setStatus(new_status); } 140 141 /** Set the status to Active. */ 142 virtual void activate(); 143 144 /** Set the status to Suspended. */ 145 virtual void suspend(); 146 147 /** Set the status to Halted. */ 148 virtual void halt(); 149 150 /** Dumps the function profiling information. 151 * @todo: Implement. 152 */ 153 virtual void dumpFuncProfile(); 154 155 /** Takes over execution of a thread from another CPU. */ 156 virtual void takeOverFrom(ThreadContext *old_context); 157 158 /** Registers statistics associated with this TC. */ 159 virtual void regStats(const std::string &name); 160 161 /** Reads the last tick that this thread was activated on. */ 162 virtual Tick readLastActivate(); 163 /** Reads the last tick that this thread was suspended on. */ 164 virtual Tick readLastSuspend(); 165 166 /** Clears the function profiling information. */ 167 virtual void profileClear(); 168 /** Samples the function profiling information. */ 169 virtual void profileSample(); 170 171 /** Copies the architectural registers from another TC into this TC. */ 172 virtual void copyArchRegs(ThreadContext *tc); 173 174 /** Resets all architectural registers to 0. */ 175 virtual void clearArchRegs(); 176 177 /** Reads an integer register. */ 178 virtual uint64_t readReg(int reg_idx) { 179 return readIntRegFlat(flattenRegId(RegId(IntRegClass, 180 reg_idx)).index()); 181 } 182 virtual uint64_t readIntReg(int reg_idx) { 183 return readIntRegFlat(flattenRegId(RegId(IntRegClass, 184 reg_idx)).index()); 185 } 186 187 virtual FloatReg readFloatReg(int reg_idx) { 188 return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, 189 reg_idx)).index()); 190 } 191 192 virtual FloatRegBits readFloatRegBits(int reg_idx) { 193 return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, 194 reg_idx)).index()); 195 } 196 197 virtual CCReg readCCReg(int reg_idx) { 198 return readCCRegFlat(flattenRegId(RegId(CCRegClass, 199 reg_idx)).index()); 200 } 201 202 /** Sets an integer register to a value. */ 203 virtual void setIntReg(int reg_idx, uint64_t val) { 204 setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); 205 } 206 207 virtual void setFloatReg(int reg_idx, FloatReg val) { 208 setFloatRegFlat(flattenRegId(RegId(FloatRegClass, 209 reg_idx)).index(), val); 210 } 211 212 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) { 213 setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, 214 reg_idx)).index(), val); 215 } 216 217 virtual void setCCReg(int reg_idx, CCReg val) { 218 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); 219 } 220 221 /** Reads this thread's PC state. */ 222 virtual TheISA::PCState pcState() 223 { return cpu->pcState(thread->threadId()); } 224 225 /** Sets this thread's PC state. */ 226 virtual void pcState(const TheISA::PCState &val); 227 228 virtual void pcStateNoRecord(const TheISA::PCState &val); 229 230 /** Reads this thread's PC. */ 231 virtual Addr instAddr() 232 { return cpu->instAddr(thread->threadId()); } 233 234 /** Reads this thread's next PC. */ 235 virtual Addr nextInstAddr() 236 { return cpu->nextInstAddr(thread->threadId()); } 237 238 /** Reads this thread's next PC. */ 239 virtual MicroPC microPC() 240 { return cpu->microPC(thread->threadId()); } 241 242 /** Reads a miscellaneous register. */ 243 virtual MiscReg readMiscRegNoEffect(int misc_reg) const 244 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 245 246 /** Reads a misc. register, including any side-effects the 247 * read might have as defined by the architecture. */ 248 virtual MiscReg readMiscReg(int misc_reg) 249 { return cpu->readMiscReg(misc_reg, thread->threadId()); } 250 251 /** Sets a misc. register. */ 252 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 253 254 /** Sets a misc. register, including any side-effects the 255 * write might have as defined by the architecture. */ 256 virtual void setMiscReg(int misc_reg, const MiscReg &val); 257 258 virtual RegId flattenRegId(const RegId& regId) const; 259 260 /** Returns the number of consecutive store conditional failures. */ 261 // @todo: Figure out where these store cond failures should go. 262 virtual unsigned readStCondFailures() 263 { return thread->storeCondFailures; } 264 265 /** Sets the number of consecutive store conditional failures. */ 266 virtual void setStCondFailures(unsigned sc_failures) 267 { thread->storeCondFailures = sc_failures; } 268 269 /** Executes a syscall in SE mode. */ 270 virtual void syscall(int64_t callnum, Fault *fault) 271 { return cpu->syscall(callnum, thread->threadId(), fault); } 272 273 /** Reads the funcExeInst counter. */ 274 virtual Counter readFuncExeInst() { return thread->funcExeInst; } 275 276 /** Returns pointer to the quiesce event. */ 277 virtual EndQuiesceEvent *getQuiesceEvent() 278 { 279 return this->thread->quiesceEvent; 280 } 281 /** check if the cpu is currently in state update mode and squash if not. 282 * This function will return true if a trap is pending or if a fault or 283 * similar is currently writing to the thread context and doesn't want 284 * reset all the state (see noSquashFromTC). 285 */ 286 inline void conditionalSquash() 287 { 288 if (!thread->trapPending && !thread->noSquashFromTC) 289 cpu->squashFromTC(thread->threadId()); 290 } 291 292 virtual uint64_t readIntRegFlat(int idx); 293 virtual void setIntRegFlat(int idx, uint64_t val); 294 295 virtual FloatReg readFloatRegFlat(int idx); 296 virtual void setFloatRegFlat(int idx, FloatReg val); 297 298 virtual FloatRegBits readFloatRegBitsFlat(int idx); 299 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val); 300 301 virtual CCReg readCCRegFlat(int idx); 302 virtual void setCCRegFlat(int idx, CCReg val); 303}; 304 305#endif 306