thread_context.hh revision 10033
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 45#define __CPU_O3_THREAD_CONTEXT_HH__ 46 47#include "config/the_isa.hh" 48#include "cpu/o3/isa_specific.hh" 49#include "cpu/thread_context.hh" 50 51class EndQuiesceEvent; 52namespace Kernel { 53 class Statistics; 54} 55 56/** 57 * Derived ThreadContext class for use with the O3CPU. It 58 * provides the interface for any external objects to access a 59 * single thread's state and some general CPU state. Any time 60 * external objects try to update state through this interface, 61 * the CPU will create an event to squash all in-flight 62 * instructions in order to ensure state is maintained correctly. 63 * It must be defined specifically for the O3CPU because 64 * not all architectural state is located within the O3ThreadState 65 * (such as the commit PC, and registers), and specific actions 66 * must be taken when using this interface (such as squashing all 67 * in-flight instructions when doing a write to this interface). 68 */ 69template <class Impl> 70class O3ThreadContext : public ThreadContext 71{ 72 public: 73 typedef typename Impl::O3CPU O3CPU; 74 75 /** Pointer to the CPU. */ 76 O3CPU *cpu; 77 78 /** Pointer to the thread state that this TC corrseponds to. */ 79 O3ThreadState<Impl> *thread; 80 81 /** Returns a pointer to the ITB. */ 82 TheISA::TLB *getITBPtr() { return cpu->itb; } 83 84 /** Returns a pointer to the DTB. */ 85 TheISA::TLB *getDTBPtr() { return cpu->dtb; } 86 87 CheckerCPU *getCheckerCpuPtr() { return NULL; } 88 89 TheISA::Decoder * 90 getDecoderPtr() 91 { 92 return cpu->fetch.decoder[thread->threadId()]; 93 } 94 95 /** Returns a pointer to this CPU. */ 96 virtual BaseCPU *getCpuPtr() { return cpu; } 97 98 /** Reads this CPU's ID. */ 99 virtual int cpuId() { return cpu->cpuId(); } 100 101 virtual int contextId() { return thread->contextId(); } 102 103 virtual void setContextId(int id) { thread->setContextId(id); } 104 105 /** Returns this thread's ID number. */ 106 virtual int threadId() { return thread->threadId(); } 107 virtual void setThreadId(int id) { return thread->setThreadId(id); } 108 109 /** Returns a pointer to the system. */ 110 virtual System *getSystemPtr() { return cpu->system; } 111 112 /** Returns a pointer to this thread's kernel statistics. */ 113 virtual TheISA::Kernel::Statistics *getKernelStats() 114 { return thread->kernelStats; } 115 116 /** Returns a pointer to this thread's process. */ 117 virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 118 119 virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); } 120 121 virtual FSTranslatingPortProxy &getVirtProxy(); 122 123 virtual void initMemProxies(ThreadContext *tc) 124 { thread->initMemProxies(tc); } 125 126 virtual SETranslatingPortProxy &getMemProxy() 127 { return thread->getMemProxy(); } 128 129 /** Returns this thread's status. */ 130 virtual Status status() const { return thread->status(); } 131 132 /** Sets this thread's status. */ 133 virtual void setStatus(Status new_status) 134 { thread->setStatus(new_status); } 135 136 /** Set the status to Active. Optional delay indicates number of 137 * cycles to wait before beginning execution. */ 138 virtual void activate(Cycles delay = Cycles(1)); 139 140 /** Set the status to Suspended. */ 141 virtual void suspend(Cycles delay = Cycles(0)); 142 143 /** Set the status to Halted. */ 144 virtual void halt(Cycles delay = Cycles(0)); 145 146 /** Dumps the function profiling information. 147 * @todo: Implement. 148 */ 149 virtual void dumpFuncProfile(); 150 151 /** Takes over execution of a thread from another CPU. */ 152 virtual void takeOverFrom(ThreadContext *old_context); 153 154 /** Registers statistics associated with this TC. */ 155 virtual void regStats(const std::string &name); 156 157 /** Reads the last tick that this thread was activated on. */ 158 virtual Tick readLastActivate(); 159 /** Reads the last tick that this thread was suspended on. */ 160 virtual Tick readLastSuspend(); 161 162 /** Clears the function profiling information. */ 163 virtual void profileClear(); 164 /** Samples the function profiling information. */ 165 virtual void profileSample(); 166 167 /** Copies the architectural registers from another TC into this TC. */ 168 virtual void copyArchRegs(ThreadContext *tc); 169 170 /** Resets all architectural registers to 0. */ 171 virtual void clearArchRegs(); 172 173 /** Reads an integer register. */ 174 virtual uint64_t readIntReg(int reg_idx) { 175 return readIntRegFlat(flattenIntIndex(reg_idx)); 176 } 177 178 virtual FloatReg readFloatReg(int reg_idx) { 179 return readFloatRegFlat(flattenFloatIndex(reg_idx)); 180 } 181 182 virtual FloatRegBits readFloatRegBits(int reg_idx) { 183 return readFloatRegBitsFlat(flattenFloatIndex(reg_idx)); 184 } 185 186 virtual CCReg readCCReg(int reg_idx) { 187 return readCCRegFlat(flattenCCIndex(reg_idx)); 188 } 189 190 /** Sets an integer register to a value. */ 191 virtual void setIntReg(int reg_idx, uint64_t val) { 192 setIntRegFlat(flattenIntIndex(reg_idx), val); 193 } 194 195 virtual void setFloatReg(int reg_idx, FloatReg val) { 196 setFloatRegFlat(flattenFloatIndex(reg_idx), val); 197 } 198 199 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) { 200 setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val); 201 } 202 203 virtual void setCCReg(int reg_idx, CCReg val) { 204 setCCRegFlat(flattenCCIndex(reg_idx), val); 205 } 206 207 /** Reads this thread's PC state. */ 208 virtual TheISA::PCState pcState() 209 { return cpu->pcState(thread->threadId()); } 210 211 /** Sets this thread's PC state. */ 212 virtual void pcState(const TheISA::PCState &val); 213 214 virtual void pcStateNoRecord(const TheISA::PCState &val); 215 216 /** Reads this thread's PC. */ 217 virtual Addr instAddr() 218 { return cpu->instAddr(thread->threadId()); } 219 220 /** Reads this thread's next PC. */ 221 virtual Addr nextInstAddr() 222 { return cpu->nextInstAddr(thread->threadId()); } 223 224 /** Reads this thread's next PC. */ 225 virtual MicroPC microPC() 226 { return cpu->microPC(thread->threadId()); } 227 228 /** Reads a miscellaneous register. */ 229 virtual MiscReg readMiscRegNoEffect(int misc_reg) 230 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 231 232 /** Reads a misc. register, including any side-effects the 233 * read might have as defined by the architecture. */ 234 virtual MiscReg readMiscReg(int misc_reg) 235 { return cpu->readMiscReg(misc_reg, thread->threadId()); } 236 237 /** Sets a misc. register. */ 238 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 239 240 /** Sets a misc. register, including any side-effects the 241 * write might have as defined by the architecture. */ 242 virtual void setMiscReg(int misc_reg, const MiscReg &val); 243 244 virtual int flattenIntIndex(int reg); 245 virtual int flattenFloatIndex(int reg); 246 virtual int flattenCCIndex(int reg); 247 virtual int flattenMiscIndex(int reg); 248 249 /** Returns the number of consecutive store conditional failures. */ 250 // @todo: Figure out where these store cond failures should go. 251 virtual unsigned readStCondFailures() 252 { return thread->storeCondFailures; } 253 254 /** Sets the number of consecutive store conditional failures. */ 255 virtual void setStCondFailures(unsigned sc_failures) 256 { thread->storeCondFailures = sc_failures; } 257 258 // Only really makes sense for old CPU model. Lots of code 259 // outside the CPU still checks this function, so it will 260 // always return false to keep everything working. 261 /** Checks if the thread is misspeculating. Because it is 262 * very difficult to determine if the thread is 263 * misspeculating, this is set as false. */ 264 virtual bool misspeculating() { return false; } 265 266 /** Executes a syscall in SE mode. */ 267 virtual void syscall(int64_t callnum) 268 { return cpu->syscall(callnum, thread->threadId()); } 269 270 /** Reads the funcExeInst counter. */ 271 virtual Counter readFuncExeInst() { return thread->funcExeInst; } 272 273 /** Returns pointer to the quiesce event. */ 274 virtual EndQuiesceEvent *getQuiesceEvent() 275 { 276 return this->thread->quiesceEvent; 277 } 278 /** check if the cpu is currently in state update mode and squash if not. 279 * This function will return true if a trap is pending or if a fault or 280 * similar is currently writing to the thread context and doesn't want 281 * reset all the state (see noSquashFromTC). 282 */ 283 inline void conditionalSquash() 284 { 285 if (!thread->trapPending && !thread->noSquashFromTC) 286 cpu->squashFromTC(thread->threadId()); 287 } 288 289 virtual uint64_t readIntRegFlat(int idx); 290 virtual void setIntRegFlat(int idx, uint64_t val); 291 292 virtual FloatReg readFloatRegFlat(int idx); 293 virtual void setFloatRegFlat(int idx, FloatReg val); 294 295 virtual FloatRegBits readFloatRegBitsFlat(int idx); 296 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val); 297 298 virtual CCReg readCCRegFlat(int idx); 299 virtual void setCCRegFlat(int idx, CCReg val); 300}; 301 302#endif 303