thread_context.hh revision 9426
12817Sksewell@umich.edu/* 29426SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 152817Sksewell@umich.edu * All rights reserved. 162817Sksewell@umich.edu * 172817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 182817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 192817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 202817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 212817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 222817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 232817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 242817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 252817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 262817Sksewell@umich.edu * this software without specific prior written permission. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392817Sksewell@umich.edu * 402817Sksewell@umich.edu * Authors: Kevin Lim 412817Sksewell@umich.edu */ 422817Sksewell@umich.edu 432817Sksewell@umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 442817Sksewell@umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 452817Sksewell@umich.edu 466658Snate@binkert.org#include "config/the_isa.hh" 478229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 482935Sksewell@umich.edu#include "cpu/thread_context.hh" 492817Sksewell@umich.edu 502834Sksewell@umich.educlass EndQuiesceEvent; 512834Sksewell@umich.edunamespace Kernel { 522834Sksewell@umich.edu class Statistics; 538902Sandreas.hansson@arm.com} 542834Sksewell@umich.edu 552817Sksewell@umich.edu/** 562817Sksewell@umich.edu * Derived ThreadContext class for use with the O3CPU. It 572817Sksewell@umich.edu * provides the interface for any external objects to access a 582817Sksewell@umich.edu * single thread's state and some general CPU state. Any time 592817Sksewell@umich.edu * external objects try to update state through this interface, 602817Sksewell@umich.edu * the CPU will create an event to squash all in-flight 612817Sksewell@umich.edu * instructions in order to ensure state is maintained correctly. 622817Sksewell@umich.edu * It must be defined specifically for the O3CPU because 632817Sksewell@umich.edu * not all architectural state is located within the O3ThreadState 642817Sksewell@umich.edu * (such as the commit PC, and registers), and specific actions 652817Sksewell@umich.edu * must be taken when using this interface (such as squashing all 662817Sksewell@umich.edu * in-flight instructions when doing a write to this interface). 672817Sksewell@umich.edu */ 682817Sksewell@umich.edutemplate <class Impl> 692817Sksewell@umich.educlass O3ThreadContext : public ThreadContext 702817Sksewell@umich.edu{ 712817Sksewell@umich.edu public: 722817Sksewell@umich.edu typedef typename Impl::O3CPU O3CPU; 732817Sksewell@umich.edu 742817Sksewell@umich.edu /** Pointer to the CPU. */ 752817Sksewell@umich.edu O3CPU *cpu; 762817Sksewell@umich.edu 772817Sksewell@umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 782817Sksewell@umich.edu O3ThreadState<Impl> *thread; 792817Sksewell@umich.edu 803784Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 816022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return cpu->itb; } 823784Sgblack@eecs.umich.edu 833784Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 846022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return cpu->dtb; } 853784Sgblack@eecs.umich.edu 868887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 878733Sgeoffrey.blake@arm.com 889023Sgblack@eecs.umich.edu TheISA::Decoder * 899023Sgblack@eecs.umich.edu getDecoderPtr() 909023Sgblack@eecs.umich.edu { 919023Sgblack@eecs.umich.edu return cpu->fetch.decoder[thread->threadId()]; 929023Sgblack@eecs.umich.edu } 938541Sgblack@eecs.umich.edu 942817Sksewell@umich.edu /** Returns a pointer to this CPU. */ 952817Sksewell@umich.edu virtual BaseCPU *getCpuPtr() { return cpu; } 962817Sksewell@umich.edu 972817Sksewell@umich.edu /** Reads this CPU's ID. */ 985712Shsul@eecs.umich.edu virtual int cpuId() { return cpu->cpuId(); } 992817Sksewell@umich.edu 1005714Shsul@eecs.umich.edu virtual int contextId() { return thread->contextId(); } 1015714Shsul@eecs.umich.edu 1025714Shsul@eecs.umich.edu virtual void setContextId(int id) { thread->setContextId(id); } 1035714Shsul@eecs.umich.edu 1045715Shsul@eecs.umich.edu /** Returns this thread's ID number. */ 1055715Shsul@eecs.umich.edu virtual int threadId() { return thread->threadId(); } 1065715Shsul@eecs.umich.edu virtual void setThreadId(int id) { return thread->setThreadId(id); } 1075715Shsul@eecs.umich.edu 1082817Sksewell@umich.edu /** Returns a pointer to the system. */ 1092817Sksewell@umich.edu virtual System *getSystemPtr() { return cpu->system; } 1102817Sksewell@umich.edu 1112817Sksewell@umich.edu /** Returns a pointer to this thread's kernel statistics. */ 1123548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() 1132817Sksewell@umich.edu { return thread->kernelStats; } 1142817Sksewell@umich.edu 1158541Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 1168541Sgblack@eecs.umich.edu virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 1178754Sgblack@eecs.umich.edu 1188852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); } 1192817Sksewell@umich.edu 1208852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy(); 1213675Sktlim@umich.edu 1228706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) 1238706Sandreas.hansson@arm.com { thread->initMemProxies(tc); } 1248799Sgblack@eecs.umich.edu 1258852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() 1268706Sandreas.hansson@arm.com { return thread->getMemProxy(); } 1272817Sksewell@umich.edu 1282817Sksewell@umich.edu /** Returns this thread's status. */ 1292817Sksewell@umich.edu virtual Status status() const { return thread->status(); } 1302817Sksewell@umich.edu 1312817Sksewell@umich.edu /** Sets this thread's status. */ 1322817Sksewell@umich.edu virtual void setStatus(Status new_status) 1332817Sksewell@umich.edu { thread->setStatus(new_status); } 1342817Sksewell@umich.edu 1352817Sksewell@umich.edu /** Set the status to Active. Optional delay indicates number of 1362817Sksewell@umich.edu * cycles to wait before beginning execution. */ 1379180Sandreas.hansson@arm.com virtual void activate(Cycles delay = Cycles(1)); 1382817Sksewell@umich.edu 1392817Sksewell@umich.edu /** Set the status to Suspended. */ 1409180Sandreas.hansson@arm.com virtual void suspend(Cycles delay = Cycles(0)); 1412817Sksewell@umich.edu 1422817Sksewell@umich.edu /** Set the status to Halted. */ 1439180Sandreas.hansson@arm.com virtual void halt(Cycles delay = Cycles(0)); 1442817Sksewell@umich.edu 1452817Sksewell@umich.edu /** Dumps the function profiling information. 1462817Sksewell@umich.edu * @todo: Implement. 1472817Sksewell@umich.edu */ 1482817Sksewell@umich.edu virtual void dumpFuncProfile(); 1498777Sgblack@eecs.umich.edu 1502817Sksewell@umich.edu /** Takes over execution of a thread from another CPU. */ 1512817Sksewell@umich.edu virtual void takeOverFrom(ThreadContext *old_context); 1522817Sksewell@umich.edu 1532817Sksewell@umich.edu /** Registers statistics associated with this TC. */ 1542817Sksewell@umich.edu virtual void regStats(const std::string &name); 1552817Sksewell@umich.edu 1562817Sksewell@umich.edu /** Serializes state. */ 1572817Sksewell@umich.edu virtual void serialize(std::ostream &os); 1582817Sksewell@umich.edu /** Unserializes state. */ 1592817Sksewell@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1602817Sksewell@umich.edu 1612817Sksewell@umich.edu /** Reads the last tick that this thread was activated on. */ 1622817Sksewell@umich.edu virtual Tick readLastActivate(); 1632817Sksewell@umich.edu /** Reads the last tick that this thread was suspended on. */ 1642817Sksewell@umich.edu virtual Tick readLastSuspend(); 1652817Sksewell@umich.edu 1662817Sksewell@umich.edu /** Clears the function profiling information. */ 1672817Sksewell@umich.edu virtual void profileClear(); 1682817Sksewell@umich.edu /** Samples the function profiling information. */ 1692817Sksewell@umich.edu virtual void profileSample(); 1702817Sksewell@umich.edu 1712817Sksewell@umich.edu /** Copies the architectural registers from another TC into this TC. */ 1722817Sksewell@umich.edu virtual void copyArchRegs(ThreadContext *tc); 1732817Sksewell@umich.edu 1742817Sksewell@umich.edu /** Resets all architectural registers to 0. */ 1752817Sksewell@umich.edu virtual void clearArchRegs(); 1762817Sksewell@umich.edu 1772817Sksewell@umich.edu /** Reads an integer register. */ 1789426SAndreas.Sandberg@ARM.com virtual uint64_t readIntReg(int reg_idx) { 1799426SAndreas.Sandberg@ARM.com return readIntRegFlat(flattenIntIndex(reg_idx)); 1809426SAndreas.Sandberg@ARM.com } 1812817Sksewell@umich.edu 1829426SAndreas.Sandberg@ARM.com virtual FloatReg readFloatReg(int reg_idx) { 1839426SAndreas.Sandberg@ARM.com return readFloatRegFlat(flattenFloatIndex(reg_idx)); 1849426SAndreas.Sandberg@ARM.com } 1852817Sksewell@umich.edu 1869426SAndreas.Sandberg@ARM.com virtual FloatRegBits readFloatRegBits(int reg_idx) { 1879426SAndreas.Sandberg@ARM.com return readFloatRegBitsFlat(flattenFloatIndex(reg_idx)); 1889426SAndreas.Sandberg@ARM.com } 1892817Sksewell@umich.edu 1902817Sksewell@umich.edu /** Sets an integer register to a value. */ 1919426SAndreas.Sandberg@ARM.com virtual void setIntReg(int reg_idx, uint64_t val) { 1929426SAndreas.Sandberg@ARM.com setIntRegFlat(flattenIntIndex(reg_idx), val); 1939426SAndreas.Sandberg@ARM.com } 1942817Sksewell@umich.edu 1959426SAndreas.Sandberg@ARM.com virtual void setFloatReg(int reg_idx, FloatReg val) { 1969426SAndreas.Sandberg@ARM.com setFloatRegFlat(flattenFloatIndex(reg_idx), val); 1979426SAndreas.Sandberg@ARM.com } 1982817Sksewell@umich.edu 1999426SAndreas.Sandberg@ARM.com virtual void setFloatRegBits(int reg_idx, FloatRegBits val) { 2009426SAndreas.Sandberg@ARM.com setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val); 2019426SAndreas.Sandberg@ARM.com } 2022817Sksewell@umich.edu 2037720Sgblack@eecs.umich.edu /** Reads this thread's PC state. */ 2047720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() 2057720Sgblack@eecs.umich.edu { return cpu->pcState(thread->threadId()); } 2067720Sgblack@eecs.umich.edu 2077720Sgblack@eecs.umich.edu /** Sets this thread's PC state. */ 2087720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val); 2097720Sgblack@eecs.umich.edu 2108733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val); 2118733Sgeoffrey.blake@arm.com 2122817Sksewell@umich.edu /** Reads this thread's PC. */ 2137720Sgblack@eecs.umich.edu virtual Addr instAddr() 2147720Sgblack@eecs.umich.edu { return cpu->instAddr(thread->threadId()); } 2152817Sksewell@umich.edu 2162817Sksewell@umich.edu /** Reads this thread's next PC. */ 2177720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() 2187720Sgblack@eecs.umich.edu { return cpu->nextInstAddr(thread->threadId()); } 2192817Sksewell@umich.edu 2207720Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 2217720Sgblack@eecs.umich.edu virtual MicroPC microPC() 2227720Sgblack@eecs.umich.edu { return cpu->microPC(thread->threadId()); } 2235259Sksewell@umich.edu 2242817Sksewell@umich.edu /** Reads a miscellaneous register. */ 2254172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) 2265715Shsul@eecs.umich.edu { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 2274172Ssaidi@eecs.umich.edu 2284172Ssaidi@eecs.umich.edu /** Reads a misc. register, including any side-effects the 2294172Ssaidi@eecs.umich.edu * read might have as defined by the architecture. */ 2302817Sksewell@umich.edu virtual MiscReg readMiscReg(int misc_reg) 2315715Shsul@eecs.umich.edu { return cpu->readMiscReg(misc_reg, thread->threadId()); } 2322817Sksewell@umich.edu 2332817Sksewell@umich.edu /** Sets a misc. register. */ 2344172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 2352817Sksewell@umich.edu 2362817Sksewell@umich.edu /** Sets a misc. register, including any side-effects the 2372817Sksewell@umich.edu * write might have as defined by the architecture. */ 2384172Ssaidi@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val); 2392817Sksewell@umich.edu 2406313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg); 2416313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg); 2426313Sgblack@eecs.umich.edu 2432817Sksewell@umich.edu /** Returns the number of consecutive store conditional failures. */ 2442817Sksewell@umich.edu // @todo: Figure out where these store cond failures should go. 2452817Sksewell@umich.edu virtual unsigned readStCondFailures() 2462817Sksewell@umich.edu { return thread->storeCondFailures; } 2472817Sksewell@umich.edu 2482817Sksewell@umich.edu /** Sets the number of consecutive store conditional failures. */ 2492817Sksewell@umich.edu virtual void setStCondFailures(unsigned sc_failures) 2502817Sksewell@umich.edu { thread->storeCondFailures = sc_failures; } 2512817Sksewell@umich.edu 2522817Sksewell@umich.edu // Only really makes sense for old CPU model. Lots of code 2532817Sksewell@umich.edu // outside the CPU still checks this function, so it will 2542817Sksewell@umich.edu // always return false to keep everything working. 2552817Sksewell@umich.edu /** Checks if the thread is misspeculating. Because it is 2562817Sksewell@umich.edu * very difficult to determine if the thread is 2572817Sksewell@umich.edu * misspeculating, this is set as false. */ 2582817Sksewell@umich.edu virtual bool misspeculating() { return false; } 2592817Sksewell@umich.edu 2602817Sksewell@umich.edu /** Executes a syscall in SE mode. */ 2612817Sksewell@umich.edu virtual void syscall(int64_t callnum) 2625715Shsul@eecs.umich.edu { return cpu->syscall(callnum, thread->threadId()); } 2632817Sksewell@umich.edu 2642817Sksewell@umich.edu /** Reads the funcExeInst counter. */ 2652817Sksewell@umich.edu virtual Counter readFuncExeInst() { return thread->funcExeInst; } 2668777Sgblack@eecs.umich.edu 2675595Sgblack@eecs.umich.edu /** Returns pointer to the quiesce event. */ 2685595Sgblack@eecs.umich.edu virtual EndQuiesceEvent *getQuiesceEvent() 2695595Sgblack@eecs.umich.edu { 2705595Sgblack@eecs.umich.edu return this->thread->quiesceEvent; 2715595Sgblack@eecs.umich.edu } 2729382SAli.Saidi@ARM.com /** check if the cpu is currently in state update mode and squash if not. 2739382SAli.Saidi@ARM.com * This function will return true if a trap is pending or if a fault or 2749382SAli.Saidi@ARM.com * similar is currently writing to the thread context and doesn't want 2759382SAli.Saidi@ARM.com * reset all the state (see noSquashFromTC). 2769382SAli.Saidi@ARM.com */ 2779382SAli.Saidi@ARM.com inline void conditionalSquash() 2789382SAli.Saidi@ARM.com { 2799382SAli.Saidi@ARM.com if (!thread->trapPending && !thread->noSquashFromTC) 2809382SAli.Saidi@ARM.com cpu->squashFromTC(thread->threadId()); 2819382SAli.Saidi@ARM.com } 2825595Sgblack@eecs.umich.edu 2839426SAndreas.Sandberg@ARM.com virtual uint64_t readIntRegFlat(int idx); 2849426SAndreas.Sandberg@ARM.com virtual void setIntRegFlat(int idx, uint64_t val); 2859426SAndreas.Sandberg@ARM.com 2869426SAndreas.Sandberg@ARM.com virtual FloatReg readFloatRegFlat(int idx); 2879426SAndreas.Sandberg@ARM.com virtual void setFloatRegFlat(int idx, FloatReg val); 2889426SAndreas.Sandberg@ARM.com 2899426SAndreas.Sandberg@ARM.com virtual FloatRegBits readFloatRegBitsFlat(int idx); 2909426SAndreas.Sandberg@ARM.com virtual void setFloatRegBitsFlat(int idx, FloatRegBits val); 2912817Sksewell@umich.edu}; 2922817Sksewell@umich.edu 2932817Sksewell@umich.edu#endif 294