thread_context.hh revision 8799
112SN/A/* 21762SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 312SN/A * All rights reserved. 412SN/A * 512SN/A * Redistribution and use in source and binary forms, with or without 612SN/A * modification, are permitted provided that the following conditions are 712SN/A * met: redistributions of source code must retain the above copyright 812SN/A * notice, this list of conditions and the following disclaimer; 912SN/A * redistributions in binary form must reproduce the above copyright 1012SN/A * notice, this list of conditions and the following disclaimer in the 1112SN/A * documentation and/or other materials provided with the distribution; 1212SN/A * neither the name of the copyright holders nor the names of its 1312SN/A * contributors may be used to endorse or promote products derived from 1412SN/A * this software without specific prior written permission. 1512SN/A * 1612SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 2912SN/A */ 3012SN/A 3112SN/A#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 3212SN/A#define __CPU_O3_THREAD_CONTEXT_HH__ 3356SN/A 347676Snate@binkert.org#include "config/the_isa.hh" 352439SN/A#include "cpu/o3/isa_specific.hh" 367676Snate@binkert.org#include "cpu/thread_context.hh" 377676Snate@binkert.org 388232Snate@binkert.orgclass EndQuiesceEvent; 3912SN/Anamespace Kernel { 407676Snate@binkert.org class Statistics; 417676Snate@binkert.org}; 427676Snate@binkert.org 437676Snate@binkert.orgclass TranslatingPort; 447676Snate@binkert.org 4556SN/A/** 4656SN/A * Derived ThreadContext class for use with the O3CPU. It 477676Snate@binkert.org * provides the interface for any external objects to access a 4812SN/A * single thread's state and some general CPU state. Any time 4912SN/A * external objects try to update state through this interface, 5012SN/A * the CPU will create an event to squash all in-flight 5112SN/A * instructions in order to ensure state is maintained correctly. 5212SN/A * It must be defined specifically for the O3CPU because 5312SN/A * not all architectural state is located within the O3ThreadState 5412SN/A * (such as the commit PC, and registers), and specific actions 5512SN/A * must be taken when using this interface (such as squashing all 56360SN/A * in-flight instructions when doing a write to this interface). 57360SN/A */ 5812SN/Atemplate <class Impl> 5912SN/Aclass O3ThreadContext : public ThreadContext 6012SN/A{ 6112SN/A public: 6212SN/A typedef typename Impl::O3CPU O3CPU; 6312SN/A 6412SN/A /** Pointer to the CPU. */ 6512SN/A O3CPU *cpu; 66360SN/A 67360SN/A /** Pointer to the thread state that this TC corrseponds to. */ 68360SN/A O3ThreadState<Impl> *thread; 6912SN/A 7012SN/A /** Returns a pointer to the ITB. */ 7112SN/A TheISA::TLB *getITBPtr() { return cpu->itb; } 7212SN/A 7312SN/A /** Returns a pointer to the DTB. */ 7412SN/A TheISA::TLB *getDTBPtr() { return cpu->dtb; } 7512SN/A 7612SN/A Decoder *getDecoderPtr() { return &cpu->fetch.decoder; } 7712SN/A 782420SN/A /** Returns a pointer to this CPU. */ 7912SN/A virtual BaseCPU *getCpuPtr() { return cpu; } 8012SN/A 8112SN/A /** Reads this CPU's ID. */ 822420SN/A virtual int cpuId() { return cpu->cpuId(); } 8312SN/A 8412SN/A virtual int contextId() { return thread->contextId(); } 8512SN/A 862420SN/A virtual void setContextId(int id) { thread->setContextId(id); } 8712SN/A 8812SN/A /** Returns this thread's ID number. */ 8912SN/A virtual int threadId() { return thread->threadId(); } 9012SN/A virtual void setThreadId(int id) { return thread->setThreadId(id); } 9112SN/A 9212SN/A /** Returns a pointer to the system. */ 9312SN/A virtual System *getSystemPtr() { return cpu->system; } 9412SN/A 953812Ssaidi@eecs.umich.edu /** Returns a pointer to this thread's kernel statistics. */ 9612SN/A virtual TheISA::Kernel::Statistics *getKernelStats() 9712SN/A { return thread->kernelStats; } 9812SN/A 9912SN/A /** Returns a pointer to this thread's process. */ 10012SN/A virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 1011252SN/A 10212SN/A virtual PortProxy* getPhysProxy() { return thread->getPhysProxy(); } 10312SN/A 10412SN/A virtual FSTranslatingPortProxy* getVirtProxy(); 10512SN/A 10612SN/A virtual void initMemProxies(ThreadContext *tc) 1071252SN/A { thread->initMemProxies(tc); } 1081252SN/A 10912SN/A virtual SETranslatingPortProxy* getMemProxy() 11012SN/A { return thread->getMemProxy(); } 11112SN/A 11212SN/A /** Returns this thread's status. */ 11312SN/A virtual Status status() const { return thread->status(); } 11412SN/A 11512SN/A /** Sets this thread's status. */ 11612SN/A virtual void setStatus(Status new_status) 11712SN/A { thread->setStatus(new_status); } 11812SN/A 11912SN/A /** Set the status to Active. Optional delay indicates number of 12012SN/A * cycles to wait before beginning execution. */ 12112SN/A virtual void activate(int delay = 1); 12212SN/A 12312SN/A /** Set the status to Suspended. */ 1243812Ssaidi@eecs.umich.edu virtual void suspend(int delay = 0); 12512SN/A 12612SN/A /** Set the status to Halted. */ 12712SN/A virtual void halt(int delay = 0); 12812SN/A 12912SN/A /** Dumps the function profiling information. 1301252SN/A * @todo: Implement. 13112SN/A */ 13212SN/A virtual void dumpFuncProfile(); 13312SN/A 13412SN/A /** Takes over execution of a thread from another CPU. */ 13512SN/A virtual void takeOverFrom(ThreadContext *old_context); 1361252SN/A 1371252SN/A /** Registers statistics associated with this TC. */ 13812SN/A virtual void regStats(const std::string &name); 13912SN/A 14012SN/A /** Serializes state. */ 14112SN/A virtual void serialize(std::ostream &os); 14212SN/A /** Unserializes state. */ 14312SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 14412SN/A 14512SN/A /** Reads the last tick that this thread was activated on. */ 14612SN/A virtual Tick readLastActivate(); 14712SN/A /** Reads the last tick that this thread was suspended on. */ 14812SN/A virtual Tick readLastSuspend(); 14912SN/A 15012SN/A /** Clears the function profiling information. */ 15112SN/A virtual void profileClear(); 15212SN/A /** Samples the function profiling information. */ 15312SN/A virtual void profileSample(); 15412SN/A 15512SN/A /** Copies the architectural registers from another TC into this TC. */ 15612SN/A virtual void copyArchRegs(ThreadContext *tc); 15712SN/A 15812SN/A /** Resets all architectural registers to 0. */ 15912SN/A virtual void clearArchRegs(); 16012SN/A 16112SN/A /** Reads an integer register. */ 162 virtual uint64_t readIntReg(int reg_idx); 163 164 virtual FloatReg readFloatReg(int reg_idx); 165 166 virtual FloatRegBits readFloatRegBits(int reg_idx); 167 168 /** Sets an integer register to a value. */ 169 virtual void setIntReg(int reg_idx, uint64_t val); 170 171 virtual void setFloatReg(int reg_idx, FloatReg val); 172 173 virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 174 175 /** Reads this thread's PC state. */ 176 virtual TheISA::PCState pcState() 177 { return cpu->pcState(thread->threadId()); } 178 179 /** Sets this thread's PC state. */ 180 virtual void pcState(const TheISA::PCState &val); 181 182 /** Reads this thread's PC. */ 183 virtual Addr instAddr() 184 { return cpu->instAddr(thread->threadId()); } 185 186 /** Reads this thread's next PC. */ 187 virtual Addr nextInstAddr() 188 { return cpu->nextInstAddr(thread->threadId()); } 189 190 /** Reads this thread's next PC. */ 191 virtual MicroPC microPC() 192 { return cpu->microPC(thread->threadId()); } 193 194 /** Reads a miscellaneous register. */ 195 virtual MiscReg readMiscRegNoEffect(int misc_reg) 196 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 197 198 /** Reads a misc. register, including any side-effects the 199 * read might have as defined by the architecture. */ 200 virtual MiscReg readMiscReg(int misc_reg) 201 { return cpu->readMiscReg(misc_reg, thread->threadId()); } 202 203 /** Sets a misc. register. */ 204 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 205 206 /** Sets a misc. register, including any side-effects the 207 * write might have as defined by the architecture. */ 208 virtual void setMiscReg(int misc_reg, const MiscReg &val); 209 210 virtual int flattenIntIndex(int reg); 211 virtual int flattenFloatIndex(int reg); 212 213 /** Returns the number of consecutive store conditional failures. */ 214 // @todo: Figure out where these store cond failures should go. 215 virtual unsigned readStCondFailures() 216 { return thread->storeCondFailures; } 217 218 /** Sets the number of consecutive store conditional failures. */ 219 virtual void setStCondFailures(unsigned sc_failures) 220 { thread->storeCondFailures = sc_failures; } 221 222 // Only really makes sense for old CPU model. Lots of code 223 // outside the CPU still checks this function, so it will 224 // always return false to keep everything working. 225 /** Checks if the thread is misspeculating. Because it is 226 * very difficult to determine if the thread is 227 * misspeculating, this is set as false. */ 228 virtual bool misspeculating() { return false; } 229 230 /** Executes a syscall in SE mode. */ 231 virtual void syscall(int64_t callnum) 232 { return cpu->syscall(callnum, thread->threadId()); } 233 234 /** Reads the funcExeInst counter. */ 235 virtual Counter readFuncExeInst() { return thread->funcExeInst; } 236 237 /** Returns pointer to the quiesce event. */ 238 virtual EndQuiesceEvent *getQuiesceEvent() 239 { 240 return this->thread->quiesceEvent; 241 } 242 243}; 244 245#endif 246