thread_context.hh revision 7680
12817Sksewell@umich.edu/* 22817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32817Sksewell@umich.edu * All rights reserved. 42817Sksewell@umich.edu * 52817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu * this software without specific prior written permission. 152817Sksewell@umich.edu * 162817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * Authors: Kevin Lim 292817Sksewell@umich.edu */ 302817Sksewell@umich.edu 312817Sksewell@umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 322817Sksewell@umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 332817Sksewell@umich.edu 346658Snate@binkert.org#include "config/the_isa.hh" 352935Sksewell@umich.edu#include "cpu/thread_context.hh" 362817Sksewell@umich.edu#include "cpu/o3/isa_specific.hh" 372817Sksewell@umich.edu 382834Sksewell@umich.educlass EndQuiesceEvent; 392834Sksewell@umich.edunamespace Kernel { 402834Sksewell@umich.edu class Statistics; 412834Sksewell@umich.edu}; 422834Sksewell@umich.edu 432834Sksewell@umich.educlass TranslatingPort; 442834Sksewell@umich.edu 452817Sksewell@umich.edu/** 462817Sksewell@umich.edu * Derived ThreadContext class for use with the O3CPU. It 472817Sksewell@umich.edu * provides the interface for any external objects to access a 482817Sksewell@umich.edu * single thread's state and some general CPU state. Any time 492817Sksewell@umich.edu * external objects try to update state through this interface, 502817Sksewell@umich.edu * the CPU will create an event to squash all in-flight 512817Sksewell@umich.edu * instructions in order to ensure state is maintained correctly. 522817Sksewell@umich.edu * It must be defined specifically for the O3CPU because 532817Sksewell@umich.edu * not all architectural state is located within the O3ThreadState 542817Sksewell@umich.edu * (such as the commit PC, and registers), and specific actions 552817Sksewell@umich.edu * must be taken when using this interface (such as squashing all 562817Sksewell@umich.edu * in-flight instructions when doing a write to this interface). 572817Sksewell@umich.edu */ 582817Sksewell@umich.edutemplate <class Impl> 592817Sksewell@umich.educlass O3ThreadContext : public ThreadContext 602817Sksewell@umich.edu{ 612817Sksewell@umich.edu public: 622817Sksewell@umich.edu typedef typename Impl::O3CPU O3CPU; 632817Sksewell@umich.edu 642817Sksewell@umich.edu /** Pointer to the CPU. */ 652817Sksewell@umich.edu O3CPU *cpu; 662817Sksewell@umich.edu 672817Sksewell@umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 682817Sksewell@umich.edu O3ThreadState<Impl> *thread; 692817Sksewell@umich.edu 703784Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 716022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return cpu->itb; } 723784Sgblack@eecs.umich.edu 733784Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 746022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return cpu->dtb; } 753784Sgblack@eecs.umich.edu 762817Sksewell@umich.edu /** Returns a pointer to this CPU. */ 772817Sksewell@umich.edu virtual BaseCPU *getCpuPtr() { return cpu; } 782817Sksewell@umich.edu 792817Sksewell@umich.edu /** Reads this CPU's ID. */ 805712Shsul@eecs.umich.edu virtual int cpuId() { return cpu->cpuId(); } 812817Sksewell@umich.edu 825714Shsul@eecs.umich.edu virtual int contextId() { return thread->contextId(); } 835714Shsul@eecs.umich.edu 845714Shsul@eecs.umich.edu virtual void setContextId(int id) { thread->setContextId(id); } 855714Shsul@eecs.umich.edu 865715Shsul@eecs.umich.edu /** Returns this thread's ID number. */ 875715Shsul@eecs.umich.edu virtual int threadId() { return thread->threadId(); } 885715Shsul@eecs.umich.edu virtual void setThreadId(int id) { return thread->setThreadId(id); } 895715Shsul@eecs.umich.edu 902817Sksewell@umich.edu /** Returns a pointer to the system. */ 912817Sksewell@umich.edu virtual System *getSystemPtr() { return cpu->system; } 922817Sksewell@umich.edu 935803Snate@binkert.org#if FULL_SYSTEM 942817Sksewell@umich.edu /** Returns a pointer to this thread's kernel statistics. */ 953548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() 962817Sksewell@umich.edu { return thread->kernelStats; } 972817Sksewell@umich.edu 982817Sksewell@umich.edu virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } 992817Sksewell@umich.edu 1005499Ssaidi@eecs.umich.edu virtual VirtualPort *getVirtPort(); 1013675Sktlim@umich.edu 1025497Ssaidi@eecs.umich.edu virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); } 1032817Sksewell@umich.edu#else 1042817Sksewell@umich.edu virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } 1052817Sksewell@umich.edu 1062817Sksewell@umich.edu /** Returns a pointer to this thread's process. */ 1072817Sksewell@umich.edu virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 1082817Sksewell@umich.edu#endif 1092817Sksewell@umich.edu /** Returns this thread's status. */ 1102817Sksewell@umich.edu virtual Status status() const { return thread->status(); } 1112817Sksewell@umich.edu 1122817Sksewell@umich.edu /** Sets this thread's status. */ 1132817Sksewell@umich.edu virtual void setStatus(Status new_status) 1142817Sksewell@umich.edu { thread->setStatus(new_status); } 1152817Sksewell@umich.edu 1162817Sksewell@umich.edu /** Set the status to Active. Optional delay indicates number of 1172817Sksewell@umich.edu * cycles to wait before beginning execution. */ 1182817Sksewell@umich.edu virtual void activate(int delay = 1); 1192817Sksewell@umich.edu 1202817Sksewell@umich.edu /** Set the status to Suspended. */ 1215250Sksewell@umich.edu virtual void suspend(int delay = 0); 1222817Sksewell@umich.edu 1232817Sksewell@umich.edu /** Set the status to Halted. */ 1245250Sksewell@umich.edu virtual void halt(int delay = 0); 1252817Sksewell@umich.edu 1262817Sksewell@umich.edu#if FULL_SYSTEM 1272817Sksewell@umich.edu /** Dumps the function profiling information. 1282817Sksewell@umich.edu * @todo: Implement. 1292817Sksewell@umich.edu */ 1302817Sksewell@umich.edu virtual void dumpFuncProfile(); 1312817Sksewell@umich.edu#endif 1322817Sksewell@umich.edu /** Takes over execution of a thread from another CPU. */ 1332817Sksewell@umich.edu virtual void takeOverFrom(ThreadContext *old_context); 1342817Sksewell@umich.edu 1352817Sksewell@umich.edu /** Registers statistics associated with this TC. */ 1362817Sksewell@umich.edu virtual void regStats(const std::string &name); 1372817Sksewell@umich.edu 1382817Sksewell@umich.edu /** Serializes state. */ 1392817Sksewell@umich.edu virtual void serialize(std::ostream &os); 1402817Sksewell@umich.edu /** Unserializes state. */ 1412817Sksewell@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1422817Sksewell@umich.edu 1432817Sksewell@umich.edu#if FULL_SYSTEM 1442817Sksewell@umich.edu /** Reads the last tick that this thread was activated on. */ 1452817Sksewell@umich.edu virtual Tick readLastActivate(); 1462817Sksewell@umich.edu /** Reads the last tick that this thread was suspended on. */ 1472817Sksewell@umich.edu virtual Tick readLastSuspend(); 1482817Sksewell@umich.edu 1492817Sksewell@umich.edu /** Clears the function profiling information. */ 1502817Sksewell@umich.edu virtual void profileClear(); 1512817Sksewell@umich.edu /** Samples the function profiling information. */ 1522817Sksewell@umich.edu virtual void profileSample(); 1532817Sksewell@umich.edu#endif 1542817Sksewell@umich.edu 1552817Sksewell@umich.edu /** Copies the architectural registers from another TC into this TC. */ 1562817Sksewell@umich.edu virtual void copyArchRegs(ThreadContext *tc); 1572817Sksewell@umich.edu 1582817Sksewell@umich.edu /** Resets all architectural registers to 0. */ 1592817Sksewell@umich.edu virtual void clearArchRegs(); 1602817Sksewell@umich.edu 1612817Sksewell@umich.edu /** Reads an integer register. */ 1622817Sksewell@umich.edu virtual uint64_t readIntReg(int reg_idx); 1632817Sksewell@umich.edu 1642817Sksewell@umich.edu virtual FloatReg readFloatReg(int reg_idx); 1652817Sksewell@umich.edu 1662817Sksewell@umich.edu virtual FloatRegBits readFloatRegBits(int reg_idx); 1672817Sksewell@umich.edu 1682817Sksewell@umich.edu /** Sets an integer register to a value. */ 1692817Sksewell@umich.edu virtual void setIntReg(int reg_idx, uint64_t val); 1702817Sksewell@umich.edu 1712817Sksewell@umich.edu virtual void setFloatReg(int reg_idx, FloatReg val); 1722817Sksewell@umich.edu 1732817Sksewell@umich.edu virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 1742817Sksewell@umich.edu 1752817Sksewell@umich.edu /** Reads this thread's PC. */ 1762817Sksewell@umich.edu virtual uint64_t readPC() 1775715Shsul@eecs.umich.edu { return cpu->readPC(thread->threadId()); } 1782817Sksewell@umich.edu 1792817Sksewell@umich.edu /** Sets this thread's PC. */ 1802817Sksewell@umich.edu virtual void setPC(uint64_t val); 1812817Sksewell@umich.edu 1822817Sksewell@umich.edu /** Reads this thread's next PC. */ 1832817Sksewell@umich.edu virtual uint64_t readNextPC() 1845715Shsul@eecs.umich.edu { return cpu->readNextPC(thread->threadId()); } 1852817Sksewell@umich.edu 1862817Sksewell@umich.edu /** Sets this thread's next PC. */ 1872817Sksewell@umich.edu virtual void setNextPC(uint64_t val); 1882817Sksewell@umich.edu 1895259Sksewell@umich.edu virtual uint64_t readMicroPC() 1905715Shsul@eecs.umich.edu { return cpu->readMicroPC(thread->threadId()); } 1915259Sksewell@umich.edu 1925259Sksewell@umich.edu virtual void setMicroPC(uint64_t val); 1935259Sksewell@umich.edu 1945259Sksewell@umich.edu virtual uint64_t readNextMicroPC() 1955715Shsul@eecs.umich.edu { return cpu->readNextMicroPC(thread->threadId()); } 1965259Sksewell@umich.edu 1975259Sksewell@umich.edu virtual void setNextMicroPC(uint64_t val); 1985259Sksewell@umich.edu 1992817Sksewell@umich.edu /** Reads a miscellaneous register. */ 2004172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) 2015715Shsul@eecs.umich.edu { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 2024172Ssaidi@eecs.umich.edu 2034172Ssaidi@eecs.umich.edu /** Reads a misc. register, including any side-effects the 2044172Ssaidi@eecs.umich.edu * read might have as defined by the architecture. */ 2052817Sksewell@umich.edu virtual MiscReg readMiscReg(int misc_reg) 2065715Shsul@eecs.umich.edu { return cpu->readMiscReg(misc_reg, thread->threadId()); } 2072817Sksewell@umich.edu 2082817Sksewell@umich.edu /** Sets a misc. register. */ 2094172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 2102817Sksewell@umich.edu 2112817Sksewell@umich.edu /** Sets a misc. register, including any side-effects the 2122817Sksewell@umich.edu * write might have as defined by the architecture. */ 2134172Ssaidi@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val); 2142817Sksewell@umich.edu 2156313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg); 2166313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg); 2176313Sgblack@eecs.umich.edu 2182817Sksewell@umich.edu /** Returns the number of consecutive store conditional failures. */ 2192817Sksewell@umich.edu // @todo: Figure out where these store cond failures should go. 2202817Sksewell@umich.edu virtual unsigned readStCondFailures() 2212817Sksewell@umich.edu { return thread->storeCondFailures; } 2222817Sksewell@umich.edu 2232817Sksewell@umich.edu /** Sets the number of consecutive store conditional failures. */ 2242817Sksewell@umich.edu virtual void setStCondFailures(unsigned sc_failures) 2252817Sksewell@umich.edu { thread->storeCondFailures = sc_failures; } 2262817Sksewell@umich.edu 2272817Sksewell@umich.edu // Only really makes sense for old CPU model. Lots of code 2282817Sksewell@umich.edu // outside the CPU still checks this function, so it will 2292817Sksewell@umich.edu // always return false to keep everything working. 2302817Sksewell@umich.edu /** Checks if the thread is misspeculating. Because it is 2312817Sksewell@umich.edu * very difficult to determine if the thread is 2322817Sksewell@umich.edu * misspeculating, this is set as false. */ 2332817Sksewell@umich.edu virtual bool misspeculating() { return false; } 2342817Sksewell@umich.edu 2352817Sksewell@umich.edu#if !FULL_SYSTEM 2362817Sksewell@umich.edu /** Executes a syscall in SE mode. */ 2372817Sksewell@umich.edu virtual void syscall(int64_t callnum) 2385715Shsul@eecs.umich.edu { return cpu->syscall(callnum, thread->threadId()); } 2392817Sksewell@umich.edu 2402817Sksewell@umich.edu /** Reads the funcExeInst counter. */ 2412817Sksewell@umich.edu virtual Counter readFuncExeInst() { return thread->funcExeInst; } 2425595Sgblack@eecs.umich.edu#else 2435595Sgblack@eecs.umich.edu /** Returns pointer to the quiesce event. */ 2445595Sgblack@eecs.umich.edu virtual EndQuiesceEvent *getQuiesceEvent() 2455595Sgblack@eecs.umich.edu { 2465595Sgblack@eecs.umich.edu return this->thread->quiesceEvent; 2475595Sgblack@eecs.umich.edu } 2482817Sksewell@umich.edu#endif 2495595Sgblack@eecs.umich.edu 2505595Sgblack@eecs.umich.edu virtual uint64_t readNextNPC() 2515595Sgblack@eecs.umich.edu { 2525715Shsul@eecs.umich.edu return this->cpu->readNextNPC(this->thread->threadId()); 2535595Sgblack@eecs.umich.edu } 2545595Sgblack@eecs.umich.edu 2555595Sgblack@eecs.umich.edu virtual void setNextNPC(uint64_t val) 2565595Sgblack@eecs.umich.edu { 2575715Shsul@eecs.umich.edu this->cpu->setNextNPC(val, this->thread->threadId()); 2585595Sgblack@eecs.umich.edu } 2592817Sksewell@umich.edu}; 2602817Sksewell@umich.edu 2612817Sksewell@umich.edu#endif 262