thread_context.hh revision 5595
16899SN/A/* 26899SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 36899SN/A * All rights reserved. 46899SN/A * 56899SN/A * Redistribution and use in source and binary forms, with or without 66899SN/A * modification, are permitted provided that the following conditions are 76899SN/A * met: redistributions of source code must retain the above copyright 86899SN/A * notice, this list of conditions and the following disclaimer; 96899SN/A * redistributions in binary form must reproduce the above copyright 106899SN/A * notice, this list of conditions and the following disclaimer in the 116899SN/A * documentation and/or other materials provided with the distribution; 126899SN/A * neither the name of the copyright holders nor the names of its 136899SN/A * contributors may be used to endorse or promote products derived from 146899SN/A * this software without specific prior written permission. 156899SN/A * 166899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276899SN/A * 286899SN/A * Authors: Kevin Lim 296899SN/A */ 3010348Sandreas.hansson@arm.com 317632SBrad.Beckmann@amd.com#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 328232Snate@binkert.org#define __CPU_O3_THREAD_CONTEXT_HH__ 337053SN/A 346899SN/A#include "cpu/thread_context.hh" 357053SN/A#include "cpu/o3/isa_specific.hh" 367053SN/A 3711025Snilay@cs.wisc.educlass EndQuiesceEvent; 3811025Snilay@cs.wisc.edunamespace Kernel { 398932SBrad.Beckmann@amd.com class Statistics; 408932SBrad.Beckmann@amd.com}; 416899SN/A 427053SN/Aclass TranslatingPort; 436899SN/A 447053SN/A/** 457053SN/A * Derived ThreadContext class for use with the O3CPU. It 467053SN/A * provides the interface for any external objects to access a 477053SN/A * single thread's state and some general CPU state. Any time 4810348Sandreas.hansson@arm.com * external objects try to update state through this interface, 4910348Sandreas.hansson@arm.com * the CPU will create an event to squash all in-flight 507053SN/A * instructions in order to ensure state is maintained correctly. 516899SN/A * It must be defined specifically for the O3CPU because 526899SN/A * not all architectural state is located within the O3ThreadState 537053SN/A * (such as the commit PC, and registers), and specific actions 547053SN/A * must be taken when using this interface (such as squashing all 556899SN/A * in-flight instructions when doing a write to this interface). 567053SN/A */ 577053SN/Atemplate <class Impl> 586899SN/Aclass O3ThreadContext : public ThreadContext 597053SN/A{ 6010348Sandreas.hansson@arm.com public: 617053SN/A typedef typename Impl::O3CPU O3CPU; 627053SN/A 636899SN/A /** Pointer to the CPU. */ 6410348Sandreas.hansson@arm.com O3CPU *cpu; 658184Ssomayeh@cs.wisc.edu 668184Ssomayeh@cs.wisc.edu /** Pointer to the thread state that this TC corrseponds to. */ 678184Ssomayeh@cs.wisc.edu O3ThreadState<Impl> *thread; 687053SN/A 697053SN/A /** Returns a pointer to the ITB. */ 707053SN/A TheISA::ITB *getITBPtr() { return cpu->itb; } 717053SN/A 727053SN/A /** Returns a pointer to the DTB. */ 737053SN/A TheISA::DTB *getDTBPtr() { return cpu->dtb; } 747053SN/A 757053SN/A /** Returns a pointer to this CPU. */ 767053SN/A virtual BaseCPU *getCpuPtr() { return cpu; } 776899SN/A 786899SN/A /** Sets this CPU's ID. */ 797053SN/A virtual void setCpuId(int id) { cpu->setCpuId(id); } 807053SN/A 816899SN/A /** Reads this CPU's ID. */ 827053SN/A virtual int readCpuId() { return cpu->readCpuId(); } 836899SN/A 8410348Sandreas.hansson@arm.com#if FULL_SYSTEM 858950Sandreas.hansson@arm.com /** Returns a pointer to the system. */ 866899SN/A virtual System *getSystemPtr() { return cpu->system; } 877053SN/A 887053SN/A /** Returns a pointer to physical memory. */ 896899SN/A virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } 907053SN/A 916899SN/A /** Returns a pointer to this thread's kernel statistics. */ 927053SN/A virtual TheISA::Kernel::Statistics *getKernelStats() 9310348Sandreas.hansson@arm.com { return thread->kernelStats; } 947053SN/A 957053SN/A virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } 968932SBrad.Beckmann@amd.com 9711266SBrad.Beckmann@amd.com virtual VirtualPort *getVirtPort(); 9811266SBrad.Beckmann@amd.com 9911266SBrad.Beckmann@amd.com virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); } 1007053SN/A#else 1017053SN/A virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } 1027053SN/A 1037053SN/A /** Returns a pointer to this thread's process. */ 1047053SN/A virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 1056899SN/A#endif 1066899SN/A /** Returns this thread's status. */ 1077568SN/A virtual Status status() const { return thread->status(); } 10811025Snilay@cs.wisc.edu 10911025Snilay@cs.wisc.edu /** Sets this thread's status. */ 11011435Smitch.hayenga@arm.com virtual void setStatus(Status new_status) 1117568SN/A { thread->setStatus(new_status); } 1128949Sandreas.hansson@arm.com 11310562Sandreas.hansson@arm.com /** Set the status to Active. Optional delay indicates number of 11410562Sandreas.hansson@arm.com * cycles to wait before beginning execution. */ 11510562Sandreas.hansson@arm.com virtual void activate(int delay = 1); 11610566Sandreas.hansson@arm.com 11710562Sandreas.hansson@arm.com /** Set the status to Suspended. */ 1186899SN/A virtual void suspend(int delay = 0); 1197053SN/A 1207053SN/A /** Set the status to Unallocated. */ 1219542Sandreas.hansson@arm.com virtual void deallocate(int delay = 0); 1226899SN/A 1238975Sandreas.hansson@arm.com /** Set the status to Halted. */ 1247053SN/A virtual void halt(int delay = 0); 1257053SN/A 1267053SN/A#if FULL_SYSTEM 1279542Sandreas.hansson@arm.com /** Dumps the function profiling information. 1287053SN/A * @todo: Implement. 1297053SN/A */ 1306899SN/A virtual void dumpFuncProfile(); 1317053SN/A#endif 1327053SN/A /** Takes over execution of a thread from another CPU. */ 1337053SN/A virtual void takeOverFrom(ThreadContext *old_context); 1346899SN/A 1356899SN/A /** Registers statistics associated with this TC. */ 1367053SN/A virtual void regStats(const std::string &name); 1378184Ssomayeh@cs.wisc.edu 1388184Ssomayeh@cs.wisc.edu /** Serializes state. */ 1398184Ssomayeh@cs.wisc.edu virtual void serialize(std::ostream &os); 1408184Ssomayeh@cs.wisc.edu /** Unserializes state. */ 1418184Ssomayeh@cs.wisc.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 14210348Sandreas.hansson@arm.com 1438950Sandreas.hansson@arm.com#if FULL_SYSTEM 1448184Ssomayeh@cs.wisc.edu /** Reads the last tick that this thread was activated on. */ 1458184Ssomayeh@cs.wisc.edu virtual Tick readLastActivate(); 1468184Ssomayeh@cs.wisc.edu /** Reads the last tick that this thread was suspended on. */ 14711025Snilay@cs.wisc.edu virtual Tick readLastSuspend(); 14811025Snilay@cs.wisc.edu 1498184Ssomayeh@cs.wisc.edu /** Clears the function profiling information. */ 1508184Ssomayeh@cs.wisc.edu virtual void profileClear(); 1518184Ssomayeh@cs.wisc.edu /** Samples the function profiling information. */ 1528184Ssomayeh@cs.wisc.edu virtual void profileSample(); 1538184Ssomayeh@cs.wisc.edu#endif 1548949Sandreas.hansson@arm.com /** Returns this thread's ID number. */ 1558184Ssomayeh@cs.wisc.edu virtual int getThreadNum() { return thread->readTid(); } 1568184Ssomayeh@cs.wisc.edu 1578184Ssomayeh@cs.wisc.edu /** Returns the instruction this thread is currently committing. 1589542Sandreas.hansson@arm.com * Only used when an instruction faults. 1598184Ssomayeh@cs.wisc.edu */ 1608975Sandreas.hansson@arm.com virtual TheISA::MachInst getInst(); 1618184Ssomayeh@cs.wisc.edu 1628184Ssomayeh@cs.wisc.edu /** Copies the architectural registers from another TC into this TC. */ 1638184Ssomayeh@cs.wisc.edu virtual void copyArchRegs(ThreadContext *tc); 1648184Ssomayeh@cs.wisc.edu 1658184Ssomayeh@cs.wisc.edu /** Resets all architectural registers to 0. */ 1667053SN/A virtual void clearArchRegs(); 1676899SN/A 1687053SN/A /** Reads an integer register. */ 1697053SN/A virtual uint64_t readIntReg(int reg_idx); 1706899SN/A 17110348Sandreas.hansson@arm.com virtual FloatReg readFloatReg(int reg_idx, int width); 1728950Sandreas.hansson@arm.com 1736899SN/A virtual FloatReg readFloatReg(int reg_idx); 1747053SN/A 1756899SN/A virtual FloatRegBits readFloatRegBits(int reg_idx, int width); 1767053SN/A 17711025Snilay@cs.wisc.edu virtual FloatRegBits readFloatRegBits(int reg_idx); 1786899SN/A 1797053SN/A /** Sets an integer register to a value. */ 18011025Snilay@cs.wisc.edu virtual void setIntReg(int reg_idx, uint64_t val); 18111025Snilay@cs.wisc.edu 1826899SN/A virtual void setFloatReg(int reg_idx, FloatReg val, int width); 18311435Smitch.hayenga@arm.com 1847053SN/A virtual void setFloatReg(int reg_idx, FloatReg val); 1857053SN/A 1867053SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 1877053SN/A 1887053SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 1897053SN/A 1906899SN/A /** Reads this thread's PC. */ 1917053SN/A virtual uint64_t readPC() 1926899SN/A { return cpu->readPC(thread->readTid()); } 1938949Sandreas.hansson@arm.com 19410566Sandreas.hansson@arm.com /** Sets this thread's PC. */ 1957053SN/A virtual void setPC(uint64_t val); 1967053SN/A 1976899SN/A /** Reads this thread's next PC. */ 19811266SBrad.Beckmann@amd.com virtual uint64_t readNextPC() 19910563Sandreas.hansson@arm.com { return cpu->readNextPC(thread->readTid()); } 2006899SN/A 2017053SN/A /** Sets this thread's next PC. */ 2027053SN/A virtual void setNextPC(uint64_t val); 2039542Sandreas.hansson@arm.com 2046899SN/A virtual uint64_t readMicroPC() 2058975Sandreas.hansson@arm.com { return cpu->readMicroPC(thread->readTid()); } 2067053SN/A 2077053SN/A virtual void setMicroPC(uint64_t val); 2087053SN/A 2097053SN/A virtual uint64_t readNextMicroPC() 21011266SBrad.Beckmann@amd.com { return cpu->readNextMicroPC(thread->readTid()); } 2117053SN/A 2127053SN/A virtual void setNextMicroPC(uint64_t val); 2137053SN/A 2147053SN/A /** Reads a miscellaneous register. */ 2159542Sandreas.hansson@arm.com virtual MiscReg readMiscRegNoEffect(int misc_reg) 2167053SN/A { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); } 2177053SN/A 2187053SN/A /** Reads a misc. register, including any side-effects the 2197053SN/A * read might have as defined by the architecture. */ 2207053SN/A virtual MiscReg readMiscReg(int misc_reg) 2217053SN/A { return cpu->readMiscReg(misc_reg, thread->readTid()); } 2227053SN/A 2236899SN/A /** Sets a misc. register. */ 2246899SN/A virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 2256899SN/A 2267053SN/A /** Sets a misc. register, including any side-effects the 2277053SN/A * write might have as defined by the architecture. */ 2286899SN/A virtual void setMiscReg(int misc_reg, const MiscReg &val); 2297053SN/A 2307053SN/A /** Returns the number of consecutive store conditional failures. */ 2316899SN/A // @todo: Figure out where these store cond failures should go. 23210348Sandreas.hansson@arm.com virtual unsigned readStCondFailures() 2338950Sandreas.hansson@arm.com { return thread->storeCondFailures; } 2346899SN/A 2357053SN/A /** Sets the number of consecutive store conditional failures. */ 2366899SN/A virtual void setStCondFailures(unsigned sc_failures) 2378932SBrad.Beckmann@amd.com { thread->storeCondFailures = sc_failures; } 23811266SBrad.Beckmann@amd.com 23911266SBrad.Beckmann@amd.com // Only really makes sense for old CPU model. Lots of code 24011266SBrad.Beckmann@amd.com // outside the CPU still checks this function, so it will 2417053SN/A // always return false to keep everything working. 2427053SN/A /** Checks if the thread is misspeculating. Because it is 2436899SN/A * very difficult to determine if the thread is 2447568SN/A * misspeculating, this is set as false. */ 24511025Snilay@cs.wisc.edu virtual bool misspeculating() { return false; } 24611025Snilay@cs.wisc.edu 2477568SN/A#if !FULL_SYSTEM 24811435Smitch.hayenga@arm.com /** Gets a syscall argument by index. */ 2498949Sandreas.hansson@arm.com virtual IntReg getSyscallArg(int i); 2509208Snilay@cs.wisc.edu 25110566Sandreas.hansson@arm.com /** Sets a syscall argument. */ 2526899SN/A virtual void setSyscallArg(int i, IntReg val); 25311266SBrad.Beckmann@amd.com 25411266SBrad.Beckmann@amd.com /** Sets the syscall return value. */ 2557053SN/A virtual void setSyscallReturn(SyscallReturn return_value); 2567053SN/A 2579542Sandreas.hansson@arm.com /** Executes a syscall in SE mode. */ 2586899SN/A virtual void syscall(int64_t callnum) 2598975Sandreas.hansson@arm.com { return cpu->syscall(callnum, thread->readTid()); } 2607053SN/A 2617053SN/A /** Reads the funcExeInst counter. */ 2627053SN/A virtual Counter readFuncExeInst() { return thread->funcExeInst; } 2637053SN/A#else 26411266SBrad.Beckmann@amd.com /** Returns pointer to the quiesce event. */ 2657053SN/A virtual EndQuiesceEvent *getQuiesceEvent() 2667053SN/A { 2677053SN/A return this->thread->quiesceEvent; 2687053SN/A } 2699542Sandreas.hansson@arm.com#endif 2707053SN/A 2717053SN/A virtual uint64_t readNextNPC() 2726899SN/A { 2737053SN/A return this->cpu->readNextNPC(this->thread->readTid()); 2747053SN/A } 2757053SN/A 2767053SN/A virtual void setNextNPC(uint64_t val) 2777053SN/A { 2786899SN/A#if THE_ISA == ALPHA_ISA 2796899SN/A panic("Not supported on Alpha!"); 2807053SN/A#endif 28110302Snilay@cs.wisc.edu this->cpu->setNextNPC(val, this->thread->readTid()); 2826899SN/A } 28311025Snilay@cs.wisc.edu 2846899SN/A virtual void changeRegFileContext(TheISA::RegContextParam param, 2857053SN/A TheISA::RegContextVal val) 2867053SN/A { 2876899SN/A#if THE_ISA != SPARC_ISA 28811025Snilay@cs.wisc.edu panic("changeRegFileContext not implemented."); 2897053SN/A#endif 2907053SN/A } 2917053SN/A 2926899SN/A 2936899SN/A /** This function exits the thread context in the CPU and returns 2947053SN/A * 1 if the CPU has no more active threads (meaning it's OK to exit); 2957053SN/A * Used in syscall-emulation mode when a thread executes the 'exit' 2967053SN/A * syscall. 2977053SN/A */ 2987053SN/A virtual int exit() 2997053SN/A { 3007053SN/A this->deallocate(); 3017053SN/A 30211266SBrad.Beckmann@amd.com // If there are still threads executing in the system 3037053SN/A if (this->cpu->numActiveThreads()) 3047053SN/A return 0; // don't exit simulation 30511266SBrad.Beckmann@amd.com else 30611266SBrad.Beckmann@amd.com return 1; // exit simulation 3077053SN/A } 3087053SN/A}; 3097053SN/A 3107053SN/A#endif 3117053SN/A