thread_context.hh revision 13628
12817Sksewell@umich.edu/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 162817Sksewell@umich.edu * All rights reserved. 172817Sksewell@umich.edu * 182817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272817Sksewell@umich.edu * this software without specific prior written permission. 282817Sksewell@umich.edu * 292817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402817Sksewell@umich.edu * 412817Sksewell@umich.edu * Authors: Kevin Lim 422817Sksewell@umich.edu */ 432817Sksewell@umich.edu 442817Sksewell@umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 452817Sksewell@umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 462817Sksewell@umich.edu 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 492935Sksewell@umich.edu#include "cpu/thread_context.hh" 502817Sksewell@umich.edu 512834Sksewell@umich.educlass EndQuiesceEvent; 522834Sksewell@umich.edunamespace Kernel { 532834Sksewell@umich.edu class Statistics; 548902Sandreas.hansson@arm.com} 552834Sksewell@umich.edu 562817Sksewell@umich.edu/** 572817Sksewell@umich.edu * Derived ThreadContext class for use with the O3CPU. It 582817Sksewell@umich.edu * provides the interface for any external objects to access a 592817Sksewell@umich.edu * single thread's state and some general CPU state. Any time 602817Sksewell@umich.edu * external objects try to update state through this interface, 612817Sksewell@umich.edu * the CPU will create an event to squash all in-flight 622817Sksewell@umich.edu * instructions in order to ensure state is maintained correctly. 632817Sksewell@umich.edu * It must be defined specifically for the O3CPU because 642817Sksewell@umich.edu * not all architectural state is located within the O3ThreadState 652817Sksewell@umich.edu * (such as the commit PC, and registers), and specific actions 662817Sksewell@umich.edu * must be taken when using this interface (such as squashing all 672817Sksewell@umich.edu * in-flight instructions when doing a write to this interface). 682817Sksewell@umich.edu */ 692817Sksewell@umich.edutemplate <class Impl> 702817Sksewell@umich.educlass O3ThreadContext : public ThreadContext 712817Sksewell@umich.edu{ 722817Sksewell@umich.edu public: 732817Sksewell@umich.edu typedef typename Impl::O3CPU O3CPU; 742817Sksewell@umich.edu 752817Sksewell@umich.edu /** Pointer to the CPU. */ 762817Sksewell@umich.edu O3CPU *cpu; 772817Sksewell@umich.edu 782817Sksewell@umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 792817Sksewell@umich.edu O3ThreadState<Impl> *thread; 802817Sksewell@umich.edu 813784Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 8213628SAndrea.Mondelli@ucf.edu BaseTLB *getITBPtr() override { return cpu->itb; } 833784Sgblack@eecs.umich.edu 843784Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 8513628SAndrea.Mondelli@ucf.edu BaseTLB *getDTBPtr() override { return cpu->dtb; } 863784Sgblack@eecs.umich.edu 8713628SAndrea.Mondelli@ucf.edu CheckerCPU *getCheckerCpuPtr() override { return NULL; } 888733Sgeoffrey.blake@arm.com 899023Sgblack@eecs.umich.edu TheISA::Decoder * 9013628SAndrea.Mondelli@ucf.edu getDecoderPtr() override 919023Sgblack@eecs.umich.edu { 929023Sgblack@eecs.umich.edu return cpu->fetch.decoder[thread->threadId()]; 939023Sgblack@eecs.umich.edu } 948541Sgblack@eecs.umich.edu 952817Sksewell@umich.edu /** Returns a pointer to this CPU. */ 9613628SAndrea.Mondelli@ucf.edu virtual BaseCPU *getCpuPtr() override { return cpu; } 972817Sksewell@umich.edu 982817Sksewell@umich.edu /** Reads this CPU's ID. */ 9913628SAndrea.Mondelli@ucf.edu virtual int cpuId() const override { return cpu->cpuId(); } 1002817Sksewell@umich.edu 10110190Sakash.bagdia@arm.com /** Reads this CPU's Socket ID. */ 10213628SAndrea.Mondelli@ucf.edu virtual uint32_t socketId() const override { return cpu->socketId(); } 10310190Sakash.bagdia@arm.com 10413628SAndrea.Mondelli@ucf.edu virtual ContextID 10513628SAndrea.Mondelli@ucf.edu contextId() const override { return thread->contextId(); } 1065714Shsul@eecs.umich.edu 10713628SAndrea.Mondelli@ucf.edu virtual void setContextId(int id) override { thread->setContextId(id); } 1085714Shsul@eecs.umich.edu 1095715Shsul@eecs.umich.edu /** Returns this thread's ID number. */ 11013628SAndrea.Mondelli@ucf.edu virtual int threadId() const override 11113628SAndrea.Mondelli@ucf.edu { return thread->threadId(); } 11213628SAndrea.Mondelli@ucf.edu virtual void setThreadId(int id) override 11313628SAndrea.Mondelli@ucf.edu { return thread->setThreadId(id); } 1145715Shsul@eecs.umich.edu 1152817Sksewell@umich.edu /** Returns a pointer to the system. */ 11613628SAndrea.Mondelli@ucf.edu virtual System *getSystemPtr() override { return cpu->system; } 1172817Sksewell@umich.edu 1182817Sksewell@umich.edu /** Returns a pointer to this thread's kernel statistics. */ 11913628SAndrea.Mondelli@ucf.edu virtual TheISA::Kernel::Statistics *getKernelStats() override 1202817Sksewell@umich.edu { return thread->kernelStats; } 1212817Sksewell@umich.edu 1228541Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 12313628SAndrea.Mondelli@ucf.edu virtual Process *getProcessPtr() override 12413628SAndrea.Mondelli@ucf.edu { return thread->getProcessPtr(); } 1258754Sgblack@eecs.umich.edu 12613628SAndrea.Mondelli@ucf.edu virtual void setProcessPtr(Process *p) override 12713628SAndrea.Mondelli@ucf.edu { thread->setProcessPtr(p); } 12811886Sbrandon.potter@amd.com 12913628SAndrea.Mondelli@ucf.edu virtual PortProxy &getPhysProxy() override 13013628SAndrea.Mondelli@ucf.edu { return thread->getPhysProxy(); } 1312817Sksewell@umich.edu 13213628SAndrea.Mondelli@ucf.edu virtual FSTranslatingPortProxy &getVirtProxy() override; 1333675Sktlim@umich.edu 13413628SAndrea.Mondelli@ucf.edu virtual void initMemProxies(ThreadContext *tc) override 1358706Sandreas.hansson@arm.com { thread->initMemProxies(tc); } 1368799Sgblack@eecs.umich.edu 13713628SAndrea.Mondelli@ucf.edu virtual SETranslatingPortProxy &getMemProxy() override 1388706Sandreas.hansson@arm.com { return thread->getMemProxy(); } 1392817Sksewell@umich.edu 1402817Sksewell@umich.edu /** Returns this thread's status. */ 14113628SAndrea.Mondelli@ucf.edu virtual Status status() const override { return thread->status(); } 1422817Sksewell@umich.edu 1432817Sksewell@umich.edu /** Sets this thread's status. */ 14413628SAndrea.Mondelli@ucf.edu virtual void setStatus(Status new_status) override 1452817Sksewell@umich.edu { thread->setStatus(new_status); } 1462817Sksewell@umich.edu 14710407Smitch.hayenga@arm.com /** Set the status to Active. */ 14813628SAndrea.Mondelli@ucf.edu virtual void activate() override; 1492817Sksewell@umich.edu 1502817Sksewell@umich.edu /** Set the status to Suspended. */ 15113628SAndrea.Mondelli@ucf.edu virtual void suspend() override; 1522817Sksewell@umich.edu 1532817Sksewell@umich.edu /** Set the status to Halted. */ 15413628SAndrea.Mondelli@ucf.edu virtual void halt() override; 1552817Sksewell@umich.edu 1562817Sksewell@umich.edu /** Dumps the function profiling information. 1572817Sksewell@umich.edu * @todo: Implement. 1582817Sksewell@umich.edu */ 15913628SAndrea.Mondelli@ucf.edu virtual void dumpFuncProfile() override; 1608777Sgblack@eecs.umich.edu 1612817Sksewell@umich.edu /** Takes over execution of a thread from another CPU. */ 16213628SAndrea.Mondelli@ucf.edu virtual void takeOverFrom(ThreadContext *old_context) override; 1632817Sksewell@umich.edu 1642817Sksewell@umich.edu /** Registers statistics associated with this TC. */ 16513628SAndrea.Mondelli@ucf.edu virtual void regStats(const std::string &name) override; 1662817Sksewell@umich.edu 1672817Sksewell@umich.edu /** Reads the last tick that this thread was activated on. */ 16813628SAndrea.Mondelli@ucf.edu virtual Tick readLastActivate() override; 1692817Sksewell@umich.edu /** Reads the last tick that this thread was suspended on. */ 17013628SAndrea.Mondelli@ucf.edu virtual Tick readLastSuspend() override; 1712817Sksewell@umich.edu 1722817Sksewell@umich.edu /** Clears the function profiling information. */ 17313628SAndrea.Mondelli@ucf.edu virtual void profileClear() override; 1742817Sksewell@umich.edu /** Samples the function profiling information. */ 17513628SAndrea.Mondelli@ucf.edu virtual void profileSample() override; 1762817Sksewell@umich.edu 1772817Sksewell@umich.edu /** Copies the architectural registers from another TC into this TC. */ 17813628SAndrea.Mondelli@ucf.edu virtual void copyArchRegs(ThreadContext *tc) override; 1792817Sksewell@umich.edu 1802817Sksewell@umich.edu /** Resets all architectural registers to 0. */ 18113628SAndrea.Mondelli@ucf.edu virtual void clearArchRegs() override; 1822817Sksewell@umich.edu 1832817Sksewell@umich.edu /** Reads an integer register. */ 18413557Sgabeblack@google.com virtual RegVal 18513557Sgabeblack@google.com readReg(int reg_idx) 18613557Sgabeblack@google.com { 18712106SRekai.GonzalezAlberquilla@arm.com return readIntRegFlat(flattenRegId(RegId(IntRegClass, 18812106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 18912106SRekai.GonzalezAlberquilla@arm.com } 19013557Sgabeblack@google.com virtual RegVal 19113628SAndrea.Mondelli@ucf.edu readIntReg(int reg_idx) override 19213557Sgabeblack@google.com { 19312106SRekai.GonzalezAlberquilla@arm.com return readIntRegFlat(flattenRegId(RegId(IntRegClass, 19412106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 1959426SAndreas.Sandberg@ARM.com } 1962817Sksewell@umich.edu 19713557Sgabeblack@google.com virtual RegVal 19813628SAndrea.Mondelli@ucf.edu readFloatReg(int reg_idx) override 19913557Sgabeblack@google.com { 20013611Sgabeblack@google.com return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, 20113611Sgabeblack@google.com reg_idx)).index()); 2029426SAndreas.Sandberg@ARM.com } 2032817Sksewell@umich.edu 20413557Sgabeblack@google.com virtual const VecRegContainer & 20513628SAndrea.Mondelli@ucf.edu readVecReg(const RegId& id) const override 20613557Sgabeblack@google.com { 20712109SRekai.GonzalezAlberquilla@arm.com return readVecRegFlat(flattenRegId(id).index()); 20812109SRekai.GonzalezAlberquilla@arm.com } 20912109SRekai.GonzalezAlberquilla@arm.com 21012109SRekai.GonzalezAlberquilla@arm.com /** 21112109SRekai.GonzalezAlberquilla@arm.com * Read vector register operand for modification, hierarchical indexing. 21212109SRekai.GonzalezAlberquilla@arm.com */ 21313557Sgabeblack@google.com virtual VecRegContainer & 21413628SAndrea.Mondelli@ucf.edu getWritableVecReg(const RegId& id) override 21513557Sgabeblack@google.com { 21612109SRekai.GonzalezAlberquilla@arm.com return getWritableVecRegFlat(flattenRegId(id).index()); 21712109SRekai.GonzalezAlberquilla@arm.com } 21812109SRekai.GonzalezAlberquilla@arm.com 21912109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 22012109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 22112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 22212109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 22313628SAndrea.Mondelli@ucf.edu readVec8BitLaneReg(const RegId& id) const override 22412109SRekai.GonzalezAlberquilla@arm.com { 22512109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint8_t>(flattenRegId(id).index(), 22612109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 22712109SRekai.GonzalezAlberquilla@arm.com } 22812109SRekai.GonzalezAlberquilla@arm.com 22912109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 23012109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 23113628SAndrea.Mondelli@ucf.edu readVec16BitLaneReg(const RegId& id) const override 23212109SRekai.GonzalezAlberquilla@arm.com { 23312109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint16_t>(flattenRegId(id).index(), 23412109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 23512109SRekai.GonzalezAlberquilla@arm.com } 23612109SRekai.GonzalezAlberquilla@arm.com 23712109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 23812109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 23913628SAndrea.Mondelli@ucf.edu readVec32BitLaneReg(const RegId& id) const override 24012109SRekai.GonzalezAlberquilla@arm.com { 24112109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint32_t>(flattenRegId(id).index(), 24212109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 24312109SRekai.GonzalezAlberquilla@arm.com } 24412109SRekai.GonzalezAlberquilla@arm.com 24512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 24612109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 24713628SAndrea.Mondelli@ucf.edu readVec64BitLaneReg(const RegId& id) const override 24812109SRekai.GonzalezAlberquilla@arm.com { 24912109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint64_t>(flattenRegId(id).index(), 25012109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 25112109SRekai.GonzalezAlberquilla@arm.com } 25212109SRekai.GonzalezAlberquilla@arm.com 25312109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 25412109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 25513628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::Byte>& val) override 25612109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 25712109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 25813628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::TwoByte>& val) override 25912109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 26012109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 26113628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::FourByte>& val) override 26212109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 26312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 26413628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::EightByte>& val) override 26512109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 26612109SRekai.GonzalezAlberquilla@arm.com /** @} */ 26712109SRekai.GonzalezAlberquilla@arm.com 26813628SAndrea.Mondelli@ucf.edu virtual const VecElem& readVecElem(const RegId& reg) const override { 26912109SRekai.GonzalezAlberquilla@arm.com return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); 27012109SRekai.GonzalezAlberquilla@arm.com } 27112109SRekai.GonzalezAlberquilla@arm.com 27213628SAndrea.Mondelli@ucf.edu virtual const VecPredRegContainer& 27313628SAndrea.Mondelli@ucf.edu readVecPredReg(const RegId& id) const override { 27413610Sgiacomo.gabrielli@arm.com return readVecPredRegFlat(flattenRegId(id).index()); 27513610Sgiacomo.gabrielli@arm.com } 27613610Sgiacomo.gabrielli@arm.com 27713628SAndrea.Mondelli@ucf.edu virtual VecPredRegContainer& 27813628SAndrea.Mondelli@ucf.edu getWritableVecPredReg(const RegId& id) override { 27913610Sgiacomo.gabrielli@arm.com return getWritableVecPredRegFlat(flattenRegId(id).index()); 28013610Sgiacomo.gabrielli@arm.com } 28113610Sgiacomo.gabrielli@arm.com 28213622Sgabeblack@google.com virtual RegVal 28313628SAndrea.Mondelli@ucf.edu readCCReg(int reg_idx) override 28413622Sgabeblack@google.com { 28512106SRekai.GonzalezAlberquilla@arm.com return readCCRegFlat(flattenRegId(RegId(CCRegClass, 28612106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 2879920Syasuko.eckert@amd.com } 2889920Syasuko.eckert@amd.com 2892817Sksewell@umich.edu /** Sets an integer register to a value. */ 29013557Sgabeblack@google.com virtual void 29113628SAndrea.Mondelli@ucf.edu setIntReg(int reg_idx, RegVal val) override 29213557Sgabeblack@google.com { 29312106SRekai.GonzalezAlberquilla@arm.com setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); 2949426SAndreas.Sandberg@ARM.com } 2952817Sksewell@umich.edu 29613557Sgabeblack@google.com virtual void 29713628SAndrea.Mondelli@ucf.edu setFloatReg(int reg_idx, RegVal val) override 29813557Sgabeblack@google.com { 29913611Sgabeblack@google.com setFloatRegFlat(flattenRegId(RegId(FloatRegClass, 30013611Sgabeblack@google.com reg_idx)).index(), val); 3019426SAndreas.Sandberg@ARM.com } 3022817Sksewell@umich.edu 30313557Sgabeblack@google.com virtual void 30413628SAndrea.Mondelli@ucf.edu setVecReg(const RegId& reg, const VecRegContainer& val) override 30513557Sgabeblack@google.com { 30612109SRekai.GonzalezAlberquilla@arm.com setVecRegFlat(flattenRegId(reg).index(), val); 30712109SRekai.GonzalezAlberquilla@arm.com } 30812109SRekai.GonzalezAlberquilla@arm.com 30913557Sgabeblack@google.com virtual void 31013628SAndrea.Mondelli@ucf.edu setVecElem(const RegId& reg, const VecElem& val) override 31113557Sgabeblack@google.com { 31212109SRekai.GonzalezAlberquilla@arm.com setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 31312109SRekai.GonzalezAlberquilla@arm.com } 31412109SRekai.GonzalezAlberquilla@arm.com 31513557Sgabeblack@google.com virtual void 31613610Sgiacomo.gabrielli@arm.com setVecPredReg(const RegId& reg, 31713628SAndrea.Mondelli@ucf.edu const VecPredRegContainer& val) override 31813610Sgiacomo.gabrielli@arm.com { 31913610Sgiacomo.gabrielli@arm.com setVecPredRegFlat(flattenRegId(reg).index(), val); 32013610Sgiacomo.gabrielli@arm.com } 32113610Sgiacomo.gabrielli@arm.com 32213610Sgiacomo.gabrielli@arm.com virtual void 32313628SAndrea.Mondelli@ucf.edu setCCReg(int reg_idx, RegVal val) override 32413557Sgabeblack@google.com { 32512106SRekai.GonzalezAlberquilla@arm.com setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); 3269920Syasuko.eckert@amd.com } 3279920Syasuko.eckert@amd.com 3287720Sgblack@eecs.umich.edu /** Reads this thread's PC state. */ 32913628SAndrea.Mondelli@ucf.edu virtual TheISA::PCState pcState() override 3307720Sgblack@eecs.umich.edu { return cpu->pcState(thread->threadId()); } 3317720Sgblack@eecs.umich.edu 3327720Sgblack@eecs.umich.edu /** Sets this thread's PC state. */ 33313628SAndrea.Mondelli@ucf.edu virtual void pcState(const TheISA::PCState &val) override; 3347720Sgblack@eecs.umich.edu 33513628SAndrea.Mondelli@ucf.edu virtual void pcStateNoRecord(const TheISA::PCState &val) override; 3368733Sgeoffrey.blake@arm.com 3372817Sksewell@umich.edu /** Reads this thread's PC. */ 33813628SAndrea.Mondelli@ucf.edu virtual Addr instAddr() override 3397720Sgblack@eecs.umich.edu { return cpu->instAddr(thread->threadId()); } 3402817Sksewell@umich.edu 3412817Sksewell@umich.edu /** Reads this thread's next PC. */ 34213628SAndrea.Mondelli@ucf.edu virtual Addr nextInstAddr() override 3437720Sgblack@eecs.umich.edu { return cpu->nextInstAddr(thread->threadId()); } 3442817Sksewell@umich.edu 3457720Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 34613628SAndrea.Mondelli@ucf.edu virtual MicroPC microPC() override 3477720Sgblack@eecs.umich.edu { return cpu->microPC(thread->threadId()); } 3485259Sksewell@umich.edu 3492817Sksewell@umich.edu /** Reads a miscellaneous register. */ 35013628SAndrea.Mondelli@ucf.edu virtual RegVal readMiscRegNoEffect(int misc_reg) const override 3515715Shsul@eecs.umich.edu { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 3524172Ssaidi@eecs.umich.edu 3534172Ssaidi@eecs.umich.edu /** Reads a misc. register, including any side-effects the 3544172Ssaidi@eecs.umich.edu * read might have as defined by the architecture. */ 35513628SAndrea.Mondelli@ucf.edu virtual RegVal readMiscReg(int misc_reg) override 3565715Shsul@eecs.umich.edu { return cpu->readMiscReg(misc_reg, thread->threadId()); } 3572817Sksewell@umich.edu 3582817Sksewell@umich.edu /** Sets a misc. register. */ 35913628SAndrea.Mondelli@ucf.edu virtual void setMiscRegNoEffect(int misc_reg, RegVal val) override; 3602817Sksewell@umich.edu 3612817Sksewell@umich.edu /** Sets a misc. register, including any side-effects the 3622817Sksewell@umich.edu * write might have as defined by the architecture. */ 36313628SAndrea.Mondelli@ucf.edu virtual void setMiscReg(int misc_reg, RegVal val) override; 3642817Sksewell@umich.edu 36513628SAndrea.Mondelli@ucf.edu virtual RegId flattenRegId(const RegId& regId) const override; 3666313Sgblack@eecs.umich.edu 3672817Sksewell@umich.edu /** Returns the number of consecutive store conditional failures. */ 3682817Sksewell@umich.edu // @todo: Figure out where these store cond failures should go. 36913628SAndrea.Mondelli@ucf.edu virtual unsigned readStCondFailures() override 3702817Sksewell@umich.edu { return thread->storeCondFailures; } 3712817Sksewell@umich.edu 3722817Sksewell@umich.edu /** Sets the number of consecutive store conditional failures. */ 37313628SAndrea.Mondelli@ucf.edu virtual void setStCondFailures(unsigned sc_failures) override 3742817Sksewell@umich.edu { thread->storeCondFailures = sc_failures; } 3752817Sksewell@umich.edu 3762817Sksewell@umich.edu /** Executes a syscall in SE mode. */ 37713628SAndrea.Mondelli@ucf.edu virtual void syscall(int64_t callnum, Fault *fault) override 37811877Sbrandon.potter@amd.com { return cpu->syscall(callnum, thread->threadId(), fault); } 3792817Sksewell@umich.edu 3802817Sksewell@umich.edu /** Reads the funcExeInst counter. */ 38113628SAndrea.Mondelli@ucf.edu virtual Counter readFuncExeInst() override { return thread->funcExeInst; } 3828777Sgblack@eecs.umich.edu 3835595Sgblack@eecs.umich.edu /** Returns pointer to the quiesce event. */ 38413557Sgabeblack@google.com virtual EndQuiesceEvent * 38513628SAndrea.Mondelli@ucf.edu getQuiesceEvent() override 3865595Sgblack@eecs.umich.edu { 3875595Sgblack@eecs.umich.edu return this->thread->quiesceEvent; 3885595Sgblack@eecs.umich.edu } 3899382SAli.Saidi@ARM.com /** check if the cpu is currently in state update mode and squash if not. 3909382SAli.Saidi@ARM.com * This function will return true if a trap is pending or if a fault or 3919382SAli.Saidi@ARM.com * similar is currently writing to the thread context and doesn't want 3929382SAli.Saidi@ARM.com * reset all the state (see noSquashFromTC). 3939382SAli.Saidi@ARM.com */ 39413557Sgabeblack@google.com inline void 39513557Sgabeblack@google.com conditionalSquash() 3969382SAli.Saidi@ARM.com { 3979382SAli.Saidi@ARM.com if (!thread->trapPending && !thread->noSquashFromTC) 3989382SAli.Saidi@ARM.com cpu->squashFromTC(thread->threadId()); 3999382SAli.Saidi@ARM.com } 4005595Sgblack@eecs.umich.edu 40113628SAndrea.Mondelli@ucf.edu virtual RegVal readIntRegFlat(int idx) override; 40213628SAndrea.Mondelli@ucf.edu virtual void setIntRegFlat(int idx, RegVal val) override; 4039426SAndreas.Sandberg@ARM.com 40413628SAndrea.Mondelli@ucf.edu virtual RegVal readFloatRegFlat(int idx) override; 40513628SAndrea.Mondelli@ucf.edu virtual void setFloatRegFlat(int idx, RegVal val) override; 4069920Syasuko.eckert@amd.com 40713628SAndrea.Mondelli@ucf.edu virtual const VecRegContainer& readVecRegFlat(int idx) const override; 40812109SRekai.GonzalezAlberquilla@arm.com /** Read vector register operand for modification, flat indexing. */ 40913628SAndrea.Mondelli@ucf.edu virtual VecRegContainer& getWritableVecRegFlat(int idx) override; 41013628SAndrea.Mondelli@ucf.edu virtual void setVecRegFlat(int idx, const VecRegContainer& val) override; 41112109SRekai.GonzalezAlberquilla@arm.com 41212109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem> 41313557Sgabeblack@google.com VecLaneT<VecElem, true> 41413557Sgabeblack@google.com readVecLaneFlat(int idx, int lId) const 41512109SRekai.GonzalezAlberquilla@arm.com { 41612109SRekai.GonzalezAlberquilla@arm.com return cpu->template readArchVecLane<VecElem>(idx, lId, 41712109SRekai.GonzalezAlberquilla@arm.com thread->threadId()); 41812109SRekai.GonzalezAlberquilla@arm.com } 41912109SRekai.GonzalezAlberquilla@arm.com 42012109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 42112109SRekai.GonzalezAlberquilla@arm.com void setVecLaneFlat(int idx, int lId, const LD& val) 42212109SRekai.GonzalezAlberquilla@arm.com { 42312109SRekai.GonzalezAlberquilla@arm.com cpu->template setArchVecLane(idx, lId, thread->threadId(), val); 42412109SRekai.GonzalezAlberquilla@arm.com } 42512109SRekai.GonzalezAlberquilla@arm.com 42613628SAndrea.Mondelli@ucf.edu virtual const VecElem& readVecElemFlat( 42713628SAndrea.Mondelli@ucf.edu const RegIndex& idx, 42813628SAndrea.Mondelli@ucf.edu const ElemIndex& elemIndex) const override; 42913628SAndrea.Mondelli@ucf.edu virtual void setVecElemFlat( 43013628SAndrea.Mondelli@ucf.edu const RegIndex& idx, 43113628SAndrea.Mondelli@ucf.edu const ElemIndex& elemIdx, const VecElem& val) override; 43212109SRekai.GonzalezAlberquilla@arm.com 43313610Sgiacomo.gabrielli@arm.com virtual const VecPredRegContainer& readVecPredRegFlat(int idx) 43413610Sgiacomo.gabrielli@arm.com const override; 43513610Sgiacomo.gabrielli@arm.com virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override; 43613610Sgiacomo.gabrielli@arm.com virtual void setVecPredRegFlat(int idx, 43713610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) override; 43813610Sgiacomo.gabrielli@arm.com 43913628SAndrea.Mondelli@ucf.edu virtual RegVal readCCRegFlat(int idx) override; 44013628SAndrea.Mondelli@ucf.edu virtual void setCCRegFlat(int idx, RegVal val) override; 4412817Sksewell@umich.edu}; 4422817Sksewell@umich.edu 4432817Sksewell@umich.edu#endif 444