store_set.cc revision 2654:9559cfa91b9d
13536SN/A/*
27752SWilliam.Wang@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan
37752SWilliam.Wang@arm.com * All rights reserved.
47752SWilliam.Wang@arm.com *
57752SWilliam.Wang@arm.com * Redistribution and use in source and binary forms, with or without
67752SWilliam.Wang@arm.com * modification, are permitted provided that the following conditions are
77752SWilliam.Wang@arm.com * met: redistributions of source code must retain the above copyright
87752SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer;
97752SWilliam.Wang@arm.com * redistributions in binary form must reproduce the above copyright
107752SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer in the
117752SWilliam.Wang@arm.com * documentation and/or other materials provided with the distribution;
127752SWilliam.Wang@arm.com * neither the name of the copyright holders nor the names of its
137752SWilliam.Wang@arm.com * contributors may be used to endorse or promote products derived from
143536SN/A * this software without specific prior written permission.
153536SN/A *
163536SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
173536SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
183536SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
193536SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
203536SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
213536SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
223536SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
233536SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
243536SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
253536SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
263536SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
273536SN/A */
283536SN/A
293536SN/A#include "base/trace.hh"
303536SN/A#include "cpu/o3/store_set.hh"
313536SN/A
323536SN/AStoreSet::StoreSet(int _SSIT_size, int _LFST_size)
333536SN/A    : SSITSize(_SSIT_size), LFSTSize(_LFST_size)
343536SN/A{
353536SN/A    DPRINTF(StoreSet, "StoreSet: Creating store set object.\n");
363536SN/A    DPRINTF(StoreSet, "StoreSet: SSIT size: %i, LFST size: %i.\n",
373536SN/A            SSITSize, LFSTSize);
383536SN/A
393536SN/A    SSIT.resize(SSITSize);
403536SN/A
417752SWilliam.Wang@arm.com    validSSIT.resize(SSITSize);
423536SN/A
433536SN/A    for (int i = 0; i < SSITSize; ++i)
443536SN/A        validSSIT[i] = false;
458332Snate@binkert.org
468332Snate@binkert.org    LFST.resize(LFSTSize);
473536SN/A
483536SN/A    validLFST.resize(LFSTSize);
493536SN/A
503536SN/A    for (int i = 0; i < LFSTSize; ++i) {
513536SN/A        validLFST[i] = false;
523536SN/A        LFST[i] = 0;
533536SN/A    }
545543SN/A
555543SN/A    indexMask = SSITSize - 1;
563536SN/A
573536SN/A    offsetBits = 2;
583536SN/A}
593536SN/A
603536SN/AStoreSet::~StoreSet()
613536SN/A{
623536SN/A}
633536SN/A
643536SN/Avoid
653536SN/AStoreSet::init(int _SSIT_size, int _LFST_size)
663536SN/A{
675543SN/A    SSITSize = _SSIT_size;
685543SN/A    LFSTSize = _LFST_size;
693536SN/A
703536SN/A    DPRINTF(StoreSet, "StoreSet: Creating store set object.\n");
713536SN/A    DPRINTF(StoreSet, "StoreSet: SSIT size: %i, LFST size: %i.\n",
723536SN/A            SSITSize, LFSTSize);
733536SN/A
743536SN/A    SSIT.resize(SSITSize);
753536SN/A
763536SN/A    validSSIT.resize(SSITSize);
773536SN/A
783536SN/A    for (int i = 0; i < SSITSize; ++i)
793536SN/A        validSSIT[i] = false;
803536SN/A
813536SN/A    LFST.resize(LFSTSize);
823536SN/A
833536SN/A    validLFST.resize(LFSTSize);
843536SN/A
855543SN/A    for (int i = 0; i < LFSTSize; ++i) {
863536SN/A        validLFST[i] = false;
873536SN/A        LFST[i] = 0;
883536SN/A    }
893536SN/A
903536SN/A    indexMask = SSITSize - 1;
913536SN/A
923536SN/A    offsetBits = 2;
933536SN/A}
943536SN/A
953536SN/A
963536SN/Avoid
973536SN/AStoreSet::violation(Addr store_PC, Addr load_PC)
983536SN/A{
993536SN/A    int load_index = calcIndex(load_PC);
1003536SN/A    int store_index = calcIndex(store_PC);
1013536SN/A
1023536SN/A    assert(load_index < SSITSize && store_index < SSITSize);
1033536SN/A
1043536SN/A    bool valid_load_SSID = validSSIT[load_index];
1055543SN/A    bool valid_store_SSID = validSSIT[store_index];
1065543SN/A
1073536SN/A    if (!valid_load_SSID && !valid_store_SSID) {
1083536SN/A        // Calculate a new SSID here.
1093536SN/A        SSID new_set = calcSSID(load_PC);
1103536SN/A
1113536SN/A        validSSIT[load_index] = true;
1123536SN/A
1133536SN/A        SSIT[load_index] = new_set;
1143536SN/A
1153536SN/A        validSSIT[store_index] = true;
1163536SN/A
1173536SN/A        SSIT[store_index] = new_set;
1183536SN/A
1193536SN/A        assert(new_set < LFSTSize);
1203536SN/A
1213536SN/A        DPRINTF(StoreSet, "StoreSet: Neither load nor store had a valid "
1223536SN/A                "storeset, creating a new one: %i for load %#x, store %#x\n",
1233536SN/A                new_set, load_PC, store_PC);
1243536SN/A    } else if (valid_load_SSID && !valid_store_SSID) {
1253536SN/A        SSID load_SSID = SSIT[load_index];
1263536SN/A
1273536SN/A        validSSIT[store_index] = true;
1283536SN/A
1293536SN/A        SSIT[store_index] = load_SSID;
1303536SN/A
1313536SN/A        assert(load_SSID < LFSTSize);
1323536SN/A
1335569SN/A        DPRINTF(StoreSet, "StoreSet: Load had a valid store set.  Adding "
1343536SN/A                "store to that set: %i for load %#x, store %#x\n",
1353536SN/A                load_SSID, load_PC, store_PC);
1363536SN/A    } else if (!valid_load_SSID && valid_store_SSID) {
1378229Snate@binkert.org        SSID store_SSID = SSIT[store_index];
1388229Snate@binkert.org
1398229Snate@binkert.org        validSSIT[load_index] = true;
1407752SWilliam.Wang@arm.com
1417752SWilliam.Wang@arm.com        SSIT[load_index] = store_SSID;
1423536SN/A
1433536SN/A        DPRINTF(StoreSet, "StoreSet: Store had a valid store set: %i for "
1443536SN/A                "load %#x, store %#x\n",
1453536SN/A                store_SSID, load_PC, store_PC);
1468541Sgblack@eecs.umich.edu    } else {
1478229Snate@binkert.org        SSID load_SSID = SSIT[load_index];
1483536SN/A        SSID store_SSID = SSIT[store_index];
1497752SWilliam.Wang@arm.com
1508232Snate@binkert.org        assert(load_SSID < LFSTSize && store_SSID < LFSTSize);
1518232Snate@binkert.org
1528229Snate@binkert.org        // The store set with the lower number wins
1533536SN/A        if (store_SSID > load_SSID) {
1543536SN/A            SSIT[store_index] = load_SSID;
1558782Sgblack@eecs.umich.edu
1563536SN/A            DPRINTF(StoreSet, "StoreSet: Load had smaller store set: %i; "
1573536SN/A                    "for load %#x, store %#x\n",
1583536SN/A                    load_SSID, load_PC, store_PC);
1597752SWilliam.Wang@arm.com        } else {
1603536SN/A            SSIT[load_index] = store_SSID;
1615569SN/A
1627752SWilliam.Wang@arm.com            DPRINTF(StoreSet, "StoreSet: Store had smaller store set: %i; "
1633536SN/A                    "for load %#x, store %#x\n",
1643536SN/A                    store_SSID, load_PC, store_PC);
1653536SN/A        }
1665569SN/A    }
1675569SN/A}
1685569SN/A
1693536SN/Avoid
1703536SN/AStoreSet::insertLoad(Addr load_PC, InstSeqNum load_seq_num)
1713536SN/A{
1728782Sgblack@eecs.umich.edu    // Does nothing.
1738782Sgblack@eecs.umich.edu    return;
1748782Sgblack@eecs.umich.edu}
1758782Sgblack@eecs.umich.edu
1763536SN/Avoid
1778782Sgblack@eecs.umich.eduStoreSet::insertStore(Addr store_PC, InstSeqNum store_seq_num,
1788782Sgblack@eecs.umich.edu                      unsigned tid)
1798782Sgblack@eecs.umich.edu{
1808782Sgblack@eecs.umich.edu    int index = calcIndex(store_PC);
1818782Sgblack@eecs.umich.edu
1828782Sgblack@eecs.umich.edu    int store_SSID;
1838782Sgblack@eecs.umich.edu
1848782Sgblack@eecs.umich.edu    assert(index < SSITSize);
1858782Sgblack@eecs.umich.edu
1868782Sgblack@eecs.umich.edu    if (!validSSIT[index]) {
1878782Sgblack@eecs.umich.edu        // Do nothing if there's no valid entry.
1888782Sgblack@eecs.umich.edu        return;
1898782Sgblack@eecs.umich.edu    } else {
1908782Sgblack@eecs.umich.edu        store_SSID = SSIT[index];
1913536SN/A
1928782Sgblack@eecs.umich.edu        assert(store_SSID < LFSTSize);
1938782Sgblack@eecs.umich.edu
1943536SN/A        // Update the last store that was fetched with the current one.
1953536SN/A        LFST[store_SSID] = store_seq_num;
1965569SN/A
1975569SN/A        validLFST[store_SSID] = 1;
1985569SN/A
1995569SN/A        storeList[store_seq_num] = store_SSID;
2003536SN/A
2013536SN/A        DPRINTF(StoreSet, "Store %#x updated the LFST, SSID: %i\n",
2023536SN/A                store_PC, store_SSID);
2037752SWilliam.Wang@arm.com    }
2047752SWilliam.Wang@arm.com}
2053579SN/A
2063536SN/AInstSeqNum
2077752SWilliam.Wang@arm.comStoreSet::checkInst(Addr PC)
2087752SWilliam.Wang@arm.com{
2097752SWilliam.Wang@arm.com    int index = calcIndex(PC);
2107752SWilliam.Wang@arm.com
2117752SWilliam.Wang@arm.com    int inst_SSID;
2127752SWilliam.Wang@arm.com
2137752SWilliam.Wang@arm.com    assert(index < SSITSize);
2147752SWilliam.Wang@arm.com
2157752SWilliam.Wang@arm.com    if (!validSSIT[index]) {
2167752SWilliam.Wang@arm.com        DPRINTF(StoreSet, "Inst %#x with index %i had no SSID\n",
2177752SWilliam.Wang@arm.com                PC, index);
2187752SWilliam.Wang@arm.com
2197752SWilliam.Wang@arm.com        // Return 0 if there's no valid entry.
2207752SWilliam.Wang@arm.com        return 0;
2217752SWilliam.Wang@arm.com    } else {
2227752SWilliam.Wang@arm.com        inst_SSID = SSIT[index];
2237752SWilliam.Wang@arm.com
2247752SWilliam.Wang@arm.com        assert(inst_SSID < LFSTSize);
2257752SWilliam.Wang@arm.com
2263536SN/A        if (!validLFST[inst_SSID]) {
2277752SWilliam.Wang@arm.com
2287752SWilliam.Wang@arm.com            DPRINTF(StoreSet, "Inst %#x with index %i and SSID %i had no "
2297752SWilliam.Wang@arm.com                    "dependency\n", PC, index, inst_SSID);
2307752SWilliam.Wang@arm.com
2317752SWilliam.Wang@arm.com            return 0;
2327752SWilliam.Wang@arm.com        } else {
2337752SWilliam.Wang@arm.com            DPRINTF(StoreSet, "Inst %#x with index %i and SSID %i had LFST "
2347752SWilliam.Wang@arm.com                    "inum of %i\n", PC, index, inst_SSID, LFST[inst_SSID]);
2357752SWilliam.Wang@arm.com
2367752SWilliam.Wang@arm.com            return LFST[inst_SSID];
2377752SWilliam.Wang@arm.com        }
2387752SWilliam.Wang@arm.com    }
2397752SWilliam.Wang@arm.com}
2403536SN/A
2413536SN/Avoid
2427752SWilliam.Wang@arm.comStoreSet::issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
2437752SWilliam.Wang@arm.com{
2447752SWilliam.Wang@arm.com    // This only is updated upon a store being issued.
2457752SWilliam.Wang@arm.com    if (!is_store) {
2463536SN/A        return;
2473536SN/A    }
2485569SN/A
2495569SN/A    int index = calcIndex(issued_PC);
2505569SN/A
2515569SN/A    int store_SSID;
2523536SN/A
2533536SN/A    assert(index < SSITSize);
2543536SN/A
2557752SWilliam.Wang@arm.com    SeqNumMapIt store_list_it = storeList.find(issued_seq_num);
2567752SWilliam.Wang@arm.com
2577752SWilliam.Wang@arm.com    if (store_list_it != storeList.end()) {
2587752SWilliam.Wang@arm.com        storeList.erase(store_list_it);
2597752SWilliam.Wang@arm.com    }
2607752SWilliam.Wang@arm.com
2617752SWilliam.Wang@arm.com    // Make sure the SSIT still has a valid entry for the issued store.
2627752SWilliam.Wang@arm.com    if (!validSSIT[index]) {
2637752SWilliam.Wang@arm.com        return;
2647752SWilliam.Wang@arm.com    }
2657752SWilliam.Wang@arm.com
2667752SWilliam.Wang@arm.com    store_SSID = SSIT[index];
2677752SWilliam.Wang@arm.com
2687752SWilliam.Wang@arm.com    assert(store_SSID < LFSTSize);
2697752SWilliam.Wang@arm.com
2707752SWilliam.Wang@arm.com    // If the last fetched store in the store set refers to the store that
2717752SWilliam.Wang@arm.com    // was just issued, then invalidate the entry.
2727752SWilliam.Wang@arm.com    if (validLFST[store_SSID] && LFST[store_SSID] == issued_seq_num) {
2737752SWilliam.Wang@arm.com        DPRINTF(StoreSet, "StoreSet: store invalidated itself in LFST.\n");
2747752SWilliam.Wang@arm.com        validLFST[store_SSID] = false;
2757752SWilliam.Wang@arm.com    }
2767752SWilliam.Wang@arm.com}
2777752SWilliam.Wang@arm.com
2787752SWilliam.Wang@arm.comvoid
2797752SWilliam.Wang@arm.comStoreSet::squash(InstSeqNum squashed_num, unsigned tid)
2807752SWilliam.Wang@arm.com{
2817752SWilliam.Wang@arm.com    DPRINTF(StoreSet, "StoreSet: Squashing until inum %i\n",
2827752SWilliam.Wang@arm.com            squashed_num);
2837752SWilliam.Wang@arm.com
2847752SWilliam.Wang@arm.com    int idx;
2857752SWilliam.Wang@arm.com    SeqNumMapIt store_list_it = storeList.begin();
2867752SWilliam.Wang@arm.com
2877752SWilliam.Wang@arm.com    //@todo:Fix to only delete from correct thread
2887752SWilliam.Wang@arm.com    while (!storeList.empty()) {
2897752SWilliam.Wang@arm.com        idx = (*store_list_it).second;
2907752SWilliam.Wang@arm.com
2917752SWilliam.Wang@arm.com        if ((*store_list_it).first <= squashed_num) {
2927752SWilliam.Wang@arm.com            break;
2933536SN/A        }
2943536SN/A
2957752SWilliam.Wang@arm.com        bool younger = LFST[idx] > squashed_num;
2967752SWilliam.Wang@arm.com
2973536SN/A        if (validLFST[idx] && younger) {
2983536SN/A            DPRINTF(StoreSet, "Squashed [sn:%lli]\n", LFST[idx]);
2993536SN/A            validLFST[idx] = false;
3003536SN/A
3013536SN/A            storeList.erase(store_list_it++);
3023536SN/A        } else if (!validLFST[idx] && younger) {
3033550SN/A            storeList.erase(store_list_it++);
3043536SN/A        }
3053550SN/A    }
3063536SN/A}
3073536SN/A
3083550SN/Avoid
3093536SN/AStoreSet::clear()
3103536SN/A{
3113536SN/A    for (int i = 0; i < SSITSize; ++i) {
3123536SN/A        validSSIT[i] = false;
3133536SN/A    }
3143536SN/A
3157720SN/A    for (int i = 0; i < LFSTSize; ++i) {
3167720SN/A        validLFST[i] = false;
3173536SN/A    }
3183536SN/A
3193536SN/A    storeList.clear();
3203536SN/A}
3217720SN/A