rename_map.hh revision 1763
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com * 1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com */ 2810259SAndrew.Bardsley@arm.com 2910259SAndrew.Bardsley@arm.com// Todo: Create destructor. 3010259SAndrew.Bardsley@arm.com// Have it so that there's a more meaningful name given to the variable 3110259SAndrew.Bardsley@arm.com// that marks the beginning of the FP registers. 3210259SAndrew.Bardsley@arm.com 3310259SAndrew.Bardsley@arm.com#ifndef __CPU_O3_CPU_RENAME_MAP_HH__ 3410259SAndrew.Bardsley@arm.com#define __CPU_O3_CPU_RENAME_MAP_HH__ 3510259SAndrew.Bardsley@arm.com 3610259SAndrew.Bardsley@arm.com#include <iostream> 3710259SAndrew.Bardsley@arm.com#include <utility> 3810259SAndrew.Bardsley@arm.com#include <vector> 3910259SAndrew.Bardsley@arm.com 4010259SAndrew.Bardsley@arm.com#include "cpu/o3/free_list.hh" 4110259SAndrew.Bardsley@arm.com 4210259SAndrew.Bardsley@arm.comclass SimpleRenameMap 4310259SAndrew.Bardsley@arm.com{ 4410259SAndrew.Bardsley@arm.com public: 4510259SAndrew.Bardsley@arm.com /** 4610259SAndrew.Bardsley@arm.com * Pair of a logical register and a physical register. Tells the 4710259SAndrew.Bardsley@arm.com * previous mapping of a logical register to a physical register. 4810259SAndrew.Bardsley@arm.com * Used to roll back the rename map to a previous state. 4910259SAndrew.Bardsley@arm.com */ 5010259SAndrew.Bardsley@arm.com typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 5110259SAndrew.Bardsley@arm.com 5210259SAndrew.Bardsley@arm.com /** 5310259SAndrew.Bardsley@arm.com * Pair of a physical register and a physical register. Used to 5410259SAndrew.Bardsley@arm.com * return the physical register that a logical register has been 5510259SAndrew.Bardsley@arm.com * renamed to, and the previous physical register that the same 5610259SAndrew.Bardsley@arm.com * logical register was previously mapped to. 5710259SAndrew.Bardsley@arm.com */ 5810259SAndrew.Bardsley@arm.com typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo; 5910259SAndrew.Bardsley@arm.com 6010259SAndrew.Bardsley@arm.com public: 6110259SAndrew.Bardsley@arm.com //Constructor 6210259SAndrew.Bardsley@arm.com SimpleRenameMap(unsigned _numLogicalIntRegs, 6310259SAndrew.Bardsley@arm.com unsigned _numPhysicalIntRegs, 6410259SAndrew.Bardsley@arm.com unsigned _numLogicalFloatRegs, 6510259SAndrew.Bardsley@arm.com unsigned _numPhysicalFloatRegs, 6610259SAndrew.Bardsley@arm.com unsigned _numMiscRegs, 6710259SAndrew.Bardsley@arm.com RegIndex _intZeroReg, 6810259SAndrew.Bardsley@arm.com RegIndex _floatZeroReg); 6910259SAndrew.Bardsley@arm.com 7010259SAndrew.Bardsley@arm.com /** Destructor. */ 7110259SAndrew.Bardsley@arm.com ~SimpleRenameMap(); 7210259SAndrew.Bardsley@arm.com 7310259SAndrew.Bardsley@arm.com void setFreeList(SimpleFreeList *fl_ptr); 7410259SAndrew.Bardsley@arm.com 7510259SAndrew.Bardsley@arm.com //Tell rename map to get a free physical register for a given 7610259SAndrew.Bardsley@arm.com //architected register. Not sure it should have a return value, 7710259SAndrew.Bardsley@arm.com //but perhaps it should have some sort of fault in case there are 7810259SAndrew.Bardsley@arm.com //no free registers. 7910259SAndrew.Bardsley@arm.com RenameInfo rename(RegIndex arch_reg); 8010259SAndrew.Bardsley@arm.com 8110259SAndrew.Bardsley@arm.com PhysRegIndex lookup(RegIndex phys_reg); 8210259SAndrew.Bardsley@arm.com 8310259SAndrew.Bardsley@arm.com bool isReady(PhysRegIndex arch_reg); 8410259SAndrew.Bardsley@arm.com 8510259SAndrew.Bardsley@arm.com /** 8610259SAndrew.Bardsley@arm.com * Marks the given register as ready, meaning that its value has been 8710259SAndrew.Bardsley@arm.com * calculated and written to the register file. 8810259SAndrew.Bardsley@arm.com * @param ready_reg The index of the physical register that is now ready. 8910259SAndrew.Bardsley@arm.com */ 9010259SAndrew.Bardsley@arm.com void markAsReady(PhysRegIndex ready_reg); 9110259SAndrew.Bardsley@arm.com 9210259SAndrew.Bardsley@arm.com void setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg); 9310259SAndrew.Bardsley@arm.com 9410259SAndrew.Bardsley@arm.com void squash(std::vector<RegIndex> freed_regs, 9510259SAndrew.Bardsley@arm.com std::vector<UnmapInfo> unmaps); 9610259SAndrew.Bardsley@arm.com 9710259SAndrew.Bardsley@arm.com int numFreeEntries(); 9810259SAndrew.Bardsley@arm.com 9910259SAndrew.Bardsley@arm.com private: 10010259SAndrew.Bardsley@arm.com /** Number of logical integer registers. */ 10110259SAndrew.Bardsley@arm.com int numLogicalIntRegs; 10210259SAndrew.Bardsley@arm.com 10310259SAndrew.Bardsley@arm.com /** Number of physical integer registers. */ 10410259SAndrew.Bardsley@arm.com int numPhysicalIntRegs; 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.com /** Number of logical floating point registers. */ 10710259SAndrew.Bardsley@arm.com int numLogicalFloatRegs; 10810259SAndrew.Bardsley@arm.com 10910259SAndrew.Bardsley@arm.com /** Number of physical floating point registers. */ 11010259SAndrew.Bardsley@arm.com int numPhysicalFloatRegs; 11110259SAndrew.Bardsley@arm.com 11210259SAndrew.Bardsley@arm.com /** Number of miscellaneous registers. */ 11310259SAndrew.Bardsley@arm.com int numMiscRegs; 11410259SAndrew.Bardsley@arm.com 11511567Smitch.hayenga@arm.com /** Number of logical integer + float registers. */ 11610259SAndrew.Bardsley@arm.com int numLogicalRegs; 11710259SAndrew.Bardsley@arm.com 11810913Sandreas.sandberg@arm.com /** Number of physical integer + float registers. */ 11910259SAndrew.Bardsley@arm.com int numPhysicalRegs; 12010259SAndrew.Bardsley@arm.com 12110259SAndrew.Bardsley@arm.com /** The integer zero register. This implementation assumes it is always 12210259SAndrew.Bardsley@arm.com * zero and never can be anything else. 12310259SAndrew.Bardsley@arm.com */ 12410259SAndrew.Bardsley@arm.com RegIndex intZeroReg; 12510259SAndrew.Bardsley@arm.com 12610259SAndrew.Bardsley@arm.com /** The floating point zero register. This implementation assumes it is 12711169Sandreas.hansson@arm.com * always zero and never can be anything else. 12810259SAndrew.Bardsley@arm.com */ 12911168Sandreas.hansson@arm.com RegIndex floatZeroReg; 13010464SAndreas.Sandberg@ARM.com 13110464SAndreas.Sandberg@ARM.com class RenameEntry 13210464SAndreas.Sandberg@ARM.com { 13310464SAndreas.Sandberg@ARM.com public: 13410259SAndrew.Bardsley@arm.com PhysRegIndex physical_reg; 13510259SAndrew.Bardsley@arm.com bool valid; 13610259SAndrew.Bardsley@arm.com 13710259SAndrew.Bardsley@arm.com RenameEntry() 13810259SAndrew.Bardsley@arm.com : physical_reg(0), valid(false) 13910259SAndrew.Bardsley@arm.com { } 14010259SAndrew.Bardsley@arm.com }; 14110259SAndrew.Bardsley@arm.com 14210259SAndrew.Bardsley@arm.com /** Integer rename map. */ 14310259SAndrew.Bardsley@arm.com RenameEntry *intRenameMap; 14410259SAndrew.Bardsley@arm.com 14510259SAndrew.Bardsley@arm.com /** Floating point rename map. */ 14610259SAndrew.Bardsley@arm.com RenameEntry *floatRenameMap; 14710259SAndrew.Bardsley@arm.com 14810259SAndrew.Bardsley@arm.com /** Free list interface. */ 14910259SAndrew.Bardsley@arm.com SimpleFreeList *freeList; 15010259SAndrew.Bardsley@arm.com 151 // Might want to make all these scoreboards into one large scoreboard. 152 153 /** Scoreboard of physical integer registers, saying whether or not they 154 * are ready. 155 */ 156 std::vector<bool> intScoreboard; 157 158 /** Scoreboard of physical floating registers, saying whether or not they 159 * are ready. 160 */ 161 std::vector<bool> floatScoreboard; 162 163 /** Scoreboard of miscellaneous registers, saying whether or not they 164 * are ready. 165 */ 166 std::vector<bool> miscScoreboard; 167}; 168 169#endif //__CPU_O3_CPU_RENAME_MAP_HH__ 170