rename_map.hh revision 1763
110037SARM gem5 Developers/*
210037SARM gem5 Developers * Copyright (c) 2004-2005 The Regents of The University of Michigan
310037SARM gem5 Developers * All rights reserved.
410037SARM gem5 Developers *
510037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without
610037SARM gem5 Developers * modification, are permitted provided that the following conditions are
710037SARM gem5 Developers * met: redistributions of source code must retain the above copyright
810037SARM gem5 Developers * notice, this list of conditions and the following disclaimer;
910037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright
1010037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the
1110037SARM gem5 Developers * documentation and/or other materials provided with the distribution;
1210037SARM gem5 Developers * neither the name of the copyright holders nor the names of its
1310037SARM gem5 Developers * contributors may be used to endorse or promote products derived from
1410037SARM gem5 Developers * this software without specific prior written permission.
1510037SARM gem5 Developers *
1610037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1710037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1810037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1910037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2010037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2110037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2210037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2310037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2410037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2510037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2610037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2710037SARM gem5 Developers */
2810037SARM gem5 Developers
2910037SARM gem5 Developers// Todo:  Create destructor.
3010037SARM gem5 Developers// Have it so that there's a more meaningful name given to the variable
3110037SARM gem5 Developers// that marks the beginning of the FP registers.
3210037SARM gem5 Developers
3310037SARM gem5 Developers#ifndef __CPU_O3_CPU_RENAME_MAP_HH__
3410037SARM gem5 Developers#define __CPU_O3_CPU_RENAME_MAP_HH__
3510037SARM gem5 Developers
3610037SARM gem5 Developers#include <iostream>
3710037SARM gem5 Developers#include <utility>
3810037SARM gem5 Developers#include <vector>
3910037SARM gem5 Developers
4010037SARM gem5 Developers#include "cpu/o3/free_list.hh"
4110037SARM gem5 Developers
4210037SARM gem5 Developersclass SimpleRenameMap
4310037SARM gem5 Developers{
4410037SARM gem5 Developers  public:
4510037SARM gem5 Developers    /**
4610037SARM gem5 Developers     * Pair of a logical register and a physical register.  Tells the
4710037SARM gem5 Developers     * previous mapping of a logical register to a physical register.
4810037SARM gem5 Developers     * Used to roll back the rename map to a previous state.
4910037SARM gem5 Developers     */
5010037SARM gem5 Developers    typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
5110037SARM gem5 Developers
5210037SARM gem5 Developers    /**
5310037SARM gem5 Developers     * Pair of a physical register and a physical register.  Used to
5410037SARM gem5 Developers     * return the physical register that a logical register has been
5510905Sandreas.sandberg@arm.com     * renamed to, and the previous physical register that the same
5610905Sandreas.sandberg@arm.com     * logical register was previously mapped to.
5710905Sandreas.sandberg@arm.com     */
5810037SARM gem5 Developers    typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo;
5910037SARM gem5 Developers
6010037SARM gem5 Developers  public:
6110037SARM gem5 Developers    //Constructor
6210037SARM gem5 Developers    SimpleRenameMap(unsigned _numLogicalIntRegs,
6310037SARM gem5 Developers                    unsigned _numPhysicalIntRegs,
6410037SARM gem5 Developers                    unsigned _numLogicalFloatRegs,
6510037SARM gem5 Developers                    unsigned _numPhysicalFloatRegs,
6610037SARM gem5 Developers                    unsigned _numMiscRegs,
6710037SARM gem5 Developers                    RegIndex _intZeroReg,
6810037SARM gem5 Developers                    RegIndex _floatZeroReg);
6910037SARM gem5 Developers
7010037SARM gem5 Developers    /** Destructor. */
7110037SARM gem5 Developers    ~SimpleRenameMap();
7210037SARM gem5 Developers
7310037SARM gem5 Developers    void setFreeList(SimpleFreeList *fl_ptr);
7410037SARM gem5 Developers
7510037SARM gem5 Developers    //Tell rename map to get a free physical register for a given
7610037SARM gem5 Developers    //architected register.  Not sure it should have a return value,
7710037SARM gem5 Developers    //but perhaps it should have some sort of fault in case there are
7810037SARM gem5 Developers    //no free registers.
7910037SARM gem5 Developers    RenameInfo rename(RegIndex arch_reg);
8010037SARM gem5 Developers
8110037SARM gem5 Developers    PhysRegIndex lookup(RegIndex phys_reg);
8210037SARM gem5 Developers
8310037SARM gem5 Developers    bool isReady(PhysRegIndex arch_reg);
8410037SARM gem5 Developers
8510037SARM gem5 Developers    /**
8610037SARM gem5 Developers     * Marks the given register as ready, meaning that its value has been
8710037SARM gem5 Developers     * calculated and written to the register file.
8810037SARM gem5 Developers     * @param ready_reg The index of the physical register that is now ready.
8910037SARM gem5 Developers     */
9010037SARM gem5 Developers    void markAsReady(PhysRegIndex ready_reg);
9110037SARM gem5 Developers
9210037SARM gem5 Developers    void setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg);
9310037SARM gem5 Developers
9410037SARM gem5 Developers    void squash(std::vector<RegIndex> freed_regs,
9510037SARM gem5 Developers                std::vector<UnmapInfo> unmaps);
9610037SARM gem5 Developers
9710037SARM gem5 Developers    int numFreeEntries();
9810037SARM gem5 Developers
9910037SARM gem5 Developers  private:
10010037SARM gem5 Developers    /** Number of logical integer registers. */
10110037SARM gem5 Developers    int numLogicalIntRegs;
10210037SARM gem5 Developers
10310037SARM gem5 Developers    /** Number of physical integer registers. */
10410037SARM gem5 Developers    int numPhysicalIntRegs;
10510037SARM gem5 Developers
10610037SARM gem5 Developers    /** Number of logical floating point registers. */
10712132Sspwilson2@wisc.edu    int numLogicalFloatRegs;
10812132Sspwilson2@wisc.edu
10910037SARM gem5 Developers    /** Number of physical floating point registers. */
11012132Sspwilson2@wisc.edu    int numPhysicalFloatRegs;
11110037SARM gem5 Developers
11210037SARM gem5 Developers    /** Number of miscellaneous registers. */
11310037SARM gem5 Developers    int numMiscRegs;
11410037SARM gem5 Developers
11510037SARM gem5 Developers    /** Number of logical integer + float registers. */
11610037SARM gem5 Developers    int numLogicalRegs;
11710037SARM gem5 Developers
11810037SARM gem5 Developers    /** Number of physical integer + float registers. */
11910037SARM gem5 Developers    int numPhysicalRegs;
12010037SARM gem5 Developers
12110037SARM gem5 Developers    /** The integer zero register.  This implementation assumes it is always
12210037SARM gem5 Developers     *  zero and never can be anything else.
12310037SARM gem5 Developers     */
12410037SARM gem5 Developers    RegIndex intZeroReg;
12510037SARM gem5 Developers
12610037SARM gem5 Developers    /** The floating point zero register.  This implementation assumes it is
12710037SARM gem5 Developers     *  always zero and never can be anything else.
12810037SARM gem5 Developers     */
12910037SARM gem5 Developers    RegIndex floatZeroReg;
13010037SARM gem5 Developers
13110037SARM gem5 Developers    class RenameEntry
13210037SARM gem5 Developers    {
13310037SARM gem5 Developers      public:
13410037SARM gem5 Developers        PhysRegIndex physical_reg;
13510037SARM gem5 Developers        bool valid;
13610037SARM gem5 Developers
13710037SARM gem5 Developers        RenameEntry()
13810037SARM gem5 Developers            : physical_reg(0), valid(false)
13910037SARM gem5 Developers        { }
14010037SARM gem5 Developers    };
14110037SARM gem5 Developers
14210037SARM gem5 Developers    /** Integer rename map. */
14310037SARM gem5 Developers    RenameEntry *intRenameMap;
14410037SARM gem5 Developers
14510037SARM gem5 Developers    /** Floating point rename map. */
14610037SARM gem5 Developers    RenameEntry *floatRenameMap;
14710037SARM gem5 Developers
14810037SARM gem5 Developers    /** Free list interface. */
14910037SARM gem5 Developers    SimpleFreeList *freeList;
15010037SARM gem5 Developers
15110037SARM gem5 Developers    // Might want to make all these scoreboards into one large scoreboard.
15210037SARM gem5 Developers
15310037SARM gem5 Developers    /** Scoreboard of physical integer registers, saying whether or not they
15410037SARM gem5 Developers     *  are ready.
15510037SARM gem5 Developers     */
15610905Sandreas.sandberg@arm.com    std::vector<bool> intScoreboard;
15710905Sandreas.sandberg@arm.com
15810905Sandreas.sandberg@arm.com    /** Scoreboard of physical floating registers, saying whether or not they
15910905Sandreas.sandberg@arm.com     *  are ready.
16010905Sandreas.sandberg@arm.com     */
16110905Sandreas.sandberg@arm.com    std::vector<bool> floatScoreboard;
16210905Sandreas.sandberg@arm.com
16310905Sandreas.sandberg@arm.com    /** Scoreboard of miscellaneous registers, saying whether or not they
16410905Sandreas.sandberg@arm.com     *  are ready.
16510905Sandreas.sandberg@arm.com     */
16610905Sandreas.sandberg@arm.com    std::vector<bool> miscScoreboard;
16710037SARM gem5 Developers};
16810037SARM gem5 Developers
16910037SARM gem5 Developers#endif //__CPU_O3_CPU_RENAME_MAP_HH__
17010037SARM gem5 Developers