rename_map.cc revision 10934:5af8f40d8f2c 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 */
31
32#include <vector>
33
34#include "cpu/o3/rename_map.hh"
35#include "debug/Rename.hh"
36
37using namespace std;
38
39/**** SimpleRenameMap methods ****/
40
41SimpleRenameMap::SimpleRenameMap()
42    : freeList(NULL), zeroReg(0)
43{
44}
45
46
47void
48SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
49                      RegIndex _zeroReg)
50{
51    assert(freeList == NULL);
52    assert(map.empty());
53
54    map.resize(size);
55    freeList = _freeList;
56    zeroReg = _zeroReg;
57}
58
59SimpleRenameMap::RenameInfo
60SimpleRenameMap::rename(RegIndex arch_reg)
61{
62    PhysRegIndex renamed_reg;
63
64    // Record the current physical register that is renamed to the
65    // requested architected register.
66    PhysRegIndex prev_reg = map[arch_reg];
67
68    // If it's not referencing the zero register, then rename the
69    // register.
70    if (arch_reg != zeroReg) {
71        renamed_reg = freeList->getReg();
72
73        map[arch_reg] = renamed_reg;
74    } else {
75        // Otherwise return the zero register so nothing bad happens.
76        assert(prev_reg == zeroReg);
77        renamed_reg = zeroReg;
78    }
79
80    DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n",
81            arch_reg, renamed_reg, prev_reg);
82
83    return RenameInfo(renamed_reg, prev_reg);
84}
85
86
87/**** UnifiedRenameMap methods ****/
88
89void
90UnifiedRenameMap::init(PhysRegFile *_regFile,
91                       RegIndex _intZeroReg,
92                       RegIndex _floatZeroReg,
93                       UnifiedFreeList *freeList)
94{
95    regFile = _regFile;
96
97    intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
98
99    floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
100
101    ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
102
103    vectorMap.init(TheISA::NumVectorRegs, &(freeList->vectorList),
104                   (RegIndex)-1);
105}
106
107
108UnifiedRenameMap::RenameInfo
109UnifiedRenameMap::rename(RegIndex arch_reg)
110{
111    RegIndex rel_arch_reg;
112
113    switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
114      case IntRegClass:
115        return renameInt(rel_arch_reg);
116
117      case FloatRegClass:
118        return renameFloat(rel_arch_reg);
119
120      case CCRegClass:
121        return renameCC(rel_arch_reg);
122
123      case VectorRegClass:
124        return renameVector(rel_arch_reg);
125
126      case MiscRegClass:
127        return renameMisc(rel_arch_reg);
128
129      default:
130        panic("rename rename(): unknown reg class %s\n",
131              RegClassStrings[regIdxToClass(arch_reg)]);
132    }
133}
134
135
136PhysRegIndex
137UnifiedRenameMap::lookup(RegIndex arch_reg) const
138{
139    RegIndex rel_arch_reg;
140
141    switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
142      case IntRegClass:
143        return lookupInt(rel_arch_reg);
144
145      case FloatRegClass:
146        return lookupFloat(rel_arch_reg);
147
148      case CCRegClass:
149        return lookupCC(rel_arch_reg);
150
151      case VectorRegClass:
152        return lookupVector(rel_arch_reg);
153
154      case MiscRegClass:
155        return lookupMisc(rel_arch_reg);
156
157      default:
158        panic("rename lookup(): unknown reg class %s\n",
159              RegClassStrings[regIdxToClass(arch_reg)]);
160    }
161}
162
163void
164UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
165{
166    RegIndex rel_arch_reg;
167
168    switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
169      case IntRegClass:
170        return setIntEntry(rel_arch_reg, phys_reg);
171
172      case FloatRegClass:
173        return setFloatEntry(rel_arch_reg, phys_reg);
174
175      case CCRegClass:
176        return setCCEntry(rel_arch_reg, phys_reg);
177
178      case VectorRegClass:
179        return setVectorEntry(rel_arch_reg, phys_reg);
180
181      case MiscRegClass:
182        // Misc registers do not actually rename, so don't change
183        // their mappings.  We end up here when a commit or squash
184        // tries to update or undo a hardwired misc reg nmapping,
185        // which should always be setting it to what it already is.
186        assert(phys_reg == lookupMisc(rel_arch_reg));
187        return;
188
189      default:
190        panic("rename setEntry(): unknown reg class %s\n",
191              RegClassStrings[regIdxToClass(arch_reg)]);
192    }
193}
194