rename_map.cc revision 9919
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 301689SN/A */ 311464SN/A 321464SN/A#include <vector> 331060SN/A 341717SN/A#include "cpu/o3/rename_map.hh" 358232Snate@binkert.org#include "debug/Rename.hh" 361060SN/A 371464SN/Ausing namespace std; 381464SN/A 399919Ssteve.reinhardt@amd.com/**** SimpleRenameMap methods ****/ 401060SN/A 419919Ssteve.reinhardt@amd.comSimpleRenameMap::SimpleRenameMap() 429919Ssteve.reinhardt@amd.com : freeList(NULL) 431060SN/A{ 442292SN/A} 452292SN/A 461061SN/A 471060SN/Avoid 489919Ssteve.reinhardt@amd.comSimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, 499919Ssteve.reinhardt@amd.com RegIndex _zeroReg) 501060SN/A{ 519919Ssteve.reinhardt@amd.com assert(freeList == NULL); 529919Ssteve.reinhardt@amd.com assert(map.empty()); 539919Ssteve.reinhardt@amd.com 549919Ssteve.reinhardt@amd.com map.resize(size); 559919Ssteve.reinhardt@amd.com freeList = _freeList; 569919Ssteve.reinhardt@amd.com zeroReg = _zeroReg; 571060SN/A} 581060SN/A 591060SN/ASimpleRenameMap::RenameInfo 601060SN/ASimpleRenameMap::rename(RegIndex arch_reg) 611060SN/A{ 621060SN/A PhysRegIndex renamed_reg; 631060SN/A 649919Ssteve.reinhardt@amd.com // Record the current physical register that is renamed to the 659919Ssteve.reinhardt@amd.com // requested architected register. 669919Ssteve.reinhardt@amd.com PhysRegIndex prev_reg = map[arch_reg]; 671060SN/A 689919Ssteve.reinhardt@amd.com // If it's not referencing the zero register, then rename the 699919Ssteve.reinhardt@amd.com // register. 709919Ssteve.reinhardt@amd.com if (arch_reg != zeroReg) { 719919Ssteve.reinhardt@amd.com renamed_reg = freeList->getReg(); 721060SN/A 739919Ssteve.reinhardt@amd.com map[arch_reg] = renamed_reg; 741060SN/A } else { 759919Ssteve.reinhardt@amd.com // Otherwise return the zero register so nothing bad happens. 769919Ssteve.reinhardt@amd.com assert(prev_reg == zeroReg); 779919Ssteve.reinhardt@amd.com renamed_reg = zeroReg; 781060SN/A } 791060SN/A 803867Sbinkertn@umich.edu DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n", 813867Sbinkertn@umich.edu arch_reg, renamed_reg, prev_reg); 823867Sbinkertn@umich.edu 831060SN/A return RenameInfo(renamed_reg, prev_reg); 841060SN/A} 851060SN/A 869919Ssteve.reinhardt@amd.com 879919Ssteve.reinhardt@amd.com/**** UnifiedRenameMap methods ****/ 889919Ssteve.reinhardt@amd.com 899919Ssteve.reinhardt@amd.comvoid 909919Ssteve.reinhardt@amd.comUnifiedRenameMap::init(PhysRegFile *_regFile, 919919Ssteve.reinhardt@amd.com RegIndex _intZeroReg, 929919Ssteve.reinhardt@amd.com RegIndex _floatZeroReg, 939919Ssteve.reinhardt@amd.com UnifiedFreeList *freeList) 949919Ssteve.reinhardt@amd.com{ 959919Ssteve.reinhardt@amd.com regFile = _regFile; 969919Ssteve.reinhardt@amd.com 979919Ssteve.reinhardt@amd.com intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 989919Ssteve.reinhardt@amd.com 999919Ssteve.reinhardt@amd.com floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 1009919Ssteve.reinhardt@amd.com} 1019919Ssteve.reinhardt@amd.com 1029919Ssteve.reinhardt@amd.com 1039919Ssteve.reinhardt@amd.comUnifiedRenameMap::RenameInfo 1049919Ssteve.reinhardt@amd.comUnifiedRenameMap::rename(RegIndex arch_reg) 1059919Ssteve.reinhardt@amd.com{ 1069919Ssteve.reinhardt@amd.com RegIndex rel_arch_reg; 1079919Ssteve.reinhardt@amd.com 1089919Ssteve.reinhardt@amd.com switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 1099919Ssteve.reinhardt@amd.com case IntRegClass: 1109919Ssteve.reinhardt@amd.com return renameInt(rel_arch_reg); 1119919Ssteve.reinhardt@amd.com 1129919Ssteve.reinhardt@amd.com case FloatRegClass: 1139919Ssteve.reinhardt@amd.com return renameFloat(rel_arch_reg); 1149919Ssteve.reinhardt@amd.com 1159919Ssteve.reinhardt@amd.com case MiscRegClass: 1169919Ssteve.reinhardt@amd.com return renameMisc(rel_arch_reg); 1179919Ssteve.reinhardt@amd.com 1189919Ssteve.reinhardt@amd.com default: 1199919Ssteve.reinhardt@amd.com panic("rename rename(): unknown reg class %s\n", 1209919Ssteve.reinhardt@amd.com RegClassStrings[regIdxToClass(arch_reg)]); 1219919Ssteve.reinhardt@amd.com } 1229919Ssteve.reinhardt@amd.com} 1239919Ssteve.reinhardt@amd.com 1249919Ssteve.reinhardt@amd.com 1251060SN/APhysRegIndex 1269919Ssteve.reinhardt@amd.comUnifiedRenameMap::lookup(RegIndex arch_reg) const 1271060SN/A{ 1289919Ssteve.reinhardt@amd.com RegIndex rel_arch_reg; 1291060SN/A 1309919Ssteve.reinhardt@amd.com switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 1319919Ssteve.reinhardt@amd.com case IntRegClass: 1329919Ssteve.reinhardt@amd.com return lookupInt(rel_arch_reg); 1339919Ssteve.reinhardt@amd.com 1349919Ssteve.reinhardt@amd.com case FloatRegClass: 1359919Ssteve.reinhardt@amd.com return lookupFloat(rel_arch_reg); 1369919Ssteve.reinhardt@amd.com 1379919Ssteve.reinhardt@amd.com case MiscRegClass: 1389919Ssteve.reinhardt@amd.com return lookupMisc(rel_arch_reg); 1399919Ssteve.reinhardt@amd.com 1409919Ssteve.reinhardt@amd.com default: 1419919Ssteve.reinhardt@amd.com panic("rename lookup(): unknown reg class %s\n", 1429919Ssteve.reinhardt@amd.com RegClassStrings[regIdxToClass(arch_reg)]); 1431060SN/A } 1441060SN/A} 1451060SN/A 1461060SN/Avoid 1479919Ssteve.reinhardt@amd.comUnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg) 1481060SN/A{ 1499919Ssteve.reinhardt@amd.com RegIndex rel_arch_reg; 1501060SN/A 1519919Ssteve.reinhardt@amd.com switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 1529919Ssteve.reinhardt@amd.com case IntRegClass: 1539919Ssteve.reinhardt@amd.com return setIntEntry(rel_arch_reg, phys_reg); 1541060SN/A 1559919Ssteve.reinhardt@amd.com case FloatRegClass: 1569919Ssteve.reinhardt@amd.com return setFloatEntry(rel_arch_reg, phys_reg); 1579919Ssteve.reinhardt@amd.com 1589919Ssteve.reinhardt@amd.com case MiscRegClass: 1599919Ssteve.reinhardt@amd.com // Misc registers do not actually rename, so don't change 1609919Ssteve.reinhardt@amd.com // their mappings. We end up here when a commit or squash 1619919Ssteve.reinhardt@amd.com // tries to update or undo a hardwired misc reg nmapping, 1629919Ssteve.reinhardt@amd.com // which should always be setting it to what it already is. 1639919Ssteve.reinhardt@amd.com assert(phys_reg == lookupMisc(rel_arch_reg)); 1649919Ssteve.reinhardt@amd.com return; 1659919Ssteve.reinhardt@amd.com 1669919Ssteve.reinhardt@amd.com default: 1679919Ssteve.reinhardt@amd.com panic("rename setEntry(): unknown reg class %s\n", 1689919Ssteve.reinhardt@amd.com RegClassStrings[regIdxToClass(arch_reg)]); 1691060SN/A } 1701060SN/A} 171