rename_map.cc revision 13610
11689SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2016-2017,2019 ARM Limited 312109SRekai.GonzalezAlberquilla@arm.com * All rights reserved 412109SRekai.GonzalezAlberquilla@arm.com * 512109SRekai.GonzalezAlberquilla@arm.com * The license below extends only to copyright in the software and shall 612109SRekai.GonzalezAlberquilla@arm.com * not be construed as granting a license to any other intellectual 712109SRekai.GonzalezAlberquilla@arm.com * property including but not limited to intellectual property relating 812109SRekai.GonzalezAlberquilla@arm.com * to a hardware implementation of the functionality of the software 912109SRekai.GonzalezAlberquilla@arm.com * licensed hereunder. You may use the software subject to the license 1012109SRekai.GonzalezAlberquilla@arm.com * terms below provided that you ensure that this notice is replicated 1112109SRekai.GonzalezAlberquilla@arm.com * unmodified and in its entirety in all distributions of the software, 1212109SRekai.GonzalezAlberquilla@arm.com * modified or unmodified, in source code or in binary form. 1312109SRekai.GonzalezAlberquilla@arm.com * 141689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 159919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 421689SN/A */ 431464SN/A 4411793Sbrandon.potter@amd.com#include "cpu/o3/rename_map.hh" 4511793Sbrandon.potter@amd.com 461464SN/A#include <vector> 471060SN/A 4812857Sradwang@ucdavis.edu#include "cpu/reg_class.hh" 498232Snate@binkert.org#include "debug/Rename.hh" 501060SN/A 511464SN/Ausing namespace std; 521464SN/A 539919Ssteve.reinhardt@amd.com/**** SimpleRenameMap methods ****/ 541060SN/A 559919Ssteve.reinhardt@amd.comSimpleRenameMap::SimpleRenameMap() 5612106SRekai.GonzalezAlberquilla@arm.com : freeList(NULL), zeroReg(IntRegClass,0) 571060SN/A{ 582292SN/A} 592292SN/A 601061SN/A 611060SN/Avoid 629919Ssteve.reinhardt@amd.comSimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, 639919Ssteve.reinhardt@amd.com RegIndex _zeroReg) 641060SN/A{ 659919Ssteve.reinhardt@amd.com assert(freeList == NULL); 669919Ssteve.reinhardt@amd.com assert(map.empty()); 679919Ssteve.reinhardt@amd.com 689919Ssteve.reinhardt@amd.com map.resize(size); 699919Ssteve.reinhardt@amd.com freeList = _freeList; 7012106SRekai.GonzalezAlberquilla@arm.com zeroReg = RegId(IntRegClass, _zeroReg); 711060SN/A} 721060SN/A 731060SN/ASimpleRenameMap::RenameInfo 7412106SRekai.GonzalezAlberquilla@arm.comSimpleRenameMap::rename(const RegId& arch_reg) 751060SN/A{ 7612105Snathanael.premillieu@arm.com PhysRegIdPtr renamed_reg; 779919Ssteve.reinhardt@amd.com // Record the current physical register that is renamed to the 789919Ssteve.reinhardt@amd.com // requested architected register. 7913600Sgiacomo.travaglini@arm.com PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()]; 801060SN/A 819919Ssteve.reinhardt@amd.com // If it's not referencing the zero register, then rename the 829919Ssteve.reinhardt@amd.com // register. 839919Ssteve.reinhardt@amd.com if (arch_reg != zeroReg) { 849919Ssteve.reinhardt@amd.com renamed_reg = freeList->getReg(); 851060SN/A 8613600Sgiacomo.travaglini@arm.com map[arch_reg.flatIndex()] = renamed_reg; 871060SN/A } else { 889919Ssteve.reinhardt@amd.com // Otherwise return the zero register so nothing bad happens. 8912105Snathanael.premillieu@arm.com assert(prev_reg->isZeroReg()); 9012105Snathanael.premillieu@arm.com renamed_reg = prev_reg; 911060SN/A } 921060SN/A 9312105Snathanael.premillieu@arm.com DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was" 9412105Snathanael.premillieu@arm.com " %d (%d)\n", 9513600Sgiacomo.travaglini@arm.com arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(), 9613600Sgiacomo.travaglini@arm.com prev_reg->flatIndex(), prev_reg->flatIndex()); 973867Sbinkertn@umich.edu 981060SN/A return RenameInfo(renamed_reg, prev_reg); 991060SN/A} 1001060SN/A 1019919Ssteve.reinhardt@amd.com 1029919Ssteve.reinhardt@amd.com/**** UnifiedRenameMap methods ****/ 1039919Ssteve.reinhardt@amd.com 1049919Ssteve.reinhardt@amd.comvoid 1059919Ssteve.reinhardt@amd.comUnifiedRenameMap::init(PhysRegFile *_regFile, 1069919Ssteve.reinhardt@amd.com RegIndex _intZeroReg, 1079919Ssteve.reinhardt@amd.com RegIndex _floatZeroReg, 10812109SRekai.GonzalezAlberquilla@arm.com UnifiedFreeList *freeList, 10912109SRekai.GonzalezAlberquilla@arm.com VecMode _mode) 1109919Ssteve.reinhardt@amd.com{ 1119919Ssteve.reinhardt@amd.com regFile = _regFile; 11212109SRekai.GonzalezAlberquilla@arm.com vecMode = _mode; 1139919Ssteve.reinhardt@amd.com 1149919Ssteve.reinhardt@amd.com intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 1159919Ssteve.reinhardt@amd.com 1169919Ssteve.reinhardt@amd.com floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 1179920Syasuko.eckert@amd.com 11812109SRekai.GonzalezAlberquilla@arm.com vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1); 11912109SRekai.GonzalezAlberquilla@arm.com 12012109SRekai.GonzalezAlberquilla@arm.com vecElemMap.init(TheISA::NumVecRegs * NVecElems, 12112109SRekai.GonzalezAlberquilla@arm.com &(freeList->vecElemList), (RegIndex)-1); 12212109SRekai.GonzalezAlberquilla@arm.com 12313610Sgiacomo.gabrielli@arm.com predMap.init(TheISA::NumVecPredRegs, &(freeList->predList), (RegIndex)-1); 12413610Sgiacomo.gabrielli@arm.com 12510897Snilay@cs.wisc.edu ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); 12612105Snathanael.premillieu@arm.com 1279919Ssteve.reinhardt@amd.com} 1289919Ssteve.reinhardt@amd.com 12912109SRekai.GonzalezAlberquilla@arm.comvoid 13013601Sgiacomo.travaglini@arm.comUnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList) 13112109SRekai.GonzalezAlberquilla@arm.com{ 13213601Sgiacomo.travaglini@arm.com if (vecMode == Enums::Elem) { 13313601Sgiacomo.travaglini@arm.com 13412109SRekai.GonzalezAlberquilla@arm.com /* The free list should currently be tracking full registers. */ 13512109SRekai.GonzalezAlberquilla@arm.com panic_if(freeList->hasFreeVecElems(), 13612109SRekai.GonzalezAlberquilla@arm.com "The free list is already tracking Vec elems"); 13712109SRekai.GonzalezAlberquilla@arm.com panic_if(freeList->numFreeVecRegs() != 13812109SRekai.GonzalezAlberquilla@arm.com regFile->numVecPhysRegs() - TheISA::NumVecRegs, 13912109SRekai.GonzalezAlberquilla@arm.com "The free list has lost vector registers"); 14013601Sgiacomo.travaglini@arm.com 14112109SRekai.GonzalezAlberquilla@arm.com /* Split the free regs. */ 14212109SRekai.GonzalezAlberquilla@arm.com while (freeList->hasFreeVecRegs()) { 14312109SRekai.GonzalezAlberquilla@arm.com auto vr = freeList->getVecReg(); 14412109SRekai.GonzalezAlberquilla@arm.com auto range = this->regFile->getRegElemIds(vr); 14512109SRekai.GonzalezAlberquilla@arm.com freeList->addRegs(range.first, range.second); 14612109SRekai.GonzalezAlberquilla@arm.com } 14713601Sgiacomo.travaglini@arm.com 14813601Sgiacomo.travaglini@arm.com } else if (vecMode == Enums::Full) { 14913601Sgiacomo.travaglini@arm.com 15012109SRekai.GonzalezAlberquilla@arm.com /* The free list should currently be tracking register elems. */ 15112109SRekai.GonzalezAlberquilla@arm.com panic_if(freeList->hasFreeVecRegs(), 15212109SRekai.GonzalezAlberquilla@arm.com "The free list is already tracking full Vec"); 15313598Sgiacomo.travaglini@arm.com panic_if(freeList->numFreeVecElems() != 15412109SRekai.GonzalezAlberquilla@arm.com regFile->numVecElemPhysRegs() - TheISA::NumFloatRegs, 15512109SRekai.GonzalezAlberquilla@arm.com "The free list has lost vector register elements"); 15613601Sgiacomo.travaglini@arm.com 15713601Sgiacomo.travaglini@arm.com auto range = regFile->getRegIds(VecRegClass); 15813601Sgiacomo.travaglini@arm.com freeList->addRegs(range.first + TheISA::NumVecRegs, range.second); 15913601Sgiacomo.travaglini@arm.com 16013601Sgiacomo.travaglini@arm.com /* We remove the elems from the free list. */ 16113601Sgiacomo.travaglini@arm.com while (freeList->hasFreeVecElems()) 16213601Sgiacomo.travaglini@arm.com freeList->getVecElem(); 16313601Sgiacomo.travaglini@arm.com } 16413601Sgiacomo.travaglini@arm.com} 16513601Sgiacomo.travaglini@arm.com 16613601Sgiacomo.travaglini@arm.comvoid 16713601Sgiacomo.travaglini@arm.comUnifiedRenameMap::switchMode(VecMode newVecMode) 16813601Sgiacomo.travaglini@arm.com{ 16913601Sgiacomo.travaglini@arm.com if (newVecMode == Enums::Elem && vecMode == Enums::Full) { 17013601Sgiacomo.travaglini@arm.com 17113601Sgiacomo.travaglini@arm.com /* Switch to vector element rename mode. */ 17213601Sgiacomo.travaglini@arm.com vecMode = Enums::Elem; 17313601Sgiacomo.travaglini@arm.com 17413601Sgiacomo.travaglini@arm.com /* Split the mapping of each arch reg. */ 17513601Sgiacomo.travaglini@arm.com int vec_idx = 0; 17613601Sgiacomo.travaglini@arm.com for (auto &vec: vecMap) { 17713601Sgiacomo.travaglini@arm.com PhysRegFile::IdRange range = this->regFile->getRegElemIds(vec); 17813601Sgiacomo.travaglini@arm.com auto idx = 0; 17913601Sgiacomo.travaglini@arm.com for (auto phys_elem = range.first; 18013601Sgiacomo.travaglini@arm.com phys_elem < range.second; idx++, phys_elem++) { 18113601Sgiacomo.travaglini@arm.com 18213601Sgiacomo.travaglini@arm.com setEntry(RegId(VecElemClass, vec_idx, idx), &(*phys_elem)); 18313601Sgiacomo.travaglini@arm.com } 18413601Sgiacomo.travaglini@arm.com vec_idx++; 18513601Sgiacomo.travaglini@arm.com } 18613601Sgiacomo.travaglini@arm.com 18713601Sgiacomo.travaglini@arm.com } else if (newVecMode == Enums::Full && vecMode == Enums::Elem) { 18813601Sgiacomo.travaglini@arm.com 18913601Sgiacomo.travaglini@arm.com /* Switch to full vector register rename mode. */ 19013601Sgiacomo.travaglini@arm.com vecMode = Enums::Full; 19113601Sgiacomo.travaglini@arm.com 19212109SRekai.GonzalezAlberquilla@arm.com /* To rebuild the arch regs we take the easy road: 19312109SRekai.GonzalezAlberquilla@arm.com * 1.- Stitch the elems together into vectors. 19412109SRekai.GonzalezAlberquilla@arm.com * 2.- Replace the contents of the register file with the vectors 19512109SRekai.GonzalezAlberquilla@arm.com * 3.- Set the remaining registers as free 19612109SRekai.GonzalezAlberquilla@arm.com */ 19712109SRekai.GonzalezAlberquilla@arm.com TheISA::VecRegContainer new_RF[TheISA::NumVecRegs]; 19812109SRekai.GonzalezAlberquilla@arm.com for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) { 19912109SRekai.GonzalezAlberquilla@arm.com VecReg dst = new_RF[i].as<TheISA::VecElem>(); 20012109SRekai.GonzalezAlberquilla@arm.com for (uint32_t l = 0; l < NVecElems; l++) { 20112109SRekai.GonzalezAlberquilla@arm.com RegId s_rid(VecElemClass, i, l); 20212109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid); 20312109SRekai.GonzalezAlberquilla@arm.com dst[l] = regFile->readVecElem(s_prid); 20412109SRekai.GonzalezAlberquilla@arm.com } 20512109SRekai.GonzalezAlberquilla@arm.com } 20612109SRekai.GonzalezAlberquilla@arm.com 20712109SRekai.GonzalezAlberquilla@arm.com for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) { 20812109SRekai.GonzalezAlberquilla@arm.com PhysRegId pregId(VecRegClass, i, 0); 20912109SRekai.GonzalezAlberquilla@arm.com regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]); 21012109SRekai.GonzalezAlberquilla@arm.com } 21112109SRekai.GonzalezAlberquilla@arm.com 21212109SRekai.GonzalezAlberquilla@arm.com } 21312109SRekai.GonzalezAlberquilla@arm.com} 214