rename_map.cc revision 12105
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 301689SN/A */ 311464SN/A 3211793Sbrandon.potter@amd.com#include "cpu/o3/rename_map.hh" 3311793Sbrandon.potter@amd.com 341464SN/A#include <vector> 351060SN/A 368232Snate@binkert.org#include "debug/Rename.hh" 371060SN/A 381464SN/Ausing namespace std; 391464SN/A 409919Ssteve.reinhardt@amd.com/**** SimpleRenameMap methods ****/ 411060SN/A 429919Ssteve.reinhardt@amd.comSimpleRenameMap::SimpleRenameMap() 4310537Sandreas.hansson@arm.com : freeList(NULL), zeroReg(0) 441060SN/A{ 452292SN/A} 462292SN/A 471061SN/A 481060SN/Avoid 499919Ssteve.reinhardt@amd.comSimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, 509919Ssteve.reinhardt@amd.com RegIndex _zeroReg) 511060SN/A{ 529919Ssteve.reinhardt@amd.com assert(freeList == NULL); 539919Ssteve.reinhardt@amd.com assert(map.empty()); 549919Ssteve.reinhardt@amd.com 559919Ssteve.reinhardt@amd.com map.resize(size); 569919Ssteve.reinhardt@amd.com freeList = _freeList; 579919Ssteve.reinhardt@amd.com zeroReg = _zeroReg; 581060SN/A} 591060SN/A 601060SN/ASimpleRenameMap::RenameInfo 611060SN/ASimpleRenameMap::rename(RegIndex arch_reg) 621060SN/A{ 6312105Snathanael.premillieu@arm.com PhysRegIdPtr renamed_reg; 641060SN/A 659919Ssteve.reinhardt@amd.com // Record the current physical register that is renamed to the 669919Ssteve.reinhardt@amd.com // requested architected register. 6712105Snathanael.premillieu@arm.com PhysRegIdPtr prev_reg = map[arch_reg]; 681060SN/A 699919Ssteve.reinhardt@amd.com // If it's not referencing the zero register, then rename the 709919Ssteve.reinhardt@amd.com // register. 719919Ssteve.reinhardt@amd.com if (arch_reg != zeroReg) { 729919Ssteve.reinhardt@amd.com renamed_reg = freeList->getReg(); 731060SN/A 749919Ssteve.reinhardt@amd.com map[arch_reg] = renamed_reg; 751060SN/A } else { 769919Ssteve.reinhardt@amd.com // Otherwise return the zero register so nothing bad happens. 7712105Snathanael.premillieu@arm.com assert(prev_reg->isZeroReg()); 7812105Snathanael.premillieu@arm.com renamed_reg = prev_reg; 791060SN/A } 801060SN/A 8112105Snathanael.premillieu@arm.com DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was" 8212105Snathanael.premillieu@arm.com " %d (%d)\n", 8312105Snathanael.premillieu@arm.com arch_reg, renamed_reg->regIdx, renamed_reg->flatIdx, 8412105Snathanael.premillieu@arm.com prev_reg->regIdx, prev_reg->flatIdx); 853867Sbinkertn@umich.edu 861060SN/A return RenameInfo(renamed_reg, prev_reg); 871060SN/A} 881060SN/A 899919Ssteve.reinhardt@amd.com 909919Ssteve.reinhardt@amd.com/**** UnifiedRenameMap methods ****/ 919919Ssteve.reinhardt@amd.com 929919Ssteve.reinhardt@amd.comvoid 939919Ssteve.reinhardt@amd.comUnifiedRenameMap::init(PhysRegFile *_regFile, 949919Ssteve.reinhardt@amd.com RegIndex _intZeroReg, 959919Ssteve.reinhardt@amd.com RegIndex _floatZeroReg, 969919Ssteve.reinhardt@amd.com UnifiedFreeList *freeList) 979919Ssteve.reinhardt@amd.com{ 989919Ssteve.reinhardt@amd.com regFile = _regFile; 999919Ssteve.reinhardt@amd.com 1009919Ssteve.reinhardt@amd.com intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 1019919Ssteve.reinhardt@amd.com 1029919Ssteve.reinhardt@amd.com floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 1039920Syasuko.eckert@amd.com 10410897Snilay@cs.wisc.edu ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); 10512105Snathanael.premillieu@arm.com 1069919Ssteve.reinhardt@amd.com} 1079919Ssteve.reinhardt@amd.com 1089919Ssteve.reinhardt@amd.com 1099919Ssteve.reinhardt@amd.comUnifiedRenameMap::RenameInfo 11012104Snathanael.premillieu@arm.comUnifiedRenameMap::rename(RegId arch_reg) 1119919Ssteve.reinhardt@amd.com{ 11212104Snathanael.premillieu@arm.com switch (arch_reg.regClass) { 1139919Ssteve.reinhardt@amd.com case IntRegClass: 11412104Snathanael.premillieu@arm.com return renameInt(arch_reg.regIdx); 1159919Ssteve.reinhardt@amd.com 1169919Ssteve.reinhardt@amd.com case FloatRegClass: 11712104Snathanael.premillieu@arm.com return renameFloat(arch_reg.regIdx); 1189919Ssteve.reinhardt@amd.com 1199920Syasuko.eckert@amd.com case CCRegClass: 12012104Snathanael.premillieu@arm.com return renameCC(arch_reg.regIdx); 1219920Syasuko.eckert@amd.com 1229919Ssteve.reinhardt@amd.com case MiscRegClass: 12312104Snathanael.premillieu@arm.com return renameMisc(arch_reg.regIdx); 1249919Ssteve.reinhardt@amd.com 1259919Ssteve.reinhardt@amd.com default: 1269919Ssteve.reinhardt@amd.com panic("rename rename(): unknown reg class %s\n", 12712104Snathanael.premillieu@arm.com RegClassStrings[arch_reg.regClass]); 1289919Ssteve.reinhardt@amd.com } 1299919Ssteve.reinhardt@amd.com} 1309919Ssteve.reinhardt@amd.com 1319919Ssteve.reinhardt@amd.com 13212105Snathanael.premillieu@arm.comPhysRegIdPtr 13312104Snathanael.premillieu@arm.comUnifiedRenameMap::lookup(RegId arch_reg) const 1341060SN/A{ 13512104Snathanael.premillieu@arm.com switch (arch_reg.regClass) { 1369919Ssteve.reinhardt@amd.com case IntRegClass: 13712104Snathanael.premillieu@arm.com return lookupInt(arch_reg.regIdx); 1389919Ssteve.reinhardt@amd.com 1399919Ssteve.reinhardt@amd.com case FloatRegClass: 14012104Snathanael.premillieu@arm.com return lookupFloat(arch_reg.regIdx); 1419919Ssteve.reinhardt@amd.com 1429920Syasuko.eckert@amd.com case CCRegClass: 14312104Snathanael.premillieu@arm.com return lookupCC(arch_reg.regIdx); 1449920Syasuko.eckert@amd.com 1459919Ssteve.reinhardt@amd.com case MiscRegClass: 14612104Snathanael.premillieu@arm.com return lookupMisc(arch_reg.regIdx); 1479919Ssteve.reinhardt@amd.com 1489919Ssteve.reinhardt@amd.com default: 1499919Ssteve.reinhardt@amd.com panic("rename lookup(): unknown reg class %s\n", 15012104Snathanael.premillieu@arm.com RegClassStrings[arch_reg.regClass]); 1511060SN/A } 1521060SN/A} 1531060SN/A 1541060SN/Avoid 15512105Snathanael.premillieu@arm.comUnifiedRenameMap::setEntry(RegId arch_reg, PhysRegIdPtr phys_reg) 1561060SN/A{ 15712104Snathanael.premillieu@arm.com switch (arch_reg.regClass) { 1589919Ssteve.reinhardt@amd.com case IntRegClass: 15912104Snathanael.premillieu@arm.com return setIntEntry(arch_reg.regIdx, phys_reg); 1601060SN/A 1619919Ssteve.reinhardt@amd.com case FloatRegClass: 16212104Snathanael.premillieu@arm.com return setFloatEntry(arch_reg.regIdx, phys_reg); 1639919Ssteve.reinhardt@amd.com 1649920Syasuko.eckert@amd.com case CCRegClass: 16512104Snathanael.premillieu@arm.com return setCCEntry(arch_reg.regIdx, phys_reg); 1669920Syasuko.eckert@amd.com 1679919Ssteve.reinhardt@amd.com case MiscRegClass: 1689919Ssteve.reinhardt@amd.com // Misc registers do not actually rename, so don't change 1699919Ssteve.reinhardt@amd.com // their mappings. We end up here when a commit or squash 1709919Ssteve.reinhardt@amd.com // tries to update or undo a hardwired misc reg nmapping, 1719919Ssteve.reinhardt@amd.com // which should always be setting it to what it already is. 17212104Snathanael.premillieu@arm.com assert(phys_reg == lookupMisc(arch_reg.regIdx)); 1739919Ssteve.reinhardt@amd.com return; 1749919Ssteve.reinhardt@amd.com 1759919Ssteve.reinhardt@amd.com default: 1769919Ssteve.reinhardt@amd.com panic("rename setEntry(): unknown reg class %s\n", 17712104Snathanael.premillieu@arm.com RegClassStrings[arch_reg.regClass]); 1781060SN/A } 1791060SN/A} 180