rename_map.cc revision 12104
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 301689SN/A */ 311464SN/A 3211793Sbrandon.potter@amd.com#include "cpu/o3/rename_map.hh" 3311793Sbrandon.potter@amd.com 341464SN/A#include <vector> 351060SN/A 368232Snate@binkert.org#include "debug/Rename.hh" 371060SN/A 381464SN/Ausing namespace std; 391464SN/A 409919Ssteve.reinhardt@amd.com/**** SimpleRenameMap methods ****/ 411060SN/A 429919Ssteve.reinhardt@amd.comSimpleRenameMap::SimpleRenameMap() 4310537Sandreas.hansson@arm.com : freeList(NULL), zeroReg(0) 441060SN/A{ 452292SN/A} 462292SN/A 471061SN/A 481060SN/Avoid 499919Ssteve.reinhardt@amd.comSimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, 509919Ssteve.reinhardt@amd.com RegIndex _zeroReg) 511060SN/A{ 529919Ssteve.reinhardt@amd.com assert(freeList == NULL); 539919Ssteve.reinhardt@amd.com assert(map.empty()); 549919Ssteve.reinhardt@amd.com 559919Ssteve.reinhardt@amd.com map.resize(size); 569919Ssteve.reinhardt@amd.com freeList = _freeList; 579919Ssteve.reinhardt@amd.com zeroReg = _zeroReg; 581060SN/A} 591060SN/A 601060SN/ASimpleRenameMap::RenameInfo 611060SN/ASimpleRenameMap::rename(RegIndex arch_reg) 621060SN/A{ 631060SN/A PhysRegIndex renamed_reg; 641060SN/A 659919Ssteve.reinhardt@amd.com // Record the current physical register that is renamed to the 669919Ssteve.reinhardt@amd.com // requested architected register. 679919Ssteve.reinhardt@amd.com PhysRegIndex prev_reg = map[arch_reg]; 681060SN/A 699919Ssteve.reinhardt@amd.com // If it's not referencing the zero register, then rename the 709919Ssteve.reinhardt@amd.com // register. 719919Ssteve.reinhardt@amd.com if (arch_reg != zeroReg) { 729919Ssteve.reinhardt@amd.com renamed_reg = freeList->getReg(); 731060SN/A 749919Ssteve.reinhardt@amd.com map[arch_reg] = renamed_reg; 751060SN/A } else { 769919Ssteve.reinhardt@amd.com // Otherwise return the zero register so nothing bad happens. 779919Ssteve.reinhardt@amd.com assert(prev_reg == zeroReg); 789919Ssteve.reinhardt@amd.com renamed_reg = zeroReg; 791060SN/A } 801060SN/A 813867Sbinkertn@umich.edu DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n", 823867Sbinkertn@umich.edu arch_reg, renamed_reg, prev_reg); 833867Sbinkertn@umich.edu 841060SN/A return RenameInfo(renamed_reg, prev_reg); 851060SN/A} 861060SN/A 879919Ssteve.reinhardt@amd.com 889919Ssteve.reinhardt@amd.com/**** UnifiedRenameMap methods ****/ 899919Ssteve.reinhardt@amd.com 909919Ssteve.reinhardt@amd.comvoid 919919Ssteve.reinhardt@amd.comUnifiedRenameMap::init(PhysRegFile *_regFile, 929919Ssteve.reinhardt@amd.com RegIndex _intZeroReg, 939919Ssteve.reinhardt@amd.com RegIndex _floatZeroReg, 949919Ssteve.reinhardt@amd.com UnifiedFreeList *freeList) 959919Ssteve.reinhardt@amd.com{ 969919Ssteve.reinhardt@amd.com regFile = _regFile; 979919Ssteve.reinhardt@amd.com 989919Ssteve.reinhardt@amd.com intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 999919Ssteve.reinhardt@amd.com 1009919Ssteve.reinhardt@amd.com floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 1019920Syasuko.eckert@amd.com 10210897Snilay@cs.wisc.edu ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); 1039919Ssteve.reinhardt@amd.com} 1049919Ssteve.reinhardt@amd.com 1059919Ssteve.reinhardt@amd.com 1069919Ssteve.reinhardt@amd.comUnifiedRenameMap::RenameInfo 10712104Snathanael.premillieu@arm.comUnifiedRenameMap::rename(RegId arch_reg) 1089919Ssteve.reinhardt@amd.com{ 10912104Snathanael.premillieu@arm.com switch (arch_reg.regClass) { 1109919Ssteve.reinhardt@amd.com case IntRegClass: 11112104Snathanael.premillieu@arm.com return renameInt(arch_reg.regIdx); 1129919Ssteve.reinhardt@amd.com 1139919Ssteve.reinhardt@amd.com case FloatRegClass: 11412104Snathanael.premillieu@arm.com return renameFloat(arch_reg.regIdx); 1159919Ssteve.reinhardt@amd.com 1169920Syasuko.eckert@amd.com case CCRegClass: 11712104Snathanael.premillieu@arm.com return renameCC(arch_reg.regIdx); 1189920Syasuko.eckert@amd.com 1199919Ssteve.reinhardt@amd.com case MiscRegClass: 12012104Snathanael.premillieu@arm.com return renameMisc(arch_reg.regIdx); 1219919Ssteve.reinhardt@amd.com 1229919Ssteve.reinhardt@amd.com default: 1239919Ssteve.reinhardt@amd.com panic("rename rename(): unknown reg class %s\n", 12412104Snathanael.premillieu@arm.com RegClassStrings[arch_reg.regClass]); 1259919Ssteve.reinhardt@amd.com } 1269919Ssteve.reinhardt@amd.com} 1279919Ssteve.reinhardt@amd.com 1289919Ssteve.reinhardt@amd.com 1291060SN/APhysRegIndex 13012104Snathanael.premillieu@arm.comUnifiedRenameMap::lookup(RegId arch_reg) const 1311060SN/A{ 13212104Snathanael.premillieu@arm.com switch (arch_reg.regClass) { 1339919Ssteve.reinhardt@amd.com case IntRegClass: 13412104Snathanael.premillieu@arm.com return lookupInt(arch_reg.regIdx); 1359919Ssteve.reinhardt@amd.com 1369919Ssteve.reinhardt@amd.com case FloatRegClass: 13712104Snathanael.premillieu@arm.com return lookupFloat(arch_reg.regIdx); 1389919Ssteve.reinhardt@amd.com 1399920Syasuko.eckert@amd.com case CCRegClass: 14012104Snathanael.premillieu@arm.com return lookupCC(arch_reg.regIdx); 1419920Syasuko.eckert@amd.com 1429919Ssteve.reinhardt@amd.com case MiscRegClass: 14312104Snathanael.premillieu@arm.com return lookupMisc(arch_reg.regIdx); 1449919Ssteve.reinhardt@amd.com 1459919Ssteve.reinhardt@amd.com default: 1469919Ssteve.reinhardt@amd.com panic("rename lookup(): unknown reg class %s\n", 14712104Snathanael.premillieu@arm.com RegClassStrings[arch_reg.regClass]); 1481060SN/A } 1491060SN/A} 1501060SN/A 1511060SN/Avoid 15212104Snathanael.premillieu@arm.comUnifiedRenameMap::setEntry(RegId arch_reg, PhysRegIndex phys_reg) 1531060SN/A{ 15412104Snathanael.premillieu@arm.com switch (arch_reg.regClass) { 1559919Ssteve.reinhardt@amd.com case IntRegClass: 15612104Snathanael.premillieu@arm.com return setIntEntry(arch_reg.regIdx, phys_reg); 1571060SN/A 1589919Ssteve.reinhardt@amd.com case FloatRegClass: 15912104Snathanael.premillieu@arm.com return setFloatEntry(arch_reg.regIdx, phys_reg); 1609919Ssteve.reinhardt@amd.com 1619920Syasuko.eckert@amd.com case CCRegClass: 16212104Snathanael.premillieu@arm.com return setCCEntry(arch_reg.regIdx, phys_reg); 1639920Syasuko.eckert@amd.com 1649919Ssteve.reinhardt@amd.com case MiscRegClass: 1659919Ssteve.reinhardt@amd.com // Misc registers do not actually rename, so don't change 1669919Ssteve.reinhardt@amd.com // their mappings. We end up here when a commit or squash 1679919Ssteve.reinhardt@amd.com // tries to update or undo a hardwired misc reg nmapping, 1689919Ssteve.reinhardt@amd.com // which should always be setting it to what it already is. 16912104Snathanael.premillieu@arm.com assert(phys_reg == lookupMisc(arch_reg.regIdx)); 1709919Ssteve.reinhardt@amd.com return; 1719919Ssteve.reinhardt@amd.com 1729919Ssteve.reinhardt@amd.com default: 1739919Ssteve.reinhardt@amd.com panic("rename setEntry(): unknown reg class %s\n", 17412104Snathanael.premillieu@arm.com RegClassStrings[arch_reg.regClass]); 1751060SN/A } 1761060SN/A} 177