rename.hh revision 1062
12623SN/A// Todo: 29442SAndreas.Sandberg@ARM.com// Fix up trap and barrier handling. 39442SAndreas.Sandberg@ARM.com// May want to have different statuses to differentiate the different stall 49442SAndreas.Sandberg@ARM.com// conditions. 59442SAndreas.Sandberg@ARM.com 69442SAndreas.Sandberg@ARM.com#ifndef __SIMPLE_RENAME_HH__ 79442SAndreas.Sandberg@ARM.com#define __SIMPLE_RENAME_HH__ 89442SAndreas.Sandberg@ARM.com 99442SAndreas.Sandberg@ARM.com#include <list> 109442SAndreas.Sandberg@ARM.com 119442SAndreas.Sandberg@ARM.com#include "base/timebuf.hh" 129442SAndreas.Sandberg@ARM.com 139442SAndreas.Sandberg@ARM.com// Will need rename maps for both the int reg file and fp reg file. 142623SN/A// Or change rename map class to handle both. (RegFile handles both.) 152623SN/Atemplate<class Impl> 162623SN/Aclass SimpleRename 172623SN/A{ 182623SN/A public: 192623SN/A // Typedefs from the Impl. 202623SN/A typedef typename Impl::ISA ISA; 212623SN/A typedef typename Impl::CPUPol CPUPol; 222623SN/A typedef typename Impl::DynInstPtr DynInstPtr; 232623SN/A typedef typename Impl::FullCPU FullCPU; 242623SN/A typedef typename Impl::Params Params; 252623SN/A 262623SN/A typedef typename CPUPol::FetchStruct FetchStruct; 272623SN/A typedef typename CPUPol::DecodeStruct DecodeStruct; 282623SN/A typedef typename CPUPol::RenameStruct RenameStruct; 292623SN/A typedef typename CPUPol::TimeStruct TimeStruct; 302623SN/A 312623SN/A // Typedefs from the CPUPol 322623SN/A typedef typename CPUPol::FreeList FreeList; 332623SN/A typedef typename CPUPol::RenameMap RenameMap; 342623SN/A 352623SN/A // Typedefs from the ISA. 362623SN/A typedef typename ISA::Addr Addr; 372623SN/A 382623SN/A public: 392665Ssaidi@eecs.umich.edu // Rename will block if ROB becomes full or issue queue becomes full, 402665Ssaidi@eecs.umich.edu // or there are no free registers to rename to. 412623SN/A // Only case where rename squashes is if IEW squashes. 422623SN/A enum Status { 432623SN/A Running, 442623SN/A Idle, 452623SN/A Squashing, 462623SN/A Blocked, 476973Stjones1@inf.ed.ac.uk Unblocking, 485529Snate@binkert.org BarrierStall 495529Snate@binkert.org }; 502623SN/A 512623SN/A private: 522623SN/A Status _status; 532623SN/A 545529Snate@binkert.org public: 552623SN/A SimpleRename(Params ¶ms); 562623SN/A 572623SN/A void regStats(); 582623SN/A 592623SN/A void setCPU(FullCPU *cpu_ptr); 602623SN/A 615728Sgblack@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 625728Sgblack@eecs.umich.edu 635728Sgblack@eecs.umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 645728Sgblack@eecs.umich.edu 655728Sgblack@eecs.umich.edu void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 665728Sgblack@eecs.umich.edu 675728Sgblack@eecs.umich.edu void setRenameMap(RenameMap *rm_ptr); 685728Sgblack@eecs.umich.edu 695728Sgblack@eecs.umich.edu void setFreeList(FreeList *fl_ptr); 705728Sgblack@eecs.umich.edu 715728Sgblack@eecs.umich.edu void dumpHistory(); 725728Sgblack@eecs.umich.edu 735728Sgblack@eecs.umich.edu void tick(); 745728Sgblack@eecs.umich.edu 755728Sgblack@eecs.umich.edu void rename(); 765728Sgblack@eecs.umich.edu 775728Sgblack@eecs.umich.edu void squash(); 785728Sgblack@eecs.umich.edu 795728Sgblack@eecs.umich.edu private: 805728Sgblack@eecs.umich.edu void block(); 815728Sgblack@eecs.umich.edu 825728Sgblack@eecs.umich.edu inline void unblock(); 835728Sgblack@eecs.umich.edu 845728Sgblack@eecs.umich.edu void doSquash(); 855728Sgblack@eecs.umich.edu 865728Sgblack@eecs.umich.edu void removeFromHistory(InstSeqNum inst_seq_num); 875728Sgblack@eecs.umich.edu 885728Sgblack@eecs.umich.edu inline void renameSrcRegs(DynInstPtr &inst); 895728Sgblack@eecs.umich.edu 905728Sgblack@eecs.umich.edu inline void renameDestRegs(DynInstPtr &inst); 915728Sgblack@eecs.umich.edu 925728Sgblack@eecs.umich.edu inline int calcFreeROBEntries(); 935728Sgblack@eecs.umich.edu 945728Sgblack@eecs.umich.edu inline int calcFreeIQEntries(); 955728Sgblack@eecs.umich.edu 965728Sgblack@eecs.umich.edu /** Holds the previous information for each rename. 975728Sgblack@eecs.umich.edu * Note that often times the inst may have been deleted, so only access 985728Sgblack@eecs.umich.edu * the pointer for the address and do not dereference it. 995728Sgblack@eecs.umich.edu */ 1005728Sgblack@eecs.umich.edu struct RenameHistory { 1015728Sgblack@eecs.umich.edu RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 1025728Sgblack@eecs.umich.edu PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 1035728Sgblack@eecs.umich.edu : instSeqNum(_instSeqNum), archReg(_archReg), 1045728Sgblack@eecs.umich.edu newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), 1055728Sgblack@eecs.umich.edu placeHolder(false) 1065728Sgblack@eecs.umich.edu { 1075728Sgblack@eecs.umich.edu } 1085894Sgblack@eecs.umich.edu 1095894Sgblack@eecs.umich.edu /** Constructor used specifically for cases where a place holder 1105894Sgblack@eecs.umich.edu * rename history entry is being made. 1115894Sgblack@eecs.umich.edu */ 1125894Sgblack@eecs.umich.edu RenameHistory(InstSeqNum _instSeqNum) 1135894Sgblack@eecs.umich.edu : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), 1146023Snate@binkert.org prevPhysReg(0), placeHolder(true) 1156023Snate@binkert.org { 1165894Sgblack@eecs.umich.edu } 1175894Sgblack@eecs.umich.edu 1186023Snate@binkert.org InstSeqNum instSeqNum; 1197944SGiacomo.Gabrielli@arm.com RegIndex archReg; 1207945SAli.Saidi@ARM.com PhysRegIndex newPhysReg; 1219342SAndreas.Sandberg@arm.com PhysRegIndex prevPhysReg; 1227945SAli.Saidi@ARM.com bool placeHolder; 1237945SAli.Saidi@ARM.com }; 1247944SGiacomo.Gabrielli@arm.com 1257944SGiacomo.Gabrielli@arm.com std::list<RenameHistory> historyBuffer; 1266023Snate@binkert.org 1276023Snate@binkert.org /** CPU interface. */ 1285894Sgblack@eecs.umich.edu FullCPU *cpu; 1295894Sgblack@eecs.umich.edu 1305894Sgblack@eecs.umich.edu // Interfaces to objects outside of rename. 1315894Sgblack@eecs.umich.edu /** Time buffer interface. */ 1325894Sgblack@eecs.umich.edu TimeBuffer<TimeStruct> *timeBuffer; 1335894Sgblack@eecs.umich.edu 1346973Stjones1@inf.ed.ac.uk /** Wire to get IEW's output from backwards time buffer. */ 1356973Stjones1@inf.ed.ac.uk typename TimeBuffer<TimeStruct>::wire fromIEW; 1366973Stjones1@inf.ed.ac.uk 1375894Sgblack@eecs.umich.edu /** Wire to get commit's output from backwards time buffer. */ 1385894Sgblack@eecs.umich.edu typename TimeBuffer<TimeStruct>::wire fromCommit; 1395894Sgblack@eecs.umich.edu 1405894Sgblack@eecs.umich.edu /** Wire to write infromation heading to previous stages. */ 1415894Sgblack@eecs.umich.edu // Might not be the best name as not only decode will read it. 1425894Sgblack@eecs.umich.edu typename TimeBuffer<TimeStruct>::wire toDecode; 1435894Sgblack@eecs.umich.edu 1445744Sgblack@eecs.umich.edu /** Rename instruction queue. */ 1455728Sgblack@eecs.umich.edu TimeBuffer<RenameStruct> *renameQueue; 1465728Sgblack@eecs.umich.edu 1475728Sgblack@eecs.umich.edu /** Wire to write any information heading to IEW. */ 1485728Sgblack@eecs.umich.edu typename TimeBuffer<RenameStruct>::wire toIEW; 1498707Sandreas.hansson@arm.com 1508707Sandreas.hansson@arm.com /** Decode instruction queue interface. */ 1518707Sandreas.hansson@arm.com TimeBuffer<DecodeStruct> *decodeQueue; 1528707Sandreas.hansson@arm.com 1538707Sandreas.hansson@arm.com /** Wire to get decode's output from decode queue. */ 1548707Sandreas.hansson@arm.com typename TimeBuffer<DecodeStruct>::wire fromDecode; 1558707Sandreas.hansson@arm.com 1562623SN/A /** Skid buffer between rename and decode. */ 1572623SN/A std::queue<DecodeStruct> skidBuffer; 1582623SN/A 1598707Sandreas.hansson@arm.com /** Rename map interface. */ 1608707Sandreas.hansson@arm.com SimpleRenameMap *renameMap; 1612623SN/A 1622623SN/A /** Free list interface. */ 1632623SN/A FreeList *freeList; 1642623SN/A 1658948Sandreas.hansson@arm.com /** Delay between iew and rename, in ticks. */ 1668948Sandreas.hansson@arm.com int iewToRenameDelay; 1678948Sandreas.hansson@arm.com 1688975Sandreas.hansson@arm.com /** Delay between decode and rename, in ticks. */ 1698948Sandreas.hansson@arm.com int decodeToRenameDelay; 1708707Sandreas.hansson@arm.com 1712948Ssaidi@eecs.umich.edu /** Delay between commit and rename, in ticks. */ 1722948Ssaidi@eecs.umich.edu unsigned commitToRenameDelay; 1732948Ssaidi@eecs.umich.edu 1743349Sbinkertn@umich.edu /** Rename width, in instructions. */ 1752948Ssaidi@eecs.umich.edu unsigned renameWidth; 1762948Ssaidi@eecs.umich.edu 1778707Sandreas.hansson@arm.com /** Commit width, in instructions. Used so rename knows how many 1785336Shines@cs.fsu.edu * instructions might have freed registers in the previous cycle. 1793349Sbinkertn@umich.edu */ 1802948Ssaidi@eecs.umich.edu unsigned commitWidth; 1812948Ssaidi@eecs.umich.edu 1829087Sandreas.hansson@arm.com /** The instruction that rename is currently on. It needs to have 1832623SN/A * persistent state so that when a stall occurs in the middle of a 1842623SN/A * group of instructions, it can restart at the proper instruction. 1858707Sandreas.hansson@arm.com */ 1862623SN/A unsigned numInst; 1872623SN/A 1882623SN/A Stats::Scalar<> renameSquashCycles; 1898707Sandreas.hansson@arm.com Stats::Scalar<> renameIdleCycles; 1909095Sandreas.hansson@arm.com Stats::Scalar<> renameBlockCycles; 1918707Sandreas.hansson@arm.com Stats::Scalar<> renameUnblockCycles; 1922623SN/A Stats::Scalar<> renameRenamedInsts; 1932623SN/A Stats::Scalar<> renameSquashedInsts; 1942623SN/A Stats::Scalar<> renameROBFullEvents; 1952623SN/A Stats::Scalar<> renameIQFullEvents; 1968975Sandreas.hansson@arm.com Stats::Scalar<> renameFullRegistersEvents; 1972623SN/A Stats::Scalar<> renameRenamedOperands; 1982657Ssaidi@eecs.umich.edu Stats::Scalar<> renameRenameLookups; 1992948Ssaidi@eecs.umich.edu Stats::Scalar<> renameHBPlaceHolders; 2002948Ssaidi@eecs.umich.edu Stats::Scalar<> renameCommittedMaps; 2012948Ssaidi@eecs.umich.edu Stats::Scalar<> renameUndoneMaps; 2022948Ssaidi@eecs.umich.edu Stats::Scalar<> renameValidUndoneMaps; 2032948Ssaidi@eecs.umich.edu}; 2042948Ssaidi@eecs.umich.edu 2052948Ssaidi@eecs.umich.edu#endif // __SIMPLE_RENAME_HH__ 2065336Shines@cs.fsu.edu