rename.hh revision 1062
18112Sgblack@eecs.umich.edu// Todo: 28112Sgblack@eecs.umich.edu// Fix up trap and barrier handling. 38112Sgblack@eecs.umich.edu// May want to have different statuses to differentiate the different stall 48112Sgblack@eecs.umich.edu// conditions. 58112Sgblack@eecs.umich.edu 68112Sgblack@eecs.umich.edu#ifndef __SIMPLE_RENAME_HH__ 78112Sgblack@eecs.umich.edu#define __SIMPLE_RENAME_HH__ 88112Sgblack@eecs.umich.edu 98112Sgblack@eecs.umich.edu#include <list> 108112Sgblack@eecs.umich.edu 118112Sgblack@eecs.umich.edu#include "base/timebuf.hh" 128112Sgblack@eecs.umich.edu 138112Sgblack@eecs.umich.edu// Will need rename maps for both the int reg file and fp reg file. 148112Sgblack@eecs.umich.edu// Or change rename map class to handle both. (RegFile handles both.) 158112Sgblack@eecs.umich.edutemplate<class Impl> 168112Sgblack@eecs.umich.educlass SimpleRename 178112Sgblack@eecs.umich.edu{ 188112Sgblack@eecs.umich.edu public: 198112Sgblack@eecs.umich.edu // Typedefs from the Impl. 208112Sgblack@eecs.umich.edu typedef typename Impl::ISA ISA; 218112Sgblack@eecs.umich.edu typedef typename Impl::CPUPol CPUPol; 228112Sgblack@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 238112Sgblack@eecs.umich.edu typedef typename Impl::FullCPU FullCPU; 248112Sgblack@eecs.umich.edu typedef typename Impl::Params Params; 258112Sgblack@eecs.umich.edu 268112Sgblack@eecs.umich.edu typedef typename CPUPol::FetchStruct FetchStruct; 278112Sgblack@eecs.umich.edu typedef typename CPUPol::DecodeStruct DecodeStruct; 288112Sgblack@eecs.umich.edu typedef typename CPUPol::RenameStruct RenameStruct; 298113Sgblack@eecs.umich.edu typedef typename CPUPol::TimeStruct TimeStruct; 308113Sgblack@eecs.umich.edu 318113Sgblack@eecs.umich.edu // Typedefs from the CPUPol 328113Sgblack@eecs.umich.edu typedef typename CPUPol::FreeList FreeList; 338113Sgblack@eecs.umich.edu typedef typename CPUPol::RenameMap RenameMap; 348113Sgblack@eecs.umich.edu 358113Sgblack@eecs.umich.edu // Typedefs from the ISA. 368113Sgblack@eecs.umich.edu typedef typename ISA::Addr Addr; 378113Sgblack@eecs.umich.edu 388113Sgblack@eecs.umich.edu public: 398113Sgblack@eecs.umich.edu // Rename will block if ROB becomes full or issue queue becomes full, 408113Sgblack@eecs.umich.edu // or there are no free registers to rename to. 418113Sgblack@eecs.umich.edu // Only case where rename squashes is if IEW squashes. 428113Sgblack@eecs.umich.edu enum Status { 438113Sgblack@eecs.umich.edu Running, 448113Sgblack@eecs.umich.edu Idle, 458113Sgblack@eecs.umich.edu Squashing, 468113Sgblack@eecs.umich.edu Blocked, 478113Sgblack@eecs.umich.edu Unblocking, 488113Sgblack@eecs.umich.edu BarrierStall 498113Sgblack@eecs.umich.edu }; 508113Sgblack@eecs.umich.edu 518113Sgblack@eecs.umich.edu private: 528113Sgblack@eecs.umich.edu Status _status; 538113Sgblack@eecs.umich.edu 548113Sgblack@eecs.umich.edu public: 558113Sgblack@eecs.umich.edu SimpleRename(Params ¶ms); 568113Sgblack@eecs.umich.edu 578113Sgblack@eecs.umich.edu void regStats(); 588113Sgblack@eecs.umich.edu 598113Sgblack@eecs.umich.edu void setCPU(FullCPU *cpu_ptr); 608113Sgblack@eecs.umich.edu 618113Sgblack@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 628113Sgblack@eecs.umich.edu 638113Sgblack@eecs.umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 648113Sgblack@eecs.umich.edu 658113Sgblack@eecs.umich.edu void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 668113Sgblack@eecs.umich.edu 678113Sgblack@eecs.umich.edu void setRenameMap(RenameMap *rm_ptr); 68 69 void setFreeList(FreeList *fl_ptr); 70 71 void dumpHistory(); 72 73 void tick(); 74 75 void rename(); 76 77 void squash(); 78 79 private: 80 void block(); 81 82 inline void unblock(); 83 84 void doSquash(); 85 86 void removeFromHistory(InstSeqNum inst_seq_num); 87 88 inline void renameSrcRegs(DynInstPtr &inst); 89 90 inline void renameDestRegs(DynInstPtr &inst); 91 92 inline int calcFreeROBEntries(); 93 94 inline int calcFreeIQEntries(); 95 96 /** Holds the previous information for each rename. 97 * Note that often times the inst may have been deleted, so only access 98 * the pointer for the address and do not dereference it. 99 */ 100 struct RenameHistory { 101 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 102 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 103 : instSeqNum(_instSeqNum), archReg(_archReg), 104 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), 105 placeHolder(false) 106 { 107 } 108 109 /** Constructor used specifically for cases where a place holder 110 * rename history entry is being made. 111 */ 112 RenameHistory(InstSeqNum _instSeqNum) 113 : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), 114 prevPhysReg(0), placeHolder(true) 115 { 116 } 117 118 InstSeqNum instSeqNum; 119 RegIndex archReg; 120 PhysRegIndex newPhysReg; 121 PhysRegIndex prevPhysReg; 122 bool placeHolder; 123 }; 124 125 std::list<RenameHistory> historyBuffer; 126 127 /** CPU interface. */ 128 FullCPU *cpu; 129 130 // Interfaces to objects outside of rename. 131 /** Time buffer interface. */ 132 TimeBuffer<TimeStruct> *timeBuffer; 133 134 /** Wire to get IEW's output from backwards time buffer. */ 135 typename TimeBuffer<TimeStruct>::wire fromIEW; 136 137 /** Wire to get commit's output from backwards time buffer. */ 138 typename TimeBuffer<TimeStruct>::wire fromCommit; 139 140 /** Wire to write infromation heading to previous stages. */ 141 // Might not be the best name as not only decode will read it. 142 typename TimeBuffer<TimeStruct>::wire toDecode; 143 144 /** Rename instruction queue. */ 145 TimeBuffer<RenameStruct> *renameQueue; 146 147 /** Wire to write any information heading to IEW. */ 148 typename TimeBuffer<RenameStruct>::wire toIEW; 149 150 /** Decode instruction queue interface. */ 151 TimeBuffer<DecodeStruct> *decodeQueue; 152 153 /** Wire to get decode's output from decode queue. */ 154 typename TimeBuffer<DecodeStruct>::wire fromDecode; 155 156 /** Skid buffer between rename and decode. */ 157 std::queue<DecodeStruct> skidBuffer; 158 159 /** Rename map interface. */ 160 SimpleRenameMap *renameMap; 161 162 /** Free list interface. */ 163 FreeList *freeList; 164 165 /** Delay between iew and rename, in ticks. */ 166 int iewToRenameDelay; 167 168 /** Delay between decode and rename, in ticks. */ 169 int decodeToRenameDelay; 170 171 /** Delay between commit and rename, in ticks. */ 172 unsigned commitToRenameDelay; 173 174 /** Rename width, in instructions. */ 175 unsigned renameWidth; 176 177 /** Commit width, in instructions. Used so rename knows how many 178 * instructions might have freed registers in the previous cycle. 179 */ 180 unsigned commitWidth; 181 182 /** The instruction that rename is currently on. It needs to have 183 * persistent state so that when a stall occurs in the middle of a 184 * group of instructions, it can restart at the proper instruction. 185 */ 186 unsigned numInst; 187 188 Stats::Scalar<> renameSquashCycles; 189 Stats::Scalar<> renameIdleCycles; 190 Stats::Scalar<> renameBlockCycles; 191 Stats::Scalar<> renameUnblockCycles; 192 Stats::Scalar<> renameRenamedInsts; 193 Stats::Scalar<> renameSquashedInsts; 194 Stats::Scalar<> renameROBFullEvents; 195 Stats::Scalar<> renameIQFullEvents; 196 Stats::Scalar<> renameFullRegistersEvents; 197 Stats::Scalar<> renameRenamedOperands; 198 Stats::Scalar<> renameRenameLookups; 199 Stats::Scalar<> renameHBPlaceHolders; 200 Stats::Scalar<> renameCommittedMaps; 201 Stats::Scalar<> renameUndoneMaps; 202 Stats::Scalar<> renameValidUndoneMaps; 203}; 204 205#endif // __SIMPLE_RENAME_HH__ 206