rename.hh revision 1061
12623SN/A// Todo: 213954Sgiacomo.gabrielli@arm.com// Fix up trap and barrier handling. 39442SAndreas.Sandberg@ARM.com// May want to have different statuses to differentiate the different stall 49442SAndreas.Sandberg@ARM.com// conditions. 59442SAndreas.Sandberg@ARM.com 69442SAndreas.Sandberg@ARM.com#ifndef __SIMPLE_RENAME_HH__ 79442SAndreas.Sandberg@ARM.com#define __SIMPLE_RENAME_HH__ 89442SAndreas.Sandberg@ARM.com 99442SAndreas.Sandberg@ARM.com#include <list> 109442SAndreas.Sandberg@ARM.com 119442SAndreas.Sandberg@ARM.com#include "base/timebuf.hh" 129442SAndreas.Sandberg@ARM.com 139442SAndreas.Sandberg@ARM.com// Will need rename maps for both the int reg file and fp reg file. 142623SN/A// Or change rename map class to handle both. (RegFile handles both.) 152623SN/Atemplate<class Impl> 162623SN/Aclass SimpleRename 172623SN/A{ 182623SN/A public: 192623SN/A // Typedefs from the Impl. 202623SN/A typedef typename Impl::ISA ISA; 212623SN/A typedef typename Impl::CPUPol CPUPol; 222623SN/A typedef typename Impl::DynInstPtr DynInstPtr; 232623SN/A typedef typename Impl::FullCPU FullCPU; 242623SN/A typedef typename Impl::Params Params; 252623SN/A 262623SN/A typedef typename CPUPol::FetchStruct FetchStruct; 272623SN/A typedef typename CPUPol::DecodeStruct DecodeStruct; 282623SN/A typedef typename CPUPol::RenameStruct RenameStruct; 292623SN/A typedef typename CPUPol::TimeStruct TimeStruct; 302623SN/A 312623SN/A // Typedefs from the CPUPol 322623SN/A typedef typename CPUPol::FreeList FreeList; 332623SN/A typedef typename CPUPol::RenameMap RenameMap; 342623SN/A 352623SN/A // Typedefs from the ISA. 362623SN/A typedef typename ISA::Addr Addr; 372623SN/A 382623SN/A public: 392665Ssaidi@eecs.umich.edu // Rename will block if ROB becomes full or issue queue becomes full, 402665Ssaidi@eecs.umich.edu // or there are no free registers to rename to. 412623SN/A // Only case where rename squashes is if IEW squashes. 422623SN/A enum Status { 432623SN/A Running, 442623SN/A Idle, 452623SN/A Squashing, 462623SN/A Blocked, 4711147Smitch.hayenga@arm.com Unblocking, 486973Stjones1@inf.ed.ac.uk BarrierStall 495529Snate@binkert.org }; 505529Snate@binkert.org 512623SN/A private: 522623SN/A Status _status; 532623SN/A 542623SN/A public: 555529Snate@binkert.org SimpleRename(Params ¶ms); 562623SN/A 572623SN/A void setCPU(FullCPU *cpu_ptr); 5811169Sandreas.hansson@arm.com 592623SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 602623SN/A 612623SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 625728Sgblack@eecs.umich.edu 635728Sgblack@eecs.umich.edu void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 645728Sgblack@eecs.umich.edu 655728Sgblack@eecs.umich.edu void setRenameMap(RenameMap *rm_ptr); 665728Sgblack@eecs.umich.edu 675728Sgblack@eecs.umich.edu void setFreeList(FreeList *fl_ptr); 685728Sgblack@eecs.umich.edu 695728Sgblack@eecs.umich.edu void dumpHistory(); 705728Sgblack@eecs.umich.edu 715728Sgblack@eecs.umich.edu void tick(); 725728Sgblack@eecs.umich.edu 735728Sgblack@eecs.umich.edu void rename(); 745728Sgblack@eecs.umich.edu 755728Sgblack@eecs.umich.edu void squash(); 765728Sgblack@eecs.umich.edu 775728Sgblack@eecs.umich.edu private: 785728Sgblack@eecs.umich.edu void block(); 795728Sgblack@eecs.umich.edu 805728Sgblack@eecs.umich.edu inline void unblock(); 815728Sgblack@eecs.umich.edu 825728Sgblack@eecs.umich.edu void doSquash(); 835728Sgblack@eecs.umich.edu 845728Sgblack@eecs.umich.edu void removeFromHistory(InstSeqNum inst_seq_num); 855728Sgblack@eecs.umich.edu 865728Sgblack@eecs.umich.edu inline void renameSrcRegs(DynInstPtr &inst); 875728Sgblack@eecs.umich.edu 885728Sgblack@eecs.umich.edu inline void renameDestRegs(DynInstPtr &inst); 895728Sgblack@eecs.umich.edu 905728Sgblack@eecs.umich.edu inline int calcFreeROBEntries(); 915728Sgblack@eecs.umich.edu 925728Sgblack@eecs.umich.edu inline int calcFreeIQEntries(); 935728Sgblack@eecs.umich.edu 945728Sgblack@eecs.umich.edu /** Holds the previous information for each rename. 955728Sgblack@eecs.umich.edu * Note that often times the inst may have been deleted, so only access 965728Sgblack@eecs.umich.edu * the pointer for the address and do not dereference it. 975728Sgblack@eecs.umich.edu */ 985728Sgblack@eecs.umich.edu struct RenameHistory { 995728Sgblack@eecs.umich.edu RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 1005728Sgblack@eecs.umich.edu PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 1015728Sgblack@eecs.umich.edu : instSeqNum(_instSeqNum), archReg(_archReg), 1025728Sgblack@eecs.umich.edu newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), 1035728Sgblack@eecs.umich.edu placeHolder(false) 1045728Sgblack@eecs.umich.edu { 1055728Sgblack@eecs.umich.edu } 1065728Sgblack@eecs.umich.edu 1075728Sgblack@eecs.umich.edu /** Constructor used specifically for cases where a place holder 1085728Sgblack@eecs.umich.edu * rename history entry is being made. 1095894Sgblack@eecs.umich.edu */ 1105894Sgblack@eecs.umich.edu RenameHistory(InstSeqNum _instSeqNum) 1115894Sgblack@eecs.umich.edu : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), 1125894Sgblack@eecs.umich.edu prevPhysReg(0), placeHolder(true) 1135894Sgblack@eecs.umich.edu { 1145894Sgblack@eecs.umich.edu } 1156023Snate@binkert.org 1166023Snate@binkert.org InstSeqNum instSeqNum; 1175894Sgblack@eecs.umich.edu RegIndex archReg; 1185894Sgblack@eecs.umich.edu PhysRegIndex newPhysReg; 1196023Snate@binkert.org PhysRegIndex prevPhysReg; 1207944SGiacomo.Gabrielli@arm.com bool placeHolder; 1217945SAli.Saidi@ARM.com }; 1229342SAndreas.Sandberg@arm.com 1237945SAli.Saidi@ARM.com std::list<RenameHistory> historyBuffer; 1247945SAli.Saidi@ARM.com 1257944SGiacomo.Gabrielli@arm.com /** CPU interface. */ 1267944SGiacomo.Gabrielli@arm.com FullCPU *cpu; 12712749Sgiacomo.travaglini@arm.com 1286023Snate@binkert.org // Interfaces to objects outside of rename. 1295894Sgblack@eecs.umich.edu /** Time buffer interface. */ 1305894Sgblack@eecs.umich.edu TimeBuffer<TimeStruct> *timeBuffer; 1315894Sgblack@eecs.umich.edu 1325894Sgblack@eecs.umich.edu /** Wire to get IEW's output from backwards time buffer. */ 1335894Sgblack@eecs.umich.edu typename TimeBuffer<TimeStruct>::wire fromIEW; 1345894Sgblack@eecs.umich.edu 13511148Smitch.hayenga@arm.com /** Wire to get commit's output from backwards time buffer. */ 13612749Sgiacomo.travaglini@arm.com typename TimeBuffer<TimeStruct>::wire fromCommit; 13712749Sgiacomo.travaglini@arm.com 13812749Sgiacomo.travaglini@arm.com /** Wire to write infromation heading to previous stages. */ 13912749Sgiacomo.travaglini@arm.com // Might not be the best name as not only decode will read it. 1406973Stjones1@inf.ed.ac.uk typename TimeBuffer<TimeStruct>::wire toDecode; 1415894Sgblack@eecs.umich.edu 14210379Sandreas.hansson@arm.com /** Rename instruction queue. */ 1435894Sgblack@eecs.umich.edu TimeBuffer<RenameStruct> *renameQueue; 14412749Sgiacomo.travaglini@arm.com 1455894Sgblack@eecs.umich.edu /** Wire to write any information heading to IEW. */ 14612749Sgiacomo.travaglini@arm.com typename TimeBuffer<RenameStruct>::wire toIEW; 14712749Sgiacomo.travaglini@arm.com 1485894Sgblack@eecs.umich.edu /** Decode instruction queue interface. */ 1495744Sgblack@eecs.umich.edu TimeBuffer<DecodeStruct> *decodeQueue; 1505728Sgblack@eecs.umich.edu 1515728Sgblack@eecs.umich.edu /** Wire to get decode's output from decode queue. */ 1525728Sgblack@eecs.umich.edu typename TimeBuffer<DecodeStruct>::wire fromDecode; 1535728Sgblack@eecs.umich.edu 1548707Sandreas.hansson@arm.com /** Skid buffer between rename and decode. */ 1558707Sandreas.hansson@arm.com std::queue<DecodeStruct> skidBuffer; 1568707Sandreas.hansson@arm.com 1578707Sandreas.hansson@arm.com /** Rename map interface. */ 1588707Sandreas.hansson@arm.com SimpleRenameMap *renameMap; 1598707Sandreas.hansson@arm.com 1609608Sandreas.hansson@arm.com /** Free list interface. */ 1612623SN/A FreeList *freeList; 1622623SN/A 1632623SN/A /** Delay between iew and rename, in ticks. */ 1648707Sandreas.hansson@arm.com int iewToRenameDelay; 16512085Sspwilson2@wisc.edu 16612085Sspwilson2@wisc.edu /** Delay between decode and rename, in ticks. */ 1672623SN/A int decodeToRenameDelay; 1682623SN/A 1692623SN/A /** Delay between commit and rename, in ticks. */ 1702623SN/A unsigned commitToRenameDelay; 1718707Sandreas.hansson@arm.com 1722948Ssaidi@eecs.umich.edu /** Rename width, in instructions. */ 1732948Ssaidi@eecs.umich.edu unsigned renameWidth; 1742948Ssaidi@eecs.umich.edu 1753349Sbinkertn@umich.edu /** Commit width, in instructions. Used so rename knows how many 1762948Ssaidi@eecs.umich.edu * instructions might have freed registers in the previous cycle. 1772948Ssaidi@eecs.umich.edu */ 1788707Sandreas.hansson@arm.com unsigned commitWidth; 1795336Shines@cs.fsu.edu 1803349Sbinkertn@umich.edu /** The instruction that rename is currently on. It needs to have 1812948Ssaidi@eecs.umich.edu * persistent state so that when a stall occurs in the middle of a 1822948Ssaidi@eecs.umich.edu * group of instructions, it can restart at the proper instruction. 18312085Sspwilson2@wisc.edu */ 1842623SN/A unsigned numInst; 1852623SN/A}; 1868707Sandreas.hansson@arm.com 1872623SN/A#endif // __SIMPLE_RENAME_HH__ 1882623SN/A