mem_dep_unit.hh revision 8737
12SN/A/* 21762SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292665SN/A */ 302665SN/A 312665SN/A#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 322SN/A#define __CPU_O3_MEM_DEP_UNIT_HH__ 332SN/A 341722SN/A#include <list> 355480Snate@binkert.org#include <set> 362SN/A 372SN/A#include "base/hashmap.hh" 38146SN/A#include "base/refcnt.hh" 392SN/A#include "base/statistics.hh" 402SN/A#include "cpu/inst_seq.hh" 412158SN/A#include "debug/MemDepUnit.hh" 42146SN/A 431805SN/Astruct SNHash { 44146SN/A size_t operator() (const InstSeqNum &seq_num) const { 451717SN/A unsigned a = (unsigned)seq_num; 462680SN/A unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 475480Snate@binkert.org 482521SN/A return hash; 4956SN/A } 505478SN/A}; 513348SN/A 523348SN/Astruct DerivO3CPUParams; 532521SN/A 545480Snate@binkert.orgtemplate <class Impl> 551805SN/Aclass InstructionQueue; 562SN/A 572SN/A/** 582107SN/A * Memory dependency unit class. This holds the memory dependence predictor. 592SN/A * As memory operations are issued to the IQ, they are also issued to this 605480Snate@binkert.org * unit, which then looks up the prediction as to what they are dependent 615478SN/A * upon. This unit must be checked prior to a memory operation being able 624762SN/A * to issue. Although this is templated, it's somewhat hard to make a generic 632SN/A * memory dependence unit. This one is mostly for store sets; it will be 64545SN/A * quite limited in what other memory dependence predictions it can also 652521SN/A * utilize. Thus this class should be most likely be rewritten for other 662521SN/A * dependence prediction schemes. 672521SN/A */ 682521SN/Atemplate <class MemDepPred, class Impl> 692SN/Aclass MemDepUnit 702SN/A{ 712SN/A protected: 72926SN/A std::string _name; 73926SN/A 74926SN/A public: 75926SN/A typedef typename Impl::DynInstPtr DynInstPtr; 76926SN/A 77926SN/A /** Empty constructor. Must call init() prior to using in this case. */ 78926SN/A MemDepUnit(); 794395SN/A 801805SN/A /** Constructs a MemDepUnit with given parameters. */ 812SN/A MemDepUnit(DerivO3CPUParams *params); 822SN/A 831634SN/A /** Frees up any memory allocated. */ 845480Snate@binkert.org ~MemDepUnit(); 851634SN/A 862549SN/A /** Returns the name of the memory dependence unit. */ 871806SN/A std::string name() const { return _name; } 881634SN/A 891634SN/A /** Initializes the unit with parameters and a thread id. */ 901634SN/A void init(DerivO3CPUParams *params, ThreadID tid); 911634SN/A 921634SN/A /** Registers statistics. */ 932521SN/A void regStats(); 941634SN/A 951634SN/A /** Switches out the memory dependence predictor. */ 962512SN/A void switchOut(); 975480Snate@binkert.org 982SN/A /** Takes over from another CPU's thread. */ 992SN/A void takeOverFrom(); 1002512SN/A 1012512SN/A /** Sets the pointer to the IQ. */ 1022512SN/A void setIQ(InstructionQueue<Impl> *iq_ptr); 1032512SN/A 104540SN/A /** Inserts a memory instruction. */ 1052641SN/A void insert(DynInstPtr &inst); 1062522SN/A 1072641SN/A /** Inserts a non-speculative memory instruction. */ 1082512SN/A void insertNonSpec(DynInstPtr &inst); 1092630SN/A 1104986SN/A /** Inserts a barrier instruction. */ 1112521SN/A void insertBarrier(DynInstPtr &barr_inst); 1122641SN/A 113873SN/A /** Indicate that an instruction has its registers ready. */ 114873SN/A void regsReady(DynInstPtr &inst); 115873SN/A 116873SN/A /** Indicate that a non-speculative instruction is ready. */ 117873SN/A void nonSpecInstReady(DynInstPtr &inst); 1182630SN/A 119873SN/A /** Reschedules an instruction to be re-executed. */ 120873SN/A void reschedule(DynInstPtr &inst); 1212630SN/A 122873SN/A /** Replays all instructions that have been rescheduled by moving them to 123873SN/A * the ready list. 1242630SN/A */ 125873SN/A void replay(DynInstPtr &inst); 126873SN/A 1272630SN/A /** Completes a memory instruction. */ 128873SN/A void completed(DynInstPtr &inst); 129873SN/A 1302512SN/A /** Completes a barrier instruction. */ 1312512SN/A void completeBarrier(DynInstPtr &inst); 1322512SN/A 1334870SN/A /** Wakes any dependents of a memory instruction. */ 134873SN/A void wakeDependents(DynInstPtr &inst); 1355480Snate@binkert.org 1362630SN/A /** Squashes all instructions up until a given sequence number for a 137873SN/A * specific thread. 138873SN/A */ 139873SN/A void squash(const InstSeqNum &squashed_num, ThreadID tid); 140873SN/A 141873SN/A /** Indicates an ordering violation between a store and a younger load. */ 1425478SN/A void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 143873SN/A 144873SN/A /** Issues the given instruction */ 1452630SN/A void issue(DynInstPtr &inst); 146873SN/A 147873SN/A /** Debugging function to dump the lists of instructions. */ 1482630SN/A void dumpLists(); 149873SN/A 150873SN/A private: 1512630SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 152873SN/A 153873SN/A class MemDepEntry; 1542630SN/A 155873SN/A typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr; 156873SN/A 1572630SN/A /** Memory dependence entries that track memory operations, marking 158873SN/A * when the instruction is ready to execute and what instructions depend 159873SN/A * upon it. 1602630SN/A */ 161873SN/A class MemDepEntry : public RefCounted { 162873SN/A public: 1632630SN/A /** Constructs a memory dependence entry. */ 164873SN/A MemDepEntry(DynInstPtr &new_inst) 165873SN/A : inst(new_inst), regsReady(false), memDepReady(false), 1662630SN/A completed(false), squashed(false) 167873SN/A { 168873SN/A#ifdef DEBUG 1692630SN/A ++memdep_count; 170873SN/A 171873SN/A DPRINTF(MemDepUnit, "Memory dependency entry created. " 1722630SN/A "memdep_count=%i %s\n", memdep_count, inst->pcState()); 173873SN/A#endif 174873SN/A } 1752630SN/A 176873SN/A /** Frees any pointers. */ 177873SN/A ~MemDepEntry() 1782114SN/A { 1792114SN/A for (int i = 0; i < dependInsts.size(); ++i) { 1802114SN/A dependInsts[i] = NULL; 1812114SN/A } 1822630SN/A#ifdef DEBUG 1832114SN/A --memdep_count; 1842114SN/A 185873SN/A DPRINTF(MemDepUnit, "Memory dependency entry deleted. " 1865480Snate@binkert.org "memdep_count=%i %s\n", memdep_count, inst->pcState()); 1872630SN/A#endif 188873SN/A } 189873SN/A 1904870SN/A /** Returns the name of the memory dependence entry. */ 1912SN/A std::string name() const { return "memdepentry"; } 1922512SN/A 1932SN/A /** The instruction being tracked. */ 1942SN/A DynInstPtr inst; 1952512SN/A 1965480Snate@binkert.org /** The iterator to the instruction's location inside the list. */ 1972SN/A ListIt listIt; 1982641SN/A 1992641SN/A /** A vector of any dependent instructions. */ 200430SN/A std::vector<MemDepEntryPtr> dependInsts; 2012630SN/A 2022641SN/A /** If the registers are ready or not. */ 2032SN/A bool regsReady; 204430SN/A /** If all memory dependencies have been satisfied. */ 205430SN/A bool memDepReady; 2062SN/A /** If the instruction is completed. */ 207430SN/A bool completed; 2082SN/A /** If the instruction is squashed. */ 209430SN/A bool squashed; 2102SN/A 211430SN/A /** For debugging. */ 2122SN/A#ifdef DEBUG 213430SN/A static int memdep_count; 2142SN/A static int memdep_insert; 215430SN/A static int memdep_erase; 2162SN/A#endif 217430SN/A }; 2182SN/A 219430SN/A /** Finds the memory dependence entry in the hash map. */ 2202SN/A inline MemDepEntryPtr &findInHash(const DynInstPtr &inst); 221430SN/A 2222SN/A /** Moves an entry to the ready list. */ 2232SN/A inline void moveToReady(MemDepEntryPtr &ready_inst_entry); 2242SN/A 2252SN/A typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; 2262SN/A 2272SN/A typedef typename MemDepHash::iterator MemDepHashIt; 228430SN/A 2292SN/A /** A hash map of all memory dependence entries. */ 230430SN/A MemDepHash memDepHash; 2315478SN/A 232430SN/A /** A list of all instructions in the memory dependence unit. */ 2332SN/A std::list<DynInstPtr> instList[Impl::MaxThreads]; 234430SN/A 2352114SN/A /** A list of all instructions that are going to be replayed. */ 2362114SN/A std::list<DynInstPtr> instsToReplay; 2372114SN/A 2382114SN/A /** The memory dependence predictor. It is accessed upon new 2392114SN/A * instructions being added to the IQ, and responds by telling 2402114SN/A * this unit what instruction the newly added instruction is dependent 2412114SN/A * upon. 2422114SN/A */ 2432SN/A MemDepPred depPred; 2442SN/A 2454870SN/A /** Is there an outstanding load barrier that loads must wait on. */ 2462SN/A bool loadBarrier; 2472512SN/A /** The sequence number of the load barrier. */ 248545SN/A InstSeqNum loadBarrierSN; 249545SN/A /** Is there an outstanding store barrier that loads must wait on. */ 2502SN/A bool storeBarrier; 2515480Snate@binkert.org /** The sequence number of the store barrier. */ 2522SN/A InstSeqNum storeBarrierSN; 253222SN/A 254222SN/A /** Pointer to the IQ. */ 255222SN/A InstructionQueue<Impl> *iqPtr; 256222SN/A 257222SN/A /** The thread id of this memory dependence unit. */ 258222SN/A int id; 259222SN/A 260222SN/A /** Stat for number of inserted loads. */ 261222SN/A Stats::Scalar insertedLoads; 262222SN/A /** Stat for number of inserted stores. */ 263222SN/A Stats::Scalar insertedStores; 264222SN/A /** Stat for number of conflicting loads that had to wait for a store. */ 265222SN/A Stats::Scalar conflictingLoads; 266222SN/A /** Stat for number of conflicting stores that had to wait for a store. */ 267222SN/A Stats::Scalar conflictingStores; 268430SN/A}; 2692114SN/A 2702SN/A#endif // __CPU_O3_MEM_DEP_UNIT_HH__ 2712SN/A