mem_dep_unit.hh revision 8737
16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 2004-2006 The Regents of The University of Michigan 36145Snate@binkert.org * All rights reserved. 46145Snate@binkert.org * 56145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66145Snate@binkert.org * modification, are permitted provided that the following conditions are 76145Snate@binkert.org * met: redistributions of source code must retain the above copyright 86145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116145Snate@binkert.org * documentation and/or other materials provided with the distribution; 126145Snate@binkert.org * neither the name of the copyright holders nor the names of its 136145Snate@binkert.org * contributors may be used to endorse or promote products derived from 146145Snate@binkert.org * this software without specific prior written permission. 156145Snate@binkert.org * 166145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145Snate@binkert.org * 286145Snate@binkert.org * Authors: Kevin Lim 296145Snate@binkert.org */ 306145Snate@binkert.org 316284Snate@binkert.org#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 326145Snate@binkert.org#define __CPU_O3_MEM_DEP_UNIT_HH__ 336145Snate@binkert.org 346145Snate@binkert.org#include <list> 356145Snate@binkert.org#include <set> 366145Snate@binkert.org 376145Snate@binkert.org#include "base/hashmap.hh" 386145Snate@binkert.org#include "base/refcnt.hh" 396145Snate@binkert.org#include "base/statistics.hh" 406154Snate@binkert.org#include "cpu/inst_seq.hh" 416154Snate@binkert.org#include "debug/MemDepUnit.hh" 426154Snate@binkert.org 436154Snate@binkert.orgstruct SNHash { 446154Snate@binkert.org size_t operator() (const InstSeqNum &seq_num) const { 456154Snate@binkert.org unsigned a = (unsigned)seq_num; 466154Snate@binkert.org unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 476154Snate@binkert.org 486145Snate@binkert.org return hash; 496145Snate@binkert.org } 506145Snate@binkert.org}; 516145Snate@binkert.org 526145Snate@binkert.orgstruct DerivO3CPUParams; 536145Snate@binkert.org 546165Ssanchezd@stanford.edutemplate <class Impl> 556145Snate@binkert.orgclass InstructionQueue; 566145Snate@binkert.org 576145Snate@binkert.org/** 586145Snate@binkert.org * Memory dependency unit class. This holds the memory dependence predictor. 596145Snate@binkert.org * As memory operations are issued to the IQ, they are also issued to this 606145Snate@binkert.org * unit, which then looks up the prediction as to what they are dependent 616145Snate@binkert.org * upon. This unit must be checked prior to a memory operation being able 626145Snate@binkert.org * to issue. Although this is templated, it's somewhat hard to make a generic 636145Snate@binkert.org * memory dependence unit. This one is mostly for store sets; it will be 646145Snate@binkert.org * quite limited in what other memory dependence predictions it can also 656145Snate@binkert.org * utilize. Thus this class should be most likely be rewritten for other 666145Snate@binkert.org * dependence prediction schemes. 676145Snate@binkert.org */ 686145Snate@binkert.orgtemplate <class MemDepPred, class Impl> 696145Snate@binkert.orgclass MemDepUnit 706145Snate@binkert.org{ 716145Snate@binkert.org protected: 726145Snate@binkert.org std::string _name; 736145Snate@binkert.org 746145Snate@binkert.org public: 756145Snate@binkert.org typedef typename Impl::DynInstPtr DynInstPtr; 766145Snate@binkert.org 776145Snate@binkert.org /** Empty constructor. Must call init() prior to using in this case. */ 786145Snate@binkert.org MemDepUnit(); 796145Snate@binkert.org 806145Snate@binkert.org /** Constructs a MemDepUnit with given parameters. */ 816145Snate@binkert.org MemDepUnit(DerivO3CPUParams *params); 826145Snate@binkert.org 836145Snate@binkert.org /** Frees up any memory allocated. */ 846145Snate@binkert.org ~MemDepUnit(); 856145Snate@binkert.org 866145Snate@binkert.org /** Returns the name of the memory dependence unit. */ 876145Snate@binkert.org std::string name() const { return _name; } 886145Snate@binkert.org 896145Snate@binkert.org /** Initializes the unit with parameters and a thread id. */ 906145Snate@binkert.org void init(DerivO3CPUParams *params, ThreadID tid); 916145Snate@binkert.org 926145Snate@binkert.org /** Registers statistics. */ 936145Snate@binkert.org void regStats(); 946145Snate@binkert.org 956145Snate@binkert.org /** Switches out the memory dependence predictor. */ 966145Snate@binkert.org void switchOut(); 976145Snate@binkert.org 986145Snate@binkert.org /** Takes over from another CPU's thread. */ 996145Snate@binkert.org void takeOverFrom(); 1006145Snate@binkert.org 1016145Snate@binkert.org /** Sets the pointer to the IQ. */ 1026145Snate@binkert.org void setIQ(InstructionQueue<Impl> *iq_ptr); 1036145Snate@binkert.org 1046145Snate@binkert.org /** Inserts a memory instruction. */ 1056145Snate@binkert.org void insert(DynInstPtr &inst); 1066165Ssanchezd@stanford.edu 1076145Snate@binkert.org /** Inserts a non-speculative memory instruction. */ 1086145Snate@binkert.org void insertNonSpec(DynInstPtr &inst); 1096151Sdrh5@cs.wisc.edu 1106151Sdrh5@cs.wisc.edu /** Inserts a barrier instruction. */ 1116145Snate@binkert.org void insertBarrier(DynInstPtr &barr_inst); 1126145Snate@binkert.org 1136145Snate@binkert.org /** Indicate that an instruction has its registers ready. */ 1146145Snate@binkert.org void regsReady(DynInstPtr &inst); 1156145Snate@binkert.org 1166145Snate@binkert.org /** Indicate that a non-speculative instruction is ready. */ 1176145Snate@binkert.org void nonSpecInstReady(DynInstPtr &inst); 1186145Snate@binkert.org 1196145Snate@binkert.org /** Reschedules an instruction to be re-executed. */ 1206145Snate@binkert.org void reschedule(DynInstPtr &inst); 1216145Snate@binkert.org 1226145Snate@binkert.org /** Replays all instructions that have been rescheduled by moving them to 1236145Snate@binkert.org * the ready list. 1246145Snate@binkert.org */ 1256145Snate@binkert.org void replay(DynInstPtr &inst); 1266145Snate@binkert.org 1276152Sdrh5@cs.wisc.edu /** Completes a memory instruction. */ 1286145Snate@binkert.org void completed(DynInstPtr &inst); 1296145Snate@binkert.org 1306145Snate@binkert.org /** Completes a barrier instruction. */ 1316145Snate@binkert.org void completeBarrier(DynInstPtr &inst); 1326145Snate@binkert.org 1336145Snate@binkert.org /** Wakes any dependents of a memory instruction. */ 1346145Snate@binkert.org void wakeDependents(DynInstPtr &inst); 1356145Snate@binkert.org 1366145Snate@binkert.org /** Squashes all instructions up until a given sequence number for a 1376145Snate@binkert.org * specific thread. 1386145Snate@binkert.org */ 1396145Snate@binkert.org void squash(const InstSeqNum &squashed_num, ThreadID tid); 1406145Snate@binkert.org 1416145Snate@binkert.org /** Indicates an ordering violation between a store and a younger load. */ 1426145Snate@binkert.org void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 1436145Snate@binkert.org 1446145Snate@binkert.org /** Issues the given instruction */ 1456165Ssanchezd@stanford.edu void issue(DynInstPtr &inst); 1466165Ssanchezd@stanford.edu 1476165Ssanchezd@stanford.edu /** Debugging function to dump the lists of instructions. */ 1486145Snate@binkert.org void dumpLists(); 1496145Snate@binkert.org 1506145Snate@binkert.org private: 1516145Snate@binkert.org typedef typename std::list<DynInstPtr>::iterator ListIt; 1526145Snate@binkert.org 1536145Snate@binkert.org class MemDepEntry; 1546145Snate@binkert.org 1556145Snate@binkert.org typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr; 1566145Snate@binkert.org 1576145Snate@binkert.org /** Memory dependence entries that track memory operations, marking 1586145Snate@binkert.org * when the instruction is ready to execute and what instructions depend 1596145Snate@binkert.org * upon it. 1606145Snate@binkert.org */ 1616145Snate@binkert.org class MemDepEntry : public RefCounted { 1626145Snate@binkert.org public: 1636145Snate@binkert.org /** Constructs a memory dependence entry. */ 1646145Snate@binkert.org MemDepEntry(DynInstPtr &new_inst) 1656145Snate@binkert.org : inst(new_inst), regsReady(false), memDepReady(false), 1666145Snate@binkert.org completed(false), squashed(false) 1676145Snate@binkert.org { 1686145Snate@binkert.org#ifdef DEBUG 1696145Snate@binkert.org ++memdep_count; 170 171 DPRINTF(MemDepUnit, "Memory dependency entry created. " 172 "memdep_count=%i %s\n", memdep_count, inst->pcState()); 173#endif 174 } 175 176 /** Frees any pointers. */ 177 ~MemDepEntry() 178 { 179 for (int i = 0; i < dependInsts.size(); ++i) { 180 dependInsts[i] = NULL; 181 } 182#ifdef DEBUG 183 --memdep_count; 184 185 DPRINTF(MemDepUnit, "Memory dependency entry deleted. " 186 "memdep_count=%i %s\n", memdep_count, inst->pcState()); 187#endif 188 } 189 190 /** Returns the name of the memory dependence entry. */ 191 std::string name() const { return "memdepentry"; } 192 193 /** The instruction being tracked. */ 194 DynInstPtr inst; 195 196 /** The iterator to the instruction's location inside the list. */ 197 ListIt listIt; 198 199 /** A vector of any dependent instructions. */ 200 std::vector<MemDepEntryPtr> dependInsts; 201 202 /** If the registers are ready or not. */ 203 bool regsReady; 204 /** If all memory dependencies have been satisfied. */ 205 bool memDepReady; 206 /** If the instruction is completed. */ 207 bool completed; 208 /** If the instruction is squashed. */ 209 bool squashed; 210 211 /** For debugging. */ 212#ifdef DEBUG 213 static int memdep_count; 214 static int memdep_insert; 215 static int memdep_erase; 216#endif 217 }; 218 219 /** Finds the memory dependence entry in the hash map. */ 220 inline MemDepEntryPtr &findInHash(const DynInstPtr &inst); 221 222 /** Moves an entry to the ready list. */ 223 inline void moveToReady(MemDepEntryPtr &ready_inst_entry); 224 225 typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; 226 227 typedef typename MemDepHash::iterator MemDepHashIt; 228 229 /** A hash map of all memory dependence entries. */ 230 MemDepHash memDepHash; 231 232 /** A list of all instructions in the memory dependence unit. */ 233 std::list<DynInstPtr> instList[Impl::MaxThreads]; 234 235 /** A list of all instructions that are going to be replayed. */ 236 std::list<DynInstPtr> instsToReplay; 237 238 /** The memory dependence predictor. It is accessed upon new 239 * instructions being added to the IQ, and responds by telling 240 * this unit what instruction the newly added instruction is dependent 241 * upon. 242 */ 243 MemDepPred depPred; 244 245 /** Is there an outstanding load barrier that loads must wait on. */ 246 bool loadBarrier; 247 /** The sequence number of the load barrier. */ 248 InstSeqNum loadBarrierSN; 249 /** Is there an outstanding store barrier that loads must wait on. */ 250 bool storeBarrier; 251 /** The sequence number of the store barrier. */ 252 InstSeqNum storeBarrierSN; 253 254 /** Pointer to the IQ. */ 255 InstructionQueue<Impl> *iqPtr; 256 257 /** The thread id of this memory dependence unit. */ 258 int id; 259 260 /** Stat for number of inserted loads. */ 261 Stats::Scalar insertedLoads; 262 /** Stat for number of inserted stores. */ 263 Stats::Scalar insertedStores; 264 /** Stat for number of conflicting loads that had to wait for a store. */ 265 Stats::Scalar conflictingLoads; 266 /** Stat for number of conflicting stores that had to wait for a store. */ 267 Stats::Scalar conflictingStores; 268}; 269 270#endif // __CPU_O3_MEM_DEP_UNIT_HH__ 271