lsq_unit_impl.hh revision 9944
19814Sandreas.hansson@arm.com 22292SN/A/* 39383SAli.Saidi@ARM.com * Copyright (c) 2010-2012 ARM Limited 47597Sminkyu.jeong@arm.com * All rights reserved 57597Sminkyu.jeong@arm.com * 67597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 77597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 87597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 97597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 107597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 117597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 127597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 137597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 147597Sminkyu.jeong@arm.com * 152292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 162292SN/A * All rights reserved. 172292SN/A * 182292SN/A * Redistribution and use in source and binary forms, with or without 192292SN/A * modification, are permitted provided that the following conditions are 202292SN/A * met: redistributions of source code must retain the above copyright 212292SN/A * notice, this list of conditions and the following disclaimer; 222292SN/A * redistributions in binary form must reproduce the above copyright 232292SN/A * notice, this list of conditions and the following disclaimer in the 242292SN/A * documentation and/or other materials provided with the distribution; 252292SN/A * neither the name of the copyright holders nor the names of its 262292SN/A * contributors may be used to endorse or promote products derived from 272292SN/A * this software without specific prior written permission. 282292SN/A * 292292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422689Sktlim@umich.edu * Korey Sewell 432292SN/A */ 442292SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_LSQ_UNIT_IMPL_HH__ 479944Smatt.horsnell@ARM.com 488591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 493326Sktlim@umich.edu#include "arch/locked_mem.hh" 508229Snate@binkert.org#include "base/str.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 528887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 532907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 542292SN/A#include "cpu/o3/lsq_unit.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 568232Snate@binkert.org#include "debug/IEW.hh" 578232Snate@binkert.org#include "debug/LSQUnit.hh" 589527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 592722Sktlim@umich.edu#include "mem/packet.hh" 602669Sktlim@umich.edu#include "mem/request.hh" 612292SN/A 622669Sktlim@umich.edutemplate<class Impl> 632678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 642678Sktlim@umich.edu LSQUnit *lsq_ptr) 658581Ssteve.reinhardt@amd.com : Event(Default_Pri, AutoDelete), 668581Ssteve.reinhardt@amd.com inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 672292SN/A{ 682292SN/A} 692292SN/A 702669Sktlim@umich.edutemplate<class Impl> 712292SN/Avoid 722678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 732292SN/A{ 749444SAndreas.Sandberg@ARM.com assert(!lsqPtr->cpu->switchedOut()); 759444SAndreas.Sandberg@ARM.com 769444SAndreas.Sandberg@ARM.com lsqPtr->writeback(inst, pkt); 774319Sktlim@umich.edu 784319Sktlim@umich.edu if (pkt->senderState) 794319Sktlim@umich.edu delete pkt->senderState; 804319Sktlim@umich.edu 814319Sktlim@umich.edu delete pkt->req; 822678Sktlim@umich.edu delete pkt; 832678Sktlim@umich.edu} 842292SN/A 852678Sktlim@umich.edutemplate<class Impl> 862678Sktlim@umich.educonst char * 875336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 882678Sktlim@umich.edu{ 894873Sstever@eecs.umich.edu return "Store writeback"; 902678Sktlim@umich.edu} 912292SN/A 922678Sktlim@umich.edutemplate<class Impl> 932678Sktlim@umich.eduvoid 942678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 952678Sktlim@umich.edu{ 962678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 972678Sktlim@umich.edu DynInstPtr inst = state->inst; 987852SMatt.Horsnell@arm.com DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 997852SMatt.Horsnell@arm.com DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 1002344SN/A 1012678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 1022678Sktlim@umich.edu 1036974Stjones1@inf.ed.ac.uk // If this is a split access, wait until all packets are received. 1046974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1056974Stjones1@inf.ed.ac.uk delete pkt->req; 1066974Stjones1@inf.ed.ac.uk delete pkt; 1076974Stjones1@inf.ed.ac.uk return; 1086974Stjones1@inf.ed.ac.uk } 1096974Stjones1@inf.ed.ac.uk 1109444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 1119444SAndreas.Sandberg@ARM.com if (inst->isSquashed()) { 1122820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 1132678Sktlim@umich.edu } else { 1142678Sktlim@umich.edu if (!state->noWB) { 1156974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1166974Stjones1@inf.ed.ac.uk !state->isLoad) { 1176974Stjones1@inf.ed.ac.uk writeback(inst, pkt); 1186974Stjones1@inf.ed.ac.uk } else { 1196974Stjones1@inf.ed.ac.uk writeback(inst, state->mainPkt); 1206974Stjones1@inf.ed.ac.uk } 1212678Sktlim@umich.edu } 1222678Sktlim@umich.edu 1232678Sktlim@umich.edu if (inst->isStore()) { 1242678Sktlim@umich.edu completeStore(state->idx); 1252678Sktlim@umich.edu } 1262344SN/A } 1272307SN/A 1286974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1296974Stjones1@inf.ed.ac.uk delete state->mainPkt->req; 1306974Stjones1@inf.ed.ac.uk delete state->mainPkt; 1316974Stjones1@inf.ed.ac.uk } 1322678Sktlim@umich.edu delete state; 1334032Sktlim@umich.edu delete pkt->req; 1342678Sktlim@umich.edu delete pkt; 1352292SN/A} 1362292SN/A 1372292SN/Atemplate <class Impl> 1382292SN/ALSQUnit<Impl>::LSQUnit() 1398545Ssaidi@eecs.umich.edu : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 1402678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1418727Snilay@cs.wisc.edu loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) 1422292SN/A{ 1432292SN/A} 1442292SN/A 1452292SN/Atemplate<class Impl> 1462292SN/Avoid 1475529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1485529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1495529Snate@binkert.org unsigned id) 1502292SN/A{ 1514329Sktlim@umich.edu cpu = cpu_ptr; 1524329Sktlim@umich.edu iewStage = iew_ptr; 1534329Sktlim@umich.edu 1544329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1552292SN/A 1562907Sktlim@umich.edu lsq = lsq_ptr; 1572907Sktlim@umich.edu 1582292SN/A lsqID = id; 1592292SN/A 1602329SN/A // Add 1 for the sentinel entry (they are circular queues). 1612329SN/A LQEntries = maxLQEntries + 1; 1622329SN/A SQEntries = maxSQEntries + 1; 1632292SN/A 1649936SFaissal.Sleiman@arm.com //Due to uint8_t index in LSQSenderState 1659936SFaissal.Sleiman@arm.com assert(LQEntries <= 256); 1669936SFaissal.Sleiman@arm.com assert(SQEntries <= 256); 1679936SFaissal.Sleiman@arm.com 1682292SN/A loadQueue.resize(LQEntries); 1692292SN/A storeQueue.resize(SQEntries); 1702292SN/A 1718199SAli.Saidi@ARM.com depCheckShift = params->LSQDepCheckShift; 1728199SAli.Saidi@ARM.com checkLoads = params->LSQCheckLoads; 1739444SAndreas.Sandberg@ARM.com cachePorts = params->cachePorts; 1749444SAndreas.Sandberg@ARM.com needsTSO = params->needsTSO; 1759444SAndreas.Sandberg@ARM.com 1769444SAndreas.Sandberg@ARM.com resetState(); 1779444SAndreas.Sandberg@ARM.com} 1789444SAndreas.Sandberg@ARM.com 1799444SAndreas.Sandberg@ARM.com 1809444SAndreas.Sandberg@ARM.comtemplate<class Impl> 1819444SAndreas.Sandberg@ARM.comvoid 1829444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::resetState() 1839444SAndreas.Sandberg@ARM.com{ 1849444SAndreas.Sandberg@ARM.com loads = stores = storesToWB = 0; 1858199SAli.Saidi@ARM.com 1862292SN/A loadHead = loadTail = 0; 1872292SN/A 1882292SN/A storeHead = storeWBIdx = storeTail = 0; 1892292SN/A 1902292SN/A usedPorts = 0; 1912292SN/A 1923492Sktlim@umich.edu retryPkt = NULL; 1932329SN/A memDepViolator = NULL; 1942292SN/A 1952292SN/A blockedLoadSeqNum = 0; 1969444SAndreas.Sandberg@ARM.com 1979444SAndreas.Sandberg@ARM.com stalled = false; 1989444SAndreas.Sandberg@ARM.com isLoadBlocked = false; 1999444SAndreas.Sandberg@ARM.com loadBlockedHandled = false; 2009444SAndreas.Sandberg@ARM.com 2019814Sandreas.hansson@arm.com cacheBlockMask = ~(cpu->cacheLineSize() - 1); 2022292SN/A} 2032292SN/A 2042292SN/Atemplate<class Impl> 2052292SN/Astd::string 2062292SN/ALSQUnit<Impl>::name() const 2072292SN/A{ 2082292SN/A if (Impl::MaxThreads == 1) { 2092292SN/A return iewStage->name() + ".lsq"; 2102292SN/A } else { 2118247Snate@binkert.org return iewStage->name() + ".lsq.thread" + to_string(lsqID); 2122292SN/A } 2132292SN/A} 2142292SN/A 2152292SN/Atemplate<class Impl> 2162292SN/Avoid 2172727Sktlim@umich.eduLSQUnit<Impl>::regStats() 2182727Sktlim@umich.edu{ 2192727Sktlim@umich.edu lsqForwLoads 2202727Sktlim@umich.edu .name(name() + ".forwLoads") 2212727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 2222727Sktlim@umich.edu 2232727Sktlim@umich.edu invAddrLoads 2242727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2252727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2262727Sktlim@umich.edu 2272727Sktlim@umich.edu lsqSquashedLoads 2282727Sktlim@umich.edu .name(name() + ".squashedLoads") 2292727Sktlim@umich.edu .desc("Number of loads squashed"); 2302727Sktlim@umich.edu 2312727Sktlim@umich.edu lsqIgnoredResponses 2322727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2332727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2342727Sktlim@umich.edu 2352361SN/A lsqMemOrderViolation 2362361SN/A .name(name() + ".memOrderViolation") 2372361SN/A .desc("Number of memory ordering violations"); 2382361SN/A 2392727Sktlim@umich.edu lsqSquashedStores 2402727Sktlim@umich.edu .name(name() + ".squashedStores") 2412727Sktlim@umich.edu .desc("Number of stores squashed"); 2422727Sktlim@umich.edu 2432727Sktlim@umich.edu invAddrSwpfs 2442727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2452727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2462727Sktlim@umich.edu 2472727Sktlim@umich.edu lsqBlockedLoads 2482727Sktlim@umich.edu .name(name() + ".blockedLoads") 2492727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2502727Sktlim@umich.edu 2512727Sktlim@umich.edu lsqRescheduledLoads 2522727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2532727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2542727Sktlim@umich.edu 2552727Sktlim@umich.edu lsqCacheBlocked 2562727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2572727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2582727Sktlim@umich.edu} 2592727Sktlim@umich.edu 2602727Sktlim@umich.edutemplate<class Impl> 2612727Sktlim@umich.eduvoid 2628922Swilliam.wang@arm.comLSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 2634329Sktlim@umich.edu{ 2644329Sktlim@umich.edu dcachePort = dcache_port; 2654329Sktlim@umich.edu} 2664329Sktlim@umich.edu 2674329Sktlim@umich.edutemplate<class Impl> 2684329Sktlim@umich.eduvoid 2692292SN/ALSQUnit<Impl>::clearLQ() 2702292SN/A{ 2712292SN/A loadQueue.clear(); 2722292SN/A} 2732292SN/A 2742292SN/Atemplate<class Impl> 2752292SN/Avoid 2762292SN/ALSQUnit<Impl>::clearSQ() 2772292SN/A{ 2782292SN/A storeQueue.clear(); 2792292SN/A} 2802292SN/A 2812292SN/Atemplate<class Impl> 2822292SN/Avoid 2839444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::drainSanityCheck() const 2842307SN/A{ 2859444SAndreas.Sandberg@ARM.com for (int i = 0; i < loadQueue.size(); ++i) 2862367SN/A assert(!loadQueue[i]); 2872307SN/A 2882329SN/A assert(storesToWB == 0); 2899444SAndreas.Sandberg@ARM.com assert(!retryPkt); 2902307SN/A} 2912307SN/A 2922307SN/Atemplate<class Impl> 2932307SN/Avoid 2942307SN/ALSQUnit<Impl>::takeOverFrom() 2952307SN/A{ 2969444SAndreas.Sandberg@ARM.com resetState(); 2972307SN/A} 2982307SN/A 2992307SN/Atemplate<class Impl> 3002307SN/Avoid 3012292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 3022292SN/A{ 3032329SN/A unsigned size_plus_sentinel = size + 1; 3042329SN/A assert(size_plus_sentinel >= LQEntries); 3052292SN/A 3062329SN/A if (size_plus_sentinel > LQEntries) { 3072329SN/A while (size_plus_sentinel > loadQueue.size()) { 3082292SN/A DynInstPtr dummy; 3092292SN/A loadQueue.push_back(dummy); 3102292SN/A LQEntries++; 3112292SN/A } 3122292SN/A } else { 3132329SN/A LQEntries = size_plus_sentinel; 3142292SN/A } 3152292SN/A 3169936SFaissal.Sleiman@arm.com assert(LQEntries <= 256); 3172292SN/A} 3182292SN/A 3192292SN/Atemplate<class Impl> 3202292SN/Avoid 3212292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3222292SN/A{ 3232329SN/A unsigned size_plus_sentinel = size + 1; 3242329SN/A if (size_plus_sentinel > SQEntries) { 3252329SN/A while (size_plus_sentinel > storeQueue.size()) { 3262292SN/A SQEntry dummy; 3272292SN/A storeQueue.push_back(dummy); 3282292SN/A SQEntries++; 3292292SN/A } 3302292SN/A } else { 3312329SN/A SQEntries = size_plus_sentinel; 3322292SN/A } 3339936SFaissal.Sleiman@arm.com 3349936SFaissal.Sleiman@arm.com assert(SQEntries <= 256); 3352292SN/A} 3362292SN/A 3372292SN/Atemplate <class Impl> 3382292SN/Avoid 3392292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3402292SN/A{ 3412292SN/A assert(inst->isMemRef()); 3422292SN/A 3432292SN/A assert(inst->isLoad() || inst->isStore()); 3442292SN/A 3452292SN/A if (inst->isLoad()) { 3462292SN/A insertLoad(inst); 3472292SN/A } else { 3482292SN/A insertStore(inst); 3492292SN/A } 3502292SN/A 3512292SN/A inst->setInLSQ(); 3522292SN/A} 3532292SN/A 3542292SN/Atemplate <class Impl> 3552292SN/Avoid 3562292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3572292SN/A{ 3582329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3592329SN/A assert(loads < LQEntries); 3602292SN/A 3617720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3627720Sgblack@eecs.umich.edu load_inst->pcState(), loadTail, load_inst->seqNum); 3632292SN/A 3642292SN/A load_inst->lqIdx = loadTail; 3652292SN/A 3662292SN/A if (stores == 0) { 3672292SN/A load_inst->sqIdx = -1; 3682292SN/A } else { 3692292SN/A load_inst->sqIdx = storeTail; 3702292SN/A } 3712292SN/A 3722292SN/A loadQueue[loadTail] = load_inst; 3732292SN/A 3742292SN/A incrLdIdx(loadTail); 3752292SN/A 3762292SN/A ++loads; 3772292SN/A} 3782292SN/A 3792292SN/Atemplate <class Impl> 3802292SN/Avoid 3812292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3822292SN/A{ 3832292SN/A // Make sure it is not full before inserting an instruction. 3842292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3852292SN/A assert(stores < SQEntries); 3862292SN/A 3877720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3887720Sgblack@eecs.umich.edu store_inst->pcState(), storeTail, store_inst->seqNum); 3892292SN/A 3902292SN/A store_inst->sqIdx = storeTail; 3912292SN/A store_inst->lqIdx = loadTail; 3922292SN/A 3932292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3942292SN/A 3952292SN/A incrStIdx(storeTail); 3962292SN/A 3972292SN/A ++stores; 3982292SN/A} 3992292SN/A 4002292SN/Atemplate <class Impl> 4012292SN/Atypename Impl::DynInstPtr 4022292SN/ALSQUnit<Impl>::getMemDepViolator() 4032292SN/A{ 4042292SN/A DynInstPtr temp = memDepViolator; 4052292SN/A 4062292SN/A memDepViolator = NULL; 4072292SN/A 4082292SN/A return temp; 4092292SN/A} 4102292SN/A 4112292SN/Atemplate <class Impl> 4122292SN/Aunsigned 4132292SN/ALSQUnit<Impl>::numFreeEntries() 4142292SN/A{ 4152292SN/A unsigned free_lq_entries = LQEntries - loads; 4162292SN/A unsigned free_sq_entries = SQEntries - stores; 4172292SN/A 4182292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4192292SN/A // empty/full conditions. Subtract 1 from the free entries. 4202292SN/A if (free_lq_entries < free_sq_entries) { 4212292SN/A return free_lq_entries - 1; 4222292SN/A } else { 4232292SN/A return free_sq_entries - 1; 4242292SN/A } 4252292SN/A} 4262292SN/A 4272292SN/Atemplate <class Impl> 4288545Ssaidi@eecs.umich.eduvoid 4298545Ssaidi@eecs.umich.eduLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 4308545Ssaidi@eecs.umich.edu{ 4318545Ssaidi@eecs.umich.edu int load_idx = loadHead; 4328545Ssaidi@eecs.umich.edu 4339383SAli.Saidi@ARM.com // Unlock the cpu-local monitor when the CPU sees a snoop to a locked 4349383SAli.Saidi@ARM.com // address. The CPU can speculatively execute a LL operation after a pending 4359383SAli.Saidi@ARM.com // SC operation in the pipeline and that can make the cache monitor the CPU 4369383SAli.Saidi@ARM.com // is connected to valid while it really shouldn't be. 4379383SAli.Saidi@ARM.com for (int x = 0; x < cpu->numActiveThreads(); x++) { 4389383SAli.Saidi@ARM.com ThreadContext *tc = cpu->getContext(x); 4399383SAli.Saidi@ARM.com bool no_squash = cpu->thread[x]->noSquashFromTC; 4409383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = true; 4419383SAli.Saidi@ARM.com TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 4429383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = no_squash; 4439383SAli.Saidi@ARM.com } 4449383SAli.Saidi@ARM.com 4458545Ssaidi@eecs.umich.edu // If this is the only load in the LSQ we don't care 4468545Ssaidi@eecs.umich.edu if (load_idx == loadTail) 4478545Ssaidi@eecs.umich.edu return; 4488545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4498545Ssaidi@eecs.umich.edu 4508545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 4518545Ssaidi@eecs.umich.edu Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 4528545Ssaidi@eecs.umich.edu while (load_idx != loadTail) { 4538545Ssaidi@eecs.umich.edu DynInstPtr ld_inst = loadQueue[load_idx]; 4548545Ssaidi@eecs.umich.edu 4559046SAli.Saidi@ARM.com if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 4568545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4578545Ssaidi@eecs.umich.edu continue; 4588545Ssaidi@eecs.umich.edu } 4598545Ssaidi@eecs.umich.edu 4608545Ssaidi@eecs.umich.edu Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 4618545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 4628545Ssaidi@eecs.umich.edu ld_inst->seqNum, load_addr, invalidate_addr); 4638545Ssaidi@eecs.umich.edu 4648545Ssaidi@eecs.umich.edu if (load_addr == invalidate_addr) { 4659046SAli.Saidi@ARM.com if (ld_inst->possibleLoadViolation()) { 4668545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 4678545Ssaidi@eecs.umich.edu ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum); 4688545Ssaidi@eecs.umich.edu 4698545Ssaidi@eecs.umich.edu // Mark the load for re-execution 4708545Ssaidi@eecs.umich.edu ld_inst->fault = new ReExec; 4718545Ssaidi@eecs.umich.edu } else { 4728545Ssaidi@eecs.umich.edu // If a older load checks this and it's true 4738545Ssaidi@eecs.umich.edu // then we might have missed the snoop 4748545Ssaidi@eecs.umich.edu // in which case we need to invalidate to be sure 4759046SAli.Saidi@ARM.com ld_inst->hitExternalSnoop(true); 4768545Ssaidi@eecs.umich.edu } 4778545Ssaidi@eecs.umich.edu } 4788545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4798545Ssaidi@eecs.umich.edu } 4808545Ssaidi@eecs.umich.edu return; 4818545Ssaidi@eecs.umich.edu} 4828545Ssaidi@eecs.umich.edu 4838545Ssaidi@eecs.umich.edutemplate <class Impl> 4842292SN/AFault 4858199SAli.Saidi@ARM.comLSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 4868199SAli.Saidi@ARM.com{ 4878199SAli.Saidi@ARM.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 4888199SAli.Saidi@ARM.com Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 4898199SAli.Saidi@ARM.com 4908199SAli.Saidi@ARM.com /** @todo in theory you only need to check an instruction that has executed 4918199SAli.Saidi@ARM.com * however, there isn't a good way in the pipeline at the moment to check 4928199SAli.Saidi@ARM.com * all instructions that will execute before the store writes back. Thus, 4938199SAli.Saidi@ARM.com * like the implementation that came before it, we're overly conservative. 4948199SAli.Saidi@ARM.com */ 4958199SAli.Saidi@ARM.com while (load_idx != loadTail) { 4968199SAli.Saidi@ARM.com DynInstPtr ld_inst = loadQueue[load_idx]; 4979046SAli.Saidi@ARM.com if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 4988199SAli.Saidi@ARM.com incrLdIdx(load_idx); 4998199SAli.Saidi@ARM.com continue; 5008199SAli.Saidi@ARM.com } 5018199SAli.Saidi@ARM.com 5028199SAli.Saidi@ARM.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 5038199SAli.Saidi@ARM.com Addr ld_eff_addr2 = 5048199SAli.Saidi@ARM.com (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 5058199SAli.Saidi@ARM.com 5068272SAli.Saidi@ARM.com if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 5078545Ssaidi@eecs.umich.edu if (inst->isLoad()) { 5088545Ssaidi@eecs.umich.edu // If this load is to the same block as an external snoop 5098545Ssaidi@eecs.umich.edu // invalidate that we've observed then the load needs to be 5108545Ssaidi@eecs.umich.edu // squashed as it could have newer data 5119046SAli.Saidi@ARM.com if (ld_inst->hitExternalSnoop()) { 5128545Ssaidi@eecs.umich.edu if (!memDepViolator || 5138545Ssaidi@eecs.umich.edu ld_inst->seqNum < memDepViolator->seqNum) { 5148545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 5158592Sgblack@eecs.umich.edu "and [sn:%lli] at address %#x\n", 5168592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5178545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5188199SAli.Saidi@ARM.com 5198545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5208199SAli.Saidi@ARM.com 5218591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault( 5228591Sgblack@eecs.umich.edu "Detected fault with inst [sn:%lli] and " 5238591Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5248591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5258545Ssaidi@eecs.umich.edu } 5268545Ssaidi@eecs.umich.edu } 5278199SAli.Saidi@ARM.com 5288545Ssaidi@eecs.umich.edu // Otherwise, mark the load has a possible load violation 5298545Ssaidi@eecs.umich.edu // and if we see a snoop before it's commited, we need to squash 5309046SAli.Saidi@ARM.com ld_inst->possibleLoadViolation(true); 5318545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 5328545Ssaidi@eecs.umich.edu " between instructions [sn:%lli] and [sn:%lli]\n", 5338545Ssaidi@eecs.umich.edu inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 5348545Ssaidi@eecs.umich.edu } else { 5358545Ssaidi@eecs.umich.edu // A load/store incorrectly passed this store. 5368545Ssaidi@eecs.umich.edu // Check if we already have a violator, or if it's newer 5378545Ssaidi@eecs.umich.edu // squash and refetch. 5388545Ssaidi@eecs.umich.edu if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5398545Ssaidi@eecs.umich.edu break; 5408545Ssaidi@eecs.umich.edu 5418592Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 5428592Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5438592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5448545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5458545Ssaidi@eecs.umich.edu 5468545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5478545Ssaidi@eecs.umich.edu 5488591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault("Detected fault with " 5498591Sgblack@eecs.umich.edu "inst [sn:%lli] and [sn:%lli] at address %#x\n", 5508591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5518545Ssaidi@eecs.umich.edu } 5528199SAli.Saidi@ARM.com } 5538199SAli.Saidi@ARM.com 5548199SAli.Saidi@ARM.com incrLdIdx(load_idx); 5558199SAli.Saidi@ARM.com } 5568199SAli.Saidi@ARM.com return NoFault; 5578199SAli.Saidi@ARM.com} 5588199SAli.Saidi@ARM.com 5598199SAli.Saidi@ARM.com 5608199SAli.Saidi@ARM.com 5618199SAli.Saidi@ARM.com 5628199SAli.Saidi@ARM.comtemplate <class Impl> 5638199SAli.Saidi@ARM.comFault 5642292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 5652292SN/A{ 5664032Sktlim@umich.edu using namespace TheISA; 5672292SN/A // Execute a specific load. 5682292SN/A Fault load_fault = NoFault; 5692292SN/A 5707720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 5717944SGiacomo.Gabrielli@arm.com inst->pcState(), inst->seqNum); 5722292SN/A 5734032Sktlim@umich.edu assert(!inst->isSquashed()); 5744032Sktlim@umich.edu 5752669Sktlim@umich.edu load_fault = inst->initiateAcc(); 5762292SN/A 5777944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 5787944SGiacomo.Gabrielli@arm.com load_fault == NoFault) 5797944SGiacomo.Gabrielli@arm.com return load_fault; 5807944SGiacomo.Gabrielli@arm.com 5817597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 5827597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 5837597Sminkyu.jeong@arm.com if (load_fault != NoFault || inst->readPredicate() == false) { 5842329SN/A // Send this instruction to commit, also make sure iew stage 5852329SN/A // realizes there is activity. 5862367SN/A // Mark it as executed unless it is an uncached load that 5872367SN/A // needs to hit the head of commit. 5887848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 5897848SAli.Saidi@ARM.com inst->forwardOldRegs(); 5907600Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 5917600Sminkyu.jeong@arm.com inst->seqNum, 5927600Sminkyu.jeong@arm.com (load_fault != NoFault ? "fault" : "predication")); 5934032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 5943731Sktlim@umich.edu inst->isAtCommit()) { 5952367SN/A inst->setExecuted(); 5962367SN/A } 5972292SN/A iewStage->instToCommit(inst); 5982292SN/A iewStage->activityThisCycle(); 5994032Sktlim@umich.edu } else if (!loadBlocked()) { 6009046SAli.Saidi@ARM.com assert(inst->effAddrValid()); 6014032Sktlim@umich.edu int load_idx = inst->lqIdx; 6024032Sktlim@umich.edu incrLdIdx(load_idx); 6034032Sktlim@umich.edu 6048199SAli.Saidi@ARM.com if (checkLoads) 6058199SAli.Saidi@ARM.com return checkViolations(load_idx, inst); 6062292SN/A } 6072292SN/A 6082292SN/A return load_fault; 6092292SN/A} 6102292SN/A 6112292SN/Atemplate <class Impl> 6122292SN/AFault 6132292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 6142292SN/A{ 6152292SN/A using namespace TheISA; 6162292SN/A // Make sure that a store exists. 6172292SN/A assert(stores != 0); 6182292SN/A 6192292SN/A int store_idx = store_inst->sqIdx; 6202292SN/A 6217720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 6227720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6232292SN/A 6244032Sktlim@umich.edu assert(!store_inst->isSquashed()); 6254032Sktlim@umich.edu 6262292SN/A // Check the recently completed loads to see if any match this store's 6272292SN/A // address. If so, then we have a memory ordering violation. 6282292SN/A int load_idx = store_inst->lqIdx; 6292292SN/A 6302292SN/A Fault store_fault = store_inst->initiateAcc(); 6312292SN/A 6327944SGiacomo.Gabrielli@arm.com if (store_inst->isTranslationDelayed() && 6337944SGiacomo.Gabrielli@arm.com store_fault == NoFault) 6347944SGiacomo.Gabrielli@arm.com return store_fault; 6357944SGiacomo.Gabrielli@arm.com 6367848SAli.Saidi@ARM.com if (store_inst->readPredicate() == false) 6377848SAli.Saidi@ARM.com store_inst->forwardOldRegs(); 6387848SAli.Saidi@ARM.com 6392329SN/A if (storeQueue[store_idx].size == 0) { 6407782Sminkyu.jeong@arm.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 6417720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6422292SN/A 6432292SN/A return store_fault; 6447782Sminkyu.jeong@arm.com } else if (store_inst->readPredicate() == false) { 6457782Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 6467782Sminkyu.jeong@arm.com store_inst->seqNum); 6477782Sminkyu.jeong@arm.com return store_fault; 6482292SN/A } 6492292SN/A 6502292SN/A assert(store_fault == NoFault); 6512292SN/A 6522336SN/A if (store_inst->isStoreConditional()) { 6532336SN/A // Store conditionals need to set themselves as able to 6542336SN/A // writeback if we haven't had a fault by here. 6552329SN/A storeQueue[store_idx].canWB = true; 6562292SN/A 6572329SN/A ++storesToWB; 6582292SN/A } 6592292SN/A 6608199SAli.Saidi@ARM.com return checkViolations(load_idx, store_inst); 6612292SN/A 6622292SN/A} 6632292SN/A 6642292SN/Atemplate <class Impl> 6652292SN/Avoid 6662292SN/ALSQUnit<Impl>::commitLoad() 6672292SN/A{ 6682292SN/A assert(loadQueue[loadHead]); 6692292SN/A 6707720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 6717720Sgblack@eecs.umich.edu loadQueue[loadHead]->pcState()); 6722292SN/A 6732292SN/A loadQueue[loadHead] = NULL; 6742292SN/A 6752292SN/A incrLdIdx(loadHead); 6762292SN/A 6772292SN/A --loads; 6782292SN/A} 6792292SN/A 6802292SN/Atemplate <class Impl> 6812292SN/Avoid 6822292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 6832292SN/A{ 6842292SN/A assert(loads == 0 || loadQueue[loadHead]); 6852292SN/A 6862292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 6872292SN/A commitLoad(); 6882292SN/A } 6892292SN/A} 6902292SN/A 6912292SN/Atemplate <class Impl> 6922292SN/Avoid 6932292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 6942292SN/A{ 6952292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 6962292SN/A 6972292SN/A int store_idx = storeHead; 6982292SN/A 6992292SN/A while (store_idx != storeTail) { 7002292SN/A assert(storeQueue[store_idx].inst); 7012329SN/A // Mark any stores that are now committed and have not yet 7022329SN/A // been marked as able to write back. 7032292SN/A if (!storeQueue[store_idx].canWB) { 7042292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 7052292SN/A break; 7062292SN/A } 7072292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 7087720Sgblack@eecs.umich.edu "%s [sn:%lli]\n", 7097720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 7102292SN/A storeQueue[store_idx].inst->seqNum); 7112292SN/A 7122292SN/A storeQueue[store_idx].canWB = true; 7132292SN/A 7142292SN/A ++storesToWB; 7152292SN/A } 7162292SN/A 7172292SN/A incrStIdx(store_idx); 7182292SN/A } 7192292SN/A} 7202292SN/A 7212292SN/Atemplate <class Impl> 7222292SN/Avoid 7236974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::writebackPendingStore() 7246974Stjones1@inf.ed.ac.uk{ 7256974Stjones1@inf.ed.ac.uk if (hasPendingPkt) { 7266974Stjones1@inf.ed.ac.uk assert(pendingPkt != NULL); 7276974Stjones1@inf.ed.ac.uk 7286974Stjones1@inf.ed.ac.uk // If the cache is blocked, this will store the packet for retry. 7296974Stjones1@inf.ed.ac.uk if (sendStore(pendingPkt)) { 7306974Stjones1@inf.ed.ac.uk storePostSend(pendingPkt); 7316974Stjones1@inf.ed.ac.uk } 7326974Stjones1@inf.ed.ac.uk pendingPkt = NULL; 7336974Stjones1@inf.ed.ac.uk hasPendingPkt = false; 7346974Stjones1@inf.ed.ac.uk } 7356974Stjones1@inf.ed.ac.uk} 7366974Stjones1@inf.ed.ac.uk 7376974Stjones1@inf.ed.ac.uktemplate <class Impl> 7386974Stjones1@inf.ed.ac.ukvoid 7392292SN/ALSQUnit<Impl>::writebackStores() 7402292SN/A{ 7416974Stjones1@inf.ed.ac.uk // First writeback the second packet from any split store that didn't 7426974Stjones1@inf.ed.ac.uk // complete last cycle because there weren't enough cache ports available. 7436974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 7446974Stjones1@inf.ed.ac.uk writebackPendingStore(); 7456974Stjones1@inf.ed.ac.uk } 7466974Stjones1@inf.ed.ac.uk 7472292SN/A while (storesToWB > 0 && 7482292SN/A storeWBIdx != storeTail && 7492292SN/A storeQueue[storeWBIdx].inst && 7502292SN/A storeQueue[storeWBIdx].canWB && 7518727Snilay@cs.wisc.edu ((!needsTSO) || (!storeInFlight)) && 7522292SN/A usedPorts < cachePorts) { 7532292SN/A 7542907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 7552678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 7562678Sktlim@umich.edu " is blocked!\n"); 7572678Sktlim@umich.edu break; 7582678Sktlim@umich.edu } 7592678Sktlim@umich.edu 7602329SN/A // Store didn't write any data so no need to write it back to 7612329SN/A // memory. 7622292SN/A if (storeQueue[storeWBIdx].size == 0) { 7632292SN/A completeStore(storeWBIdx); 7642292SN/A 7652292SN/A incrStIdx(storeWBIdx); 7662292SN/A 7672292SN/A continue; 7682292SN/A } 7692678Sktlim@umich.edu 7702292SN/A ++usedPorts; 7712292SN/A 7722292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 7732292SN/A incrStIdx(storeWBIdx); 7742292SN/A 7752292SN/A continue; 7762292SN/A } 7772292SN/A 7782292SN/A assert(storeQueue[storeWBIdx].req); 7792292SN/A assert(!storeQueue[storeWBIdx].committed); 7802292SN/A 7816974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 7826974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqLow); 7836974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqHigh); 7846974Stjones1@inf.ed.ac.uk } 7856974Stjones1@inf.ed.ac.uk 7862669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 7872669Sktlim@umich.edu 7882669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 7898481Sgblack@eecs.umich.edu RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 7908481Sgblack@eecs.umich.edu RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 7918481Sgblack@eecs.umich.edu 7922292SN/A storeQueue[storeWBIdx].committed = true; 7932292SN/A 7942669Sktlim@umich.edu assert(!inst->memData); 7952669Sktlim@umich.edu inst->memData = new uint8_t[64]; 7963772Sgblack@eecs.umich.edu 7974326Sgblack@eecs.umich.edu memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 7982669Sktlim@umich.edu 7994878Sstever@eecs.umich.edu MemCmd command = 8004878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 8016102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 8026974Stjones1@inf.ed.ac.uk PacketPtr data_pkt; 8036974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 8042292SN/A 8052678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 8062678Sktlim@umich.edu state->isLoad = false; 8072678Sktlim@umich.edu state->idx = storeWBIdx; 8082678Sktlim@umich.edu state->inst = inst; 8096974Stjones1@inf.ed.ac.uk 8106974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 8116974Stjones1@inf.ed.ac.uk 8126974Stjones1@inf.ed.ac.uk // Build a single data packet if the store isn't split. 8138949Sandreas.hansson@arm.com data_pkt = new Packet(req, command); 8146974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8156974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8166974Stjones1@inf.ed.ac.uk } else { 8176974Stjones1@inf.ed.ac.uk // Create two packets if the store is split in two. 8188949Sandreas.hansson@arm.com data_pkt = new Packet(sreqLow, command); 8198949Sandreas.hansson@arm.com snd_data_pkt = new Packet(sreqHigh, command); 8206974Stjones1@inf.ed.ac.uk 8216974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8226974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 8236974Stjones1@inf.ed.ac.uk 8246974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8256974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 8266974Stjones1@inf.ed.ac.uk 8276974Stjones1@inf.ed.ac.uk state->isSplit = true; 8286974Stjones1@inf.ed.ac.uk state->outstanding = 2; 8296974Stjones1@inf.ed.ac.uk 8306974Stjones1@inf.ed.ac.uk // Can delete the main request now. 8316974Stjones1@inf.ed.ac.uk delete req; 8326974Stjones1@inf.ed.ac.uk req = sreqLow; 8336974Stjones1@inf.ed.ac.uk } 8342678Sktlim@umich.edu 8357720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 8362292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 8377720Sgblack@eecs.umich.edu storeWBIdx, inst->pcState(), 8383797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 8393221Sktlim@umich.edu inst->seqNum); 8402292SN/A 8412693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 8424350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 8436974Stjones1@inf.ed.ac.uk assert(!storeQueue[storeWBIdx].isSplit); 8443326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 8453326Sktlim@umich.edu // misc regs normally updates the result, but this is not 8463326Sktlim@umich.edu // the desired behavior when handling store conditionals. 8479046SAli.Saidi@ARM.com inst->recordResult(false); 8483326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 8499046SAli.Saidi@ARM.com inst->recordResult(true); 8503326Sktlim@umich.edu 8513326Sktlim@umich.edu if (!success) { 8523326Sktlim@umich.edu // Instantly complete this store. 8533326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 8543326Sktlim@umich.edu "Instantly completing it.\n", 8553326Sktlim@umich.edu inst->seqNum); 8563326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 8577823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick() + 1); 8588887Sgeoffrey.blake@arm.com if (cpu->checker) { 8598887Sgeoffrey.blake@arm.com // Make sure to set the LLSC data for verification 8608887Sgeoffrey.blake@arm.com // if checker is loaded 8618887Sgeoffrey.blake@arm.com inst->reqToVerify->setExtraData(0); 8628887Sgeoffrey.blake@arm.com inst->completeAcc(data_pkt); 8638887Sgeoffrey.blake@arm.com } 8643326Sktlim@umich.edu completeStore(storeWBIdx); 8653326Sktlim@umich.edu incrStIdx(storeWBIdx); 8663326Sktlim@umich.edu continue; 8672693Sktlim@umich.edu } 8682693Sktlim@umich.edu } else { 8692693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 8702693Sktlim@umich.edu state->noWB = true; 8712693Sktlim@umich.edu } 8722693Sktlim@umich.edu 8738481Sgblack@eecs.umich.edu bool split = 8748481Sgblack@eecs.umich.edu TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 8758481Sgblack@eecs.umich.edu 8768481Sgblack@eecs.umich.edu ThreadContext *thread = cpu->tcBase(lsqID); 8778481Sgblack@eecs.umich.edu 8788481Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 8798481Sgblack@eecs.umich.edu assert(!inst->isStoreConditional()); 8808481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, data_pkt); 8818481Sgblack@eecs.umich.edu delete data_pkt; 8828481Sgblack@eecs.umich.edu if (split) { 8838481Sgblack@eecs.umich.edu assert(snd_data_pkt->req->isMmappedIpr()); 8848481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, snd_data_pkt); 8858481Sgblack@eecs.umich.edu delete snd_data_pkt; 8868481Sgblack@eecs.umich.edu delete sreqLow; 8878481Sgblack@eecs.umich.edu delete sreqHigh; 8888481Sgblack@eecs.umich.edu } 8898481Sgblack@eecs.umich.edu delete state; 8908481Sgblack@eecs.umich.edu delete req; 8918481Sgblack@eecs.umich.edu completeStore(storeWBIdx); 8928481Sgblack@eecs.umich.edu incrStIdx(storeWBIdx); 8938481Sgblack@eecs.umich.edu } else if (!sendStore(data_pkt)) { 8944032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 8953221Sktlim@umich.edu "retry later\n", 8963221Sktlim@umich.edu inst->seqNum); 8976974Stjones1@inf.ed.ac.uk 8986974Stjones1@inf.ed.ac.uk // Need to store the second packet, if split. 8998481Sgblack@eecs.umich.edu if (split) { 9006974Stjones1@inf.ed.ac.uk state->pktToSend = true; 9016974Stjones1@inf.ed.ac.uk state->pendingPacket = snd_data_pkt; 9026974Stjones1@inf.ed.ac.uk } 9032669Sktlim@umich.edu } else { 9046974Stjones1@inf.ed.ac.uk 9056974Stjones1@inf.ed.ac.uk // If split, try to send the second packet too 9068481Sgblack@eecs.umich.edu if (split) { 9076974Stjones1@inf.ed.ac.uk assert(snd_data_pkt); 9086974Stjones1@inf.ed.ac.uk 9096974Stjones1@inf.ed.ac.uk // Ensure there are enough ports to use. 9106974Stjones1@inf.ed.ac.uk if (usedPorts < cachePorts) { 9116974Stjones1@inf.ed.ac.uk ++usedPorts; 9126974Stjones1@inf.ed.ac.uk if (sendStore(snd_data_pkt)) { 9136974Stjones1@inf.ed.ac.uk storePostSend(snd_data_pkt); 9146974Stjones1@inf.ed.ac.uk } else { 9156974Stjones1@inf.ed.ac.uk DPRINTF(IEW, "D-Cache became blocked when writing" 9166974Stjones1@inf.ed.ac.uk " [sn:%lli] second packet, will retry later\n", 9176974Stjones1@inf.ed.ac.uk inst->seqNum); 9186974Stjones1@inf.ed.ac.uk } 9196974Stjones1@inf.ed.ac.uk } else { 9206974Stjones1@inf.ed.ac.uk 9216974Stjones1@inf.ed.ac.uk // Store the packet for when there's free ports. 9226974Stjones1@inf.ed.ac.uk assert(pendingPkt == NULL); 9236974Stjones1@inf.ed.ac.uk pendingPkt = snd_data_pkt; 9246974Stjones1@inf.ed.ac.uk hasPendingPkt = true; 9256974Stjones1@inf.ed.ac.uk } 9266974Stjones1@inf.ed.ac.uk } else { 9276974Stjones1@inf.ed.ac.uk 9286974Stjones1@inf.ed.ac.uk // Not a split store. 9296974Stjones1@inf.ed.ac.uk storePostSend(data_pkt); 9306974Stjones1@inf.ed.ac.uk } 9312292SN/A } 9322292SN/A } 9332292SN/A 9342292SN/A // Not sure this should set it to 0. 9352292SN/A usedPorts = 0; 9362292SN/A 9372292SN/A assert(stores >= 0 && storesToWB >= 0); 9382292SN/A} 9392292SN/A 9402292SN/A/*template <class Impl> 9412292SN/Avoid 9422292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 9432292SN/A{ 9442292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 9452292SN/A mshrSeqNums.end(), 9462292SN/A seqNum); 9472292SN/A 9482292SN/A if (mshr_it != mshrSeqNums.end()) { 9492292SN/A mshrSeqNums.erase(mshr_it); 9502292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 9512292SN/A } 9522292SN/A}*/ 9532292SN/A 9542292SN/Atemplate <class Impl> 9552292SN/Avoid 9562292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 9572292SN/A{ 9582292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 9592329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 9602292SN/A 9612292SN/A int load_idx = loadTail; 9622292SN/A decrLdIdx(load_idx); 9632292SN/A 9642292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 9657720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 9662292SN/A "[sn:%lli]\n", 9677720Sgblack@eecs.umich.edu loadQueue[load_idx]->pcState(), 9682292SN/A loadQueue[load_idx]->seqNum); 9692292SN/A 9702292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 9712292SN/A stalled = false; 9722292SN/A stallingStoreIsn = 0; 9732292SN/A stallingLoadIdx = 0; 9742292SN/A } 9752292SN/A 9762329SN/A // Clear the smart pointer to make sure it is decremented. 9772731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 9782292SN/A loadQueue[load_idx] = NULL; 9792292SN/A --loads; 9802292SN/A 9812292SN/A // Inefficient! 9822292SN/A loadTail = load_idx; 9832292SN/A 9842292SN/A decrLdIdx(load_idx); 9852727Sktlim@umich.edu ++lsqSquashedLoads; 9862292SN/A } 9872292SN/A 9882292SN/A if (isLoadBlocked) { 9892292SN/A if (squashed_num < blockedLoadSeqNum) { 9902292SN/A isLoadBlocked = false; 9912292SN/A loadBlockedHandled = false; 9922292SN/A blockedLoadSeqNum = 0; 9932292SN/A } 9942292SN/A } 9952292SN/A 9964032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 9974032Sktlim@umich.edu memDepViolator = NULL; 9984032Sktlim@umich.edu } 9994032Sktlim@umich.edu 10002292SN/A int store_idx = storeTail; 10012292SN/A decrStIdx(store_idx); 10022292SN/A 10032292SN/A while (stores != 0 && 10042292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 10052329SN/A // Instructions marked as can WB are already committed. 10062292SN/A if (storeQueue[store_idx].canWB) { 10072292SN/A break; 10082292SN/A } 10092292SN/A 10107720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 10112292SN/A "idx:%i [sn:%lli]\n", 10127720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 10132292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 10142292SN/A 10152329SN/A // I don't think this can happen. It should have been cleared 10162329SN/A // by the stalling load. 10172292SN/A if (isStalled() && 10182292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10192292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 10202292SN/A stalled = false; 10212292SN/A stallingStoreIsn = 0; 10222292SN/A } 10232292SN/A 10242329SN/A // Clear the smart pointer to make sure it is decremented. 10252731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 10262292SN/A storeQueue[store_idx].inst = NULL; 10272292SN/A storeQueue[store_idx].canWB = 0; 10282292SN/A 10294032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 10304032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 10314032Sktlim@umich.edu // place to really handle request deletes. 10324032Sktlim@umich.edu delete storeQueue[store_idx].req; 10336974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 10346974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqLow; 10356974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqHigh; 10366974Stjones1@inf.ed.ac.uk 10376974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = NULL; 10386974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = NULL; 10396974Stjones1@inf.ed.ac.uk } 10404032Sktlim@umich.edu 10412292SN/A storeQueue[store_idx].req = NULL; 10422292SN/A --stores; 10432292SN/A 10442292SN/A // Inefficient! 10452292SN/A storeTail = store_idx; 10462292SN/A 10472292SN/A decrStIdx(store_idx); 10482727Sktlim@umich.edu ++lsqSquashedStores; 10492292SN/A } 10502292SN/A} 10512292SN/A 10522292SN/Atemplate <class Impl> 10532292SN/Avoid 10543349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 10552693Sktlim@umich.edu{ 10562693Sktlim@umich.edu if (isStalled() && 10572693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 10582693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10592693Sktlim@umich.edu "load idx:%i\n", 10602693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 10612693Sktlim@umich.edu stalled = false; 10622693Sktlim@umich.edu stallingStoreIsn = 0; 10632693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10642693Sktlim@umich.edu } 10652693Sktlim@umich.edu 10662693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 10672693Sktlim@umich.edu // The store is basically completed at this time. This 10682693Sktlim@umich.edu // only works so long as the checker doesn't try to 10692693Sktlim@umich.edu // verify the value in memory for stores. 10702693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 10718887Sgeoffrey.blake@arm.com 10722693Sktlim@umich.edu if (cpu->checker) { 10732732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 10742693Sktlim@umich.edu } 10752693Sktlim@umich.edu } 10762693Sktlim@umich.edu 10778727Snilay@cs.wisc.edu if (needsTSO) { 10788727Snilay@cs.wisc.edu storeInFlight = true; 10798727Snilay@cs.wisc.edu } 10808727Snilay@cs.wisc.edu 10812693Sktlim@umich.edu incrStIdx(storeWBIdx); 10822693Sktlim@umich.edu} 10832693Sktlim@umich.edu 10842693Sktlim@umich.edutemplate <class Impl> 10852693Sktlim@umich.eduvoid 10862678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 10872678Sktlim@umich.edu{ 10882678Sktlim@umich.edu iewStage->wakeCPU(); 10892678Sktlim@umich.edu 10902678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 10912678Sktlim@umich.edu if (inst->isSquashed()) { 10922927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 10932678Sktlim@umich.edu assert(!inst->isStore()); 10942727Sktlim@umich.edu ++lsqIgnoredResponses; 10952678Sktlim@umich.edu return; 10962678Sktlim@umich.edu } 10972678Sktlim@umich.edu 10982678Sktlim@umich.edu if (!inst->isExecuted()) { 10992678Sktlim@umich.edu inst->setExecuted(); 11002678Sktlim@umich.edu 11012678Sktlim@umich.edu // Complete access to copy data to proper place. 11022678Sktlim@umich.edu inst->completeAcc(pkt); 11032678Sktlim@umich.edu } 11042678Sktlim@umich.edu 11052678Sktlim@umich.edu // Need to insert instruction into queue to commit 11062678Sktlim@umich.edu iewStage->instToCommit(inst); 11072678Sktlim@umich.edu 11082678Sktlim@umich.edu iewStage->activityThisCycle(); 11097598Sminkyu.jeong@arm.com 11107598Sminkyu.jeong@arm.com // see if this load changed the PC 11117598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 11122678Sktlim@umich.edu} 11132678Sktlim@umich.edu 11142678Sktlim@umich.edutemplate <class Impl> 11152678Sktlim@umich.eduvoid 11162292SN/ALSQUnit<Impl>::completeStore(int store_idx) 11172292SN/A{ 11182292SN/A assert(storeQueue[store_idx].inst); 11192292SN/A storeQueue[store_idx].completed = true; 11202292SN/A --storesToWB; 11212292SN/A // A bit conservative because a store completion may not free up entries, 11222292SN/A // but hopefully avoids two store completions in one cycle from making 11232292SN/A // the CPU tick twice. 11243126Sktlim@umich.edu cpu->wakeCPU(); 11252292SN/A cpu->activityThisCycle(); 11262292SN/A 11272292SN/A if (store_idx == storeHead) { 11282292SN/A do { 11292292SN/A incrStIdx(storeHead); 11302292SN/A 11312292SN/A --stores; 11322292SN/A } while (storeQueue[storeHead].completed && 11332292SN/A storeHead != storeTail); 11342292SN/A 11352292SN/A iewStage->updateLSQNextCycle = true; 11362292SN/A } 11372292SN/A 11382329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 11392329SN/A "idx:%i\n", 11402329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 11412292SN/A 11429527SMatt.Horsnell@arm.com#if TRACING_ON 11439527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 11449527SMatt.Horsnell@arm.com storeQueue[store_idx].inst->storeTick = 11459527SMatt.Horsnell@arm.com curTick() - storeQueue[store_idx].inst->fetchTick; 11469527SMatt.Horsnell@arm.com } 11479527SMatt.Horsnell@arm.com#endif 11489527SMatt.Horsnell@arm.com 11492292SN/A if (isStalled() && 11502292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 11512292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 11522292SN/A "load idx:%i\n", 11532292SN/A stallingStoreIsn, stallingLoadIdx); 11542292SN/A stalled = false; 11552292SN/A stallingStoreIsn = 0; 11562292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 11572292SN/A } 11582316SN/A 11592316SN/A storeQueue[store_idx].inst->setCompleted(); 11602329SN/A 11618727Snilay@cs.wisc.edu if (needsTSO) { 11628727Snilay@cs.wisc.edu storeInFlight = false; 11638727Snilay@cs.wisc.edu } 11648727Snilay@cs.wisc.edu 11652329SN/A // Tell the checker we've completed this instruction. Some stores 11662329SN/A // may get reported twice to the checker, but the checker can 11672329SN/A // handle that case. 11682316SN/A if (cpu->checker) { 11692732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 11702316SN/A } 11712292SN/A} 11722292SN/A 11732292SN/Atemplate <class Impl> 11746974Stjones1@inf.ed.ac.ukbool 11756974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::sendStore(PacketPtr data_pkt) 11766974Stjones1@inf.ed.ac.uk{ 11778975Sandreas.hansson@arm.com if (!dcachePort->sendTimingReq(data_pkt)) { 11786974Stjones1@inf.ed.ac.uk // Need to handle becoming blocked on a store. 11796974Stjones1@inf.ed.ac.uk isStoreBlocked = true; 11806974Stjones1@inf.ed.ac.uk ++lsqCacheBlocked; 11816974Stjones1@inf.ed.ac.uk assert(retryPkt == NULL); 11826974Stjones1@inf.ed.ac.uk retryPkt = data_pkt; 11836974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 11846974Stjones1@inf.ed.ac.uk return false; 11856974Stjones1@inf.ed.ac.uk } 11866974Stjones1@inf.ed.ac.uk return true; 11876974Stjones1@inf.ed.ac.uk} 11886974Stjones1@inf.ed.ac.uk 11896974Stjones1@inf.ed.ac.uktemplate <class Impl> 11902693Sktlim@umich.eduvoid 11912693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 11922693Sktlim@umich.edu{ 11932698Sktlim@umich.edu if (isStoreBlocked) { 11944985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 11952698Sktlim@umich.edu assert(retryPkt != NULL); 11962693Sktlim@umich.edu 11978587Snilay@cs.wisc.edu LSQSenderState *state = 11988587Snilay@cs.wisc.edu dynamic_cast<LSQSenderState *>(retryPkt->senderState); 11998587Snilay@cs.wisc.edu 12008975Sandreas.hansson@arm.com if (dcachePort->sendTimingReq(retryPkt)) { 12016974Stjones1@inf.ed.ac.uk // Don't finish the store unless this is the last packet. 12028133SAli.Saidi@ARM.com if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 12038133SAli.Saidi@ARM.com state->pendingPacket == retryPkt) { 12048133SAli.Saidi@ARM.com state->pktToSend = false; 12056974Stjones1@inf.ed.ac.uk storePostSend(retryPkt); 12066974Stjones1@inf.ed.ac.uk } 12072699Sktlim@umich.edu retryPkt = NULL; 12082693Sktlim@umich.edu isStoreBlocked = false; 12096221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 12106974Stjones1@inf.ed.ac.uk 12116974Stjones1@inf.ed.ac.uk // Send any outstanding packet. 12126974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 12136974Stjones1@inf.ed.ac.uk assert(state->pendingPacket); 12146974Stjones1@inf.ed.ac.uk if (sendStore(state->pendingPacket)) { 12156974Stjones1@inf.ed.ac.uk storePostSend(state->pendingPacket); 12166974Stjones1@inf.ed.ac.uk } 12176974Stjones1@inf.ed.ac.uk } 12182693Sktlim@umich.edu } else { 12192693Sktlim@umich.edu // Still blocked! 12202727Sktlim@umich.edu ++lsqCacheBlocked; 12212907Sktlim@umich.edu lsq->setRetryTid(lsqID); 12222693Sktlim@umich.edu } 12232693Sktlim@umich.edu } else if (isLoadBlocked) { 12242693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 12252693Sktlim@umich.edu "no need to resend packet.\n"); 12262693Sktlim@umich.edu } else { 12272693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 12282693Sktlim@umich.edu } 12292693Sktlim@umich.edu} 12302693Sktlim@umich.edu 12312693Sktlim@umich.edutemplate <class Impl> 12322292SN/Ainline void 12339440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::incrStIdx(int &store_idx) const 12342292SN/A{ 12352292SN/A if (++store_idx >= SQEntries) 12362292SN/A store_idx = 0; 12372292SN/A} 12382292SN/A 12392292SN/Atemplate <class Impl> 12402292SN/Ainline void 12419440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::decrStIdx(int &store_idx) const 12422292SN/A{ 12432292SN/A if (--store_idx < 0) 12442292SN/A store_idx += SQEntries; 12452292SN/A} 12462292SN/A 12472292SN/Atemplate <class Impl> 12482292SN/Ainline void 12499440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::incrLdIdx(int &load_idx) const 12502292SN/A{ 12512292SN/A if (++load_idx >= LQEntries) 12522292SN/A load_idx = 0; 12532292SN/A} 12542292SN/A 12552292SN/Atemplate <class Impl> 12562292SN/Ainline void 12579440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::decrLdIdx(int &load_idx) const 12582292SN/A{ 12592292SN/A if (--load_idx < 0) 12602292SN/A load_idx += LQEntries; 12612292SN/A} 12622329SN/A 12632329SN/Atemplate <class Impl> 12642329SN/Avoid 12659440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::dumpInsts() const 12662329SN/A{ 12672329SN/A cprintf("Load store queue: Dumping instructions.\n"); 12682329SN/A cprintf("Load queue size: %i\n", loads); 12692329SN/A cprintf("Load queue: "); 12702329SN/A 12712329SN/A int load_idx = loadHead; 12722329SN/A 12732329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 12749440SAndreas.Sandberg@ARM.com const DynInstPtr &inst(loadQueue[load_idx]); 12759440SAndreas.Sandberg@ARM.com cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 12762329SN/A 12772329SN/A incrLdIdx(load_idx); 12782329SN/A } 12799440SAndreas.Sandberg@ARM.com cprintf("\n"); 12802329SN/A 12812329SN/A cprintf("Store queue size: %i\n", stores); 12822329SN/A cprintf("Store queue: "); 12832329SN/A 12842329SN/A int store_idx = storeHead; 12852329SN/A 12862329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 12879440SAndreas.Sandberg@ARM.com const DynInstPtr &inst(storeQueue[store_idx].inst); 12889440SAndreas.Sandberg@ARM.com cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 12892329SN/A 12902329SN/A incrStIdx(store_idx); 12912329SN/A } 12922329SN/A 12932329SN/A cprintf("\n"); 12942329SN/A} 12959944Smatt.horsnell@ARM.com 12969944Smatt.horsnell@ARM.com#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__ 1297