lsq_unit_impl.hh revision 9527
12292SN/A/* 29383SAli.Saidi@ARM.com * Copyright (c) 2010-2012 ARM Limited 37597Sminkyu.jeong@arm.com * All rights reserved 47597Sminkyu.jeong@arm.com * 57597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137597Sminkyu.jeong@arm.com * 142292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 152292SN/A * All rights reserved. 162292SN/A * 172292SN/A * Redistribution and use in source and binary forms, with or without 182292SN/A * modification, are permitted provided that the following conditions are 192292SN/A * met: redistributions of source code must retain the above copyright 202292SN/A * notice, this list of conditions and the following disclaimer; 212292SN/A * redistributions in binary form must reproduce the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer in the 232292SN/A * documentation and/or other materials provided with the distribution; 242292SN/A * neither the name of the copyright holders nor the names of its 252292SN/A * contributors may be used to endorse or promote products derived from 262292SN/A * this software without specific prior written permission. 272292SN/A * 282292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Kevin Lim 412689Sktlim@umich.edu * Korey Sewell 422292SN/A */ 432292SN/A 448591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 453326Sktlim@umich.edu#include "arch/locked_mem.hh" 468229Snate@binkert.org#include "base/str.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 492907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 502292SN/A#include "cpu/o3/lsq_unit.hh" 518232Snate@binkert.org#include "debug/Activity.hh" 528232Snate@binkert.org#include "debug/IEW.hh" 538232Snate@binkert.org#include "debug/LSQUnit.hh" 549527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 552722Sktlim@umich.edu#include "mem/packet.hh" 562669Sktlim@umich.edu#include "mem/request.hh" 572292SN/A 582669Sktlim@umich.edutemplate<class Impl> 592678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 602678Sktlim@umich.edu LSQUnit *lsq_ptr) 618581Ssteve.reinhardt@amd.com : Event(Default_Pri, AutoDelete), 628581Ssteve.reinhardt@amd.com inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 632292SN/A{ 642292SN/A} 652292SN/A 662669Sktlim@umich.edutemplate<class Impl> 672292SN/Avoid 682678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 692292SN/A{ 709444SAndreas.Sandberg@ARM.com assert(!lsqPtr->cpu->switchedOut()); 719444SAndreas.Sandberg@ARM.com 729444SAndreas.Sandberg@ARM.com lsqPtr->writeback(inst, pkt); 734319Sktlim@umich.edu 744319Sktlim@umich.edu if (pkt->senderState) 754319Sktlim@umich.edu delete pkt->senderState; 764319Sktlim@umich.edu 774319Sktlim@umich.edu delete pkt->req; 782678Sktlim@umich.edu delete pkt; 792678Sktlim@umich.edu} 802292SN/A 812678Sktlim@umich.edutemplate<class Impl> 822678Sktlim@umich.educonst char * 835336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 842678Sktlim@umich.edu{ 854873Sstever@eecs.umich.edu return "Store writeback"; 862678Sktlim@umich.edu} 872292SN/A 882678Sktlim@umich.edutemplate<class Impl> 892678Sktlim@umich.eduvoid 902678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 912678Sktlim@umich.edu{ 922678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 932678Sktlim@umich.edu DynInstPtr inst = state->inst; 947852SMatt.Horsnell@arm.com DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 957852SMatt.Horsnell@arm.com DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 962344SN/A 972678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 982678Sktlim@umich.edu 996974Stjones1@inf.ed.ac.uk // If this is a split access, wait until all packets are received. 1006974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1016974Stjones1@inf.ed.ac.uk delete pkt->req; 1026974Stjones1@inf.ed.ac.uk delete pkt; 1036974Stjones1@inf.ed.ac.uk return; 1046974Stjones1@inf.ed.ac.uk } 1056974Stjones1@inf.ed.ac.uk 1069444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 1079444SAndreas.Sandberg@ARM.com if (inst->isSquashed()) { 1082820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 1092678Sktlim@umich.edu } else { 1102678Sktlim@umich.edu if (!state->noWB) { 1116974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1126974Stjones1@inf.ed.ac.uk !state->isLoad) { 1136974Stjones1@inf.ed.ac.uk writeback(inst, pkt); 1146974Stjones1@inf.ed.ac.uk } else { 1156974Stjones1@inf.ed.ac.uk writeback(inst, state->mainPkt); 1166974Stjones1@inf.ed.ac.uk } 1172678Sktlim@umich.edu } 1182678Sktlim@umich.edu 1192678Sktlim@umich.edu if (inst->isStore()) { 1202678Sktlim@umich.edu completeStore(state->idx); 1212678Sktlim@umich.edu } 1222344SN/A } 1232307SN/A 1246974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1256974Stjones1@inf.ed.ac.uk delete state->mainPkt->req; 1266974Stjones1@inf.ed.ac.uk delete state->mainPkt; 1276974Stjones1@inf.ed.ac.uk } 1282678Sktlim@umich.edu delete state; 1294032Sktlim@umich.edu delete pkt->req; 1302678Sktlim@umich.edu delete pkt; 1312292SN/A} 1322292SN/A 1332292SN/Atemplate <class Impl> 1342292SN/ALSQUnit<Impl>::LSQUnit() 1358545Ssaidi@eecs.umich.edu : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 1362678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1378727Snilay@cs.wisc.edu loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) 1382292SN/A{ 1392292SN/A} 1402292SN/A 1412292SN/Atemplate<class Impl> 1422292SN/Avoid 1435529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1445529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1455529Snate@binkert.org unsigned id) 1462292SN/A{ 1474329Sktlim@umich.edu cpu = cpu_ptr; 1484329Sktlim@umich.edu iewStage = iew_ptr; 1494329Sktlim@umich.edu 1504329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1512292SN/A 1522907Sktlim@umich.edu lsq = lsq_ptr; 1532907Sktlim@umich.edu 1542292SN/A lsqID = id; 1552292SN/A 1562329SN/A // Add 1 for the sentinel entry (they are circular queues). 1572329SN/A LQEntries = maxLQEntries + 1; 1582329SN/A SQEntries = maxSQEntries + 1; 1592292SN/A 1602292SN/A loadQueue.resize(LQEntries); 1612292SN/A storeQueue.resize(SQEntries); 1622292SN/A 1638199SAli.Saidi@ARM.com depCheckShift = params->LSQDepCheckShift; 1648199SAli.Saidi@ARM.com checkLoads = params->LSQCheckLoads; 1659444SAndreas.Sandberg@ARM.com cachePorts = params->cachePorts; 1669444SAndreas.Sandberg@ARM.com needsTSO = params->needsTSO; 1679444SAndreas.Sandberg@ARM.com 1689444SAndreas.Sandberg@ARM.com resetState(); 1699444SAndreas.Sandberg@ARM.com} 1709444SAndreas.Sandberg@ARM.com 1719444SAndreas.Sandberg@ARM.com 1729444SAndreas.Sandberg@ARM.comtemplate<class Impl> 1739444SAndreas.Sandberg@ARM.comvoid 1749444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::resetState() 1759444SAndreas.Sandberg@ARM.com{ 1769444SAndreas.Sandberg@ARM.com loads = stores = storesToWB = 0; 1778199SAli.Saidi@ARM.com 1782292SN/A loadHead = loadTail = 0; 1792292SN/A 1802292SN/A storeHead = storeWBIdx = storeTail = 0; 1812292SN/A 1822292SN/A usedPorts = 0; 1832292SN/A 1843492Sktlim@umich.edu retryPkt = NULL; 1852329SN/A memDepViolator = NULL; 1862292SN/A 1872292SN/A blockedLoadSeqNum = 0; 1889444SAndreas.Sandberg@ARM.com 1899444SAndreas.Sandberg@ARM.com stalled = false; 1909444SAndreas.Sandberg@ARM.com isLoadBlocked = false; 1919444SAndreas.Sandberg@ARM.com loadBlockedHandled = false; 1929444SAndreas.Sandberg@ARM.com 1939444SAndreas.Sandberg@ARM.com cacheBlockMask = 0; 1942292SN/A} 1952292SN/A 1962292SN/Atemplate<class Impl> 1972292SN/Astd::string 1982292SN/ALSQUnit<Impl>::name() const 1992292SN/A{ 2002292SN/A if (Impl::MaxThreads == 1) { 2012292SN/A return iewStage->name() + ".lsq"; 2022292SN/A } else { 2038247Snate@binkert.org return iewStage->name() + ".lsq.thread" + to_string(lsqID); 2042292SN/A } 2052292SN/A} 2062292SN/A 2072292SN/Atemplate<class Impl> 2082292SN/Avoid 2092727Sktlim@umich.eduLSQUnit<Impl>::regStats() 2102727Sktlim@umich.edu{ 2112727Sktlim@umich.edu lsqForwLoads 2122727Sktlim@umich.edu .name(name() + ".forwLoads") 2132727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 2142727Sktlim@umich.edu 2152727Sktlim@umich.edu invAddrLoads 2162727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2172727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2182727Sktlim@umich.edu 2192727Sktlim@umich.edu lsqSquashedLoads 2202727Sktlim@umich.edu .name(name() + ".squashedLoads") 2212727Sktlim@umich.edu .desc("Number of loads squashed"); 2222727Sktlim@umich.edu 2232727Sktlim@umich.edu lsqIgnoredResponses 2242727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2252727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2262727Sktlim@umich.edu 2272361SN/A lsqMemOrderViolation 2282361SN/A .name(name() + ".memOrderViolation") 2292361SN/A .desc("Number of memory ordering violations"); 2302361SN/A 2312727Sktlim@umich.edu lsqSquashedStores 2322727Sktlim@umich.edu .name(name() + ".squashedStores") 2332727Sktlim@umich.edu .desc("Number of stores squashed"); 2342727Sktlim@umich.edu 2352727Sktlim@umich.edu invAddrSwpfs 2362727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2372727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2382727Sktlim@umich.edu 2392727Sktlim@umich.edu lsqBlockedLoads 2402727Sktlim@umich.edu .name(name() + ".blockedLoads") 2412727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2422727Sktlim@umich.edu 2432727Sktlim@umich.edu lsqRescheduledLoads 2442727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2452727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2462727Sktlim@umich.edu 2472727Sktlim@umich.edu lsqCacheBlocked 2482727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2492727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2502727Sktlim@umich.edu} 2512727Sktlim@umich.edu 2522727Sktlim@umich.edutemplate<class Impl> 2532727Sktlim@umich.eduvoid 2548922Swilliam.wang@arm.comLSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 2554329Sktlim@umich.edu{ 2564329Sktlim@umich.edu dcachePort = dcache_port; 2574329Sktlim@umich.edu} 2584329Sktlim@umich.edu 2594329Sktlim@umich.edutemplate<class Impl> 2604329Sktlim@umich.eduvoid 2612292SN/ALSQUnit<Impl>::clearLQ() 2622292SN/A{ 2632292SN/A loadQueue.clear(); 2642292SN/A} 2652292SN/A 2662292SN/Atemplate<class Impl> 2672292SN/Avoid 2682292SN/ALSQUnit<Impl>::clearSQ() 2692292SN/A{ 2702292SN/A storeQueue.clear(); 2712292SN/A} 2722292SN/A 2732292SN/Atemplate<class Impl> 2742292SN/Avoid 2759444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::drainSanityCheck() const 2762307SN/A{ 2779444SAndreas.Sandberg@ARM.com for (int i = 0; i < loadQueue.size(); ++i) 2782367SN/A assert(!loadQueue[i]); 2792307SN/A 2802329SN/A assert(storesToWB == 0); 2819444SAndreas.Sandberg@ARM.com assert(!retryPkt); 2822307SN/A} 2832307SN/A 2842307SN/Atemplate<class Impl> 2852307SN/Avoid 2862307SN/ALSQUnit<Impl>::takeOverFrom() 2872307SN/A{ 2889444SAndreas.Sandberg@ARM.com resetState(); 2892307SN/A} 2902307SN/A 2912307SN/Atemplate<class Impl> 2922307SN/Avoid 2932292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2942292SN/A{ 2952329SN/A unsigned size_plus_sentinel = size + 1; 2962329SN/A assert(size_plus_sentinel >= LQEntries); 2972292SN/A 2982329SN/A if (size_plus_sentinel > LQEntries) { 2992329SN/A while (size_plus_sentinel > loadQueue.size()) { 3002292SN/A DynInstPtr dummy; 3012292SN/A loadQueue.push_back(dummy); 3022292SN/A LQEntries++; 3032292SN/A } 3042292SN/A } else { 3052329SN/A LQEntries = size_plus_sentinel; 3062292SN/A } 3072292SN/A 3082292SN/A} 3092292SN/A 3102292SN/Atemplate<class Impl> 3112292SN/Avoid 3122292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3132292SN/A{ 3142329SN/A unsigned size_plus_sentinel = size + 1; 3152329SN/A if (size_plus_sentinel > SQEntries) { 3162329SN/A while (size_plus_sentinel > storeQueue.size()) { 3172292SN/A SQEntry dummy; 3182292SN/A storeQueue.push_back(dummy); 3192292SN/A SQEntries++; 3202292SN/A } 3212292SN/A } else { 3222329SN/A SQEntries = size_plus_sentinel; 3232292SN/A } 3242292SN/A} 3252292SN/A 3262292SN/Atemplate <class Impl> 3272292SN/Avoid 3282292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3292292SN/A{ 3302292SN/A assert(inst->isMemRef()); 3312292SN/A 3322292SN/A assert(inst->isLoad() || inst->isStore()); 3332292SN/A 3342292SN/A if (inst->isLoad()) { 3352292SN/A insertLoad(inst); 3362292SN/A } else { 3372292SN/A insertStore(inst); 3382292SN/A } 3392292SN/A 3402292SN/A inst->setInLSQ(); 3412292SN/A} 3422292SN/A 3432292SN/Atemplate <class Impl> 3442292SN/Avoid 3452292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3462292SN/A{ 3472329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3482329SN/A assert(loads < LQEntries); 3492292SN/A 3507720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3517720Sgblack@eecs.umich.edu load_inst->pcState(), loadTail, load_inst->seqNum); 3522292SN/A 3532292SN/A load_inst->lqIdx = loadTail; 3542292SN/A 3552292SN/A if (stores == 0) { 3562292SN/A load_inst->sqIdx = -1; 3572292SN/A } else { 3582292SN/A load_inst->sqIdx = storeTail; 3592292SN/A } 3602292SN/A 3612292SN/A loadQueue[loadTail] = load_inst; 3622292SN/A 3632292SN/A incrLdIdx(loadTail); 3642292SN/A 3652292SN/A ++loads; 3662292SN/A} 3672292SN/A 3682292SN/Atemplate <class Impl> 3692292SN/Avoid 3702292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3712292SN/A{ 3722292SN/A // Make sure it is not full before inserting an instruction. 3732292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3742292SN/A assert(stores < SQEntries); 3752292SN/A 3767720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3777720Sgblack@eecs.umich.edu store_inst->pcState(), storeTail, store_inst->seqNum); 3782292SN/A 3792292SN/A store_inst->sqIdx = storeTail; 3802292SN/A store_inst->lqIdx = loadTail; 3812292SN/A 3822292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3832292SN/A 3842292SN/A incrStIdx(storeTail); 3852292SN/A 3862292SN/A ++stores; 3872292SN/A} 3882292SN/A 3892292SN/Atemplate <class Impl> 3902292SN/Atypename Impl::DynInstPtr 3912292SN/ALSQUnit<Impl>::getMemDepViolator() 3922292SN/A{ 3932292SN/A DynInstPtr temp = memDepViolator; 3942292SN/A 3952292SN/A memDepViolator = NULL; 3962292SN/A 3972292SN/A return temp; 3982292SN/A} 3992292SN/A 4002292SN/Atemplate <class Impl> 4012292SN/Aunsigned 4022292SN/ALSQUnit<Impl>::numFreeEntries() 4032292SN/A{ 4042292SN/A unsigned free_lq_entries = LQEntries - loads; 4052292SN/A unsigned free_sq_entries = SQEntries - stores; 4062292SN/A 4072292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4082292SN/A // empty/full conditions. Subtract 1 from the free entries. 4092292SN/A if (free_lq_entries < free_sq_entries) { 4102292SN/A return free_lq_entries - 1; 4112292SN/A } else { 4122292SN/A return free_sq_entries - 1; 4132292SN/A } 4142292SN/A} 4152292SN/A 4162292SN/Atemplate <class Impl> 4178545Ssaidi@eecs.umich.eduvoid 4188545Ssaidi@eecs.umich.eduLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 4198545Ssaidi@eecs.umich.edu{ 4208545Ssaidi@eecs.umich.edu int load_idx = loadHead; 4218545Ssaidi@eecs.umich.edu 4228545Ssaidi@eecs.umich.edu if (!cacheBlockMask) { 4238545Ssaidi@eecs.umich.edu assert(dcachePort); 4248545Ssaidi@eecs.umich.edu Addr bs = dcachePort->peerBlockSize(); 4258545Ssaidi@eecs.umich.edu 4268545Ssaidi@eecs.umich.edu // Make sure we actually got a size 4278545Ssaidi@eecs.umich.edu assert(bs != 0); 4288545Ssaidi@eecs.umich.edu 4298545Ssaidi@eecs.umich.edu cacheBlockMask = ~(bs - 1); 4308545Ssaidi@eecs.umich.edu } 4318545Ssaidi@eecs.umich.edu 4329383SAli.Saidi@ARM.com // Unlock the cpu-local monitor when the CPU sees a snoop to a locked 4339383SAli.Saidi@ARM.com // address. The CPU can speculatively execute a LL operation after a pending 4349383SAli.Saidi@ARM.com // SC operation in the pipeline and that can make the cache monitor the CPU 4359383SAli.Saidi@ARM.com // is connected to valid while it really shouldn't be. 4369383SAli.Saidi@ARM.com for (int x = 0; x < cpu->numActiveThreads(); x++) { 4379383SAli.Saidi@ARM.com ThreadContext *tc = cpu->getContext(x); 4389383SAli.Saidi@ARM.com bool no_squash = cpu->thread[x]->noSquashFromTC; 4399383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = true; 4409383SAli.Saidi@ARM.com TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 4419383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = no_squash; 4429383SAli.Saidi@ARM.com } 4439383SAli.Saidi@ARM.com 4448545Ssaidi@eecs.umich.edu // If this is the only load in the LSQ we don't care 4458545Ssaidi@eecs.umich.edu if (load_idx == loadTail) 4468545Ssaidi@eecs.umich.edu return; 4478545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4488545Ssaidi@eecs.umich.edu 4498545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 4508545Ssaidi@eecs.umich.edu Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 4518545Ssaidi@eecs.umich.edu while (load_idx != loadTail) { 4528545Ssaidi@eecs.umich.edu DynInstPtr ld_inst = loadQueue[load_idx]; 4538545Ssaidi@eecs.umich.edu 4549046SAli.Saidi@ARM.com if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 4558545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4568545Ssaidi@eecs.umich.edu continue; 4578545Ssaidi@eecs.umich.edu } 4588545Ssaidi@eecs.umich.edu 4598545Ssaidi@eecs.umich.edu Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 4608545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 4618545Ssaidi@eecs.umich.edu ld_inst->seqNum, load_addr, invalidate_addr); 4628545Ssaidi@eecs.umich.edu 4638545Ssaidi@eecs.umich.edu if (load_addr == invalidate_addr) { 4649046SAli.Saidi@ARM.com if (ld_inst->possibleLoadViolation()) { 4658545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 4668545Ssaidi@eecs.umich.edu ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum); 4678545Ssaidi@eecs.umich.edu 4688545Ssaidi@eecs.umich.edu // Mark the load for re-execution 4698545Ssaidi@eecs.umich.edu ld_inst->fault = new ReExec; 4708545Ssaidi@eecs.umich.edu } else { 4718545Ssaidi@eecs.umich.edu // If a older load checks this and it's true 4728545Ssaidi@eecs.umich.edu // then we might have missed the snoop 4738545Ssaidi@eecs.umich.edu // in which case we need to invalidate to be sure 4749046SAli.Saidi@ARM.com ld_inst->hitExternalSnoop(true); 4758545Ssaidi@eecs.umich.edu } 4768545Ssaidi@eecs.umich.edu } 4778545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4788545Ssaidi@eecs.umich.edu } 4798545Ssaidi@eecs.umich.edu return; 4808545Ssaidi@eecs.umich.edu} 4818545Ssaidi@eecs.umich.edu 4828545Ssaidi@eecs.umich.edutemplate <class Impl> 4832292SN/AFault 4848199SAli.Saidi@ARM.comLSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 4858199SAli.Saidi@ARM.com{ 4868199SAli.Saidi@ARM.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 4878199SAli.Saidi@ARM.com Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 4888199SAli.Saidi@ARM.com 4898199SAli.Saidi@ARM.com /** @todo in theory you only need to check an instruction that has executed 4908199SAli.Saidi@ARM.com * however, there isn't a good way in the pipeline at the moment to check 4918199SAli.Saidi@ARM.com * all instructions that will execute before the store writes back. Thus, 4928199SAli.Saidi@ARM.com * like the implementation that came before it, we're overly conservative. 4938199SAli.Saidi@ARM.com */ 4948199SAli.Saidi@ARM.com while (load_idx != loadTail) { 4958199SAli.Saidi@ARM.com DynInstPtr ld_inst = loadQueue[load_idx]; 4969046SAli.Saidi@ARM.com if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 4978199SAli.Saidi@ARM.com incrLdIdx(load_idx); 4988199SAli.Saidi@ARM.com continue; 4998199SAli.Saidi@ARM.com } 5008199SAli.Saidi@ARM.com 5018199SAli.Saidi@ARM.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 5028199SAli.Saidi@ARM.com Addr ld_eff_addr2 = 5038199SAli.Saidi@ARM.com (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 5048199SAli.Saidi@ARM.com 5058272SAli.Saidi@ARM.com if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 5068545Ssaidi@eecs.umich.edu if (inst->isLoad()) { 5078545Ssaidi@eecs.umich.edu // If this load is to the same block as an external snoop 5088545Ssaidi@eecs.umich.edu // invalidate that we've observed then the load needs to be 5098545Ssaidi@eecs.umich.edu // squashed as it could have newer data 5109046SAli.Saidi@ARM.com if (ld_inst->hitExternalSnoop()) { 5118545Ssaidi@eecs.umich.edu if (!memDepViolator || 5128545Ssaidi@eecs.umich.edu ld_inst->seqNum < memDepViolator->seqNum) { 5138545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 5148592Sgblack@eecs.umich.edu "and [sn:%lli] at address %#x\n", 5158592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5168545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5178199SAli.Saidi@ARM.com 5188545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5198199SAli.Saidi@ARM.com 5208591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault( 5218591Sgblack@eecs.umich.edu "Detected fault with inst [sn:%lli] and " 5228591Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5238591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5248545Ssaidi@eecs.umich.edu } 5258545Ssaidi@eecs.umich.edu } 5268199SAli.Saidi@ARM.com 5278545Ssaidi@eecs.umich.edu // Otherwise, mark the load has a possible load violation 5288545Ssaidi@eecs.umich.edu // and if we see a snoop before it's commited, we need to squash 5299046SAli.Saidi@ARM.com ld_inst->possibleLoadViolation(true); 5308545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 5318545Ssaidi@eecs.umich.edu " between instructions [sn:%lli] and [sn:%lli]\n", 5328545Ssaidi@eecs.umich.edu inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 5338545Ssaidi@eecs.umich.edu } else { 5348545Ssaidi@eecs.umich.edu // A load/store incorrectly passed this store. 5358545Ssaidi@eecs.umich.edu // Check if we already have a violator, or if it's newer 5368545Ssaidi@eecs.umich.edu // squash and refetch. 5378545Ssaidi@eecs.umich.edu if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5388545Ssaidi@eecs.umich.edu break; 5398545Ssaidi@eecs.umich.edu 5408592Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 5418592Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5428592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5438545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5448545Ssaidi@eecs.umich.edu 5458545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5468545Ssaidi@eecs.umich.edu 5478591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault("Detected fault with " 5488591Sgblack@eecs.umich.edu "inst [sn:%lli] and [sn:%lli] at address %#x\n", 5498591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5508545Ssaidi@eecs.umich.edu } 5518199SAli.Saidi@ARM.com } 5528199SAli.Saidi@ARM.com 5538199SAli.Saidi@ARM.com incrLdIdx(load_idx); 5548199SAli.Saidi@ARM.com } 5558199SAli.Saidi@ARM.com return NoFault; 5568199SAli.Saidi@ARM.com} 5578199SAli.Saidi@ARM.com 5588199SAli.Saidi@ARM.com 5598199SAli.Saidi@ARM.com 5608199SAli.Saidi@ARM.com 5618199SAli.Saidi@ARM.comtemplate <class Impl> 5628199SAli.Saidi@ARM.comFault 5632292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 5642292SN/A{ 5654032Sktlim@umich.edu using namespace TheISA; 5662292SN/A // Execute a specific load. 5672292SN/A Fault load_fault = NoFault; 5682292SN/A 5697720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 5707944SGiacomo.Gabrielli@arm.com inst->pcState(), inst->seqNum); 5712292SN/A 5724032Sktlim@umich.edu assert(!inst->isSquashed()); 5734032Sktlim@umich.edu 5742669Sktlim@umich.edu load_fault = inst->initiateAcc(); 5752292SN/A 5767944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 5777944SGiacomo.Gabrielli@arm.com load_fault == NoFault) 5787944SGiacomo.Gabrielli@arm.com return load_fault; 5797944SGiacomo.Gabrielli@arm.com 5807597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 5817597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 5827597Sminkyu.jeong@arm.com if (load_fault != NoFault || inst->readPredicate() == false) { 5832329SN/A // Send this instruction to commit, also make sure iew stage 5842329SN/A // realizes there is activity. 5852367SN/A // Mark it as executed unless it is an uncached load that 5862367SN/A // needs to hit the head of commit. 5877848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 5887848SAli.Saidi@ARM.com inst->forwardOldRegs(); 5897600Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 5907600Sminkyu.jeong@arm.com inst->seqNum, 5917600Sminkyu.jeong@arm.com (load_fault != NoFault ? "fault" : "predication")); 5924032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 5933731Sktlim@umich.edu inst->isAtCommit()) { 5942367SN/A inst->setExecuted(); 5952367SN/A } 5962292SN/A iewStage->instToCommit(inst); 5972292SN/A iewStage->activityThisCycle(); 5984032Sktlim@umich.edu } else if (!loadBlocked()) { 5999046SAli.Saidi@ARM.com assert(inst->effAddrValid()); 6004032Sktlim@umich.edu int load_idx = inst->lqIdx; 6014032Sktlim@umich.edu incrLdIdx(load_idx); 6024032Sktlim@umich.edu 6038199SAli.Saidi@ARM.com if (checkLoads) 6048199SAli.Saidi@ARM.com return checkViolations(load_idx, inst); 6052292SN/A } 6062292SN/A 6072292SN/A return load_fault; 6082292SN/A} 6092292SN/A 6102292SN/Atemplate <class Impl> 6112292SN/AFault 6122292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 6132292SN/A{ 6142292SN/A using namespace TheISA; 6152292SN/A // Make sure that a store exists. 6162292SN/A assert(stores != 0); 6172292SN/A 6182292SN/A int store_idx = store_inst->sqIdx; 6192292SN/A 6207720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 6217720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6222292SN/A 6234032Sktlim@umich.edu assert(!store_inst->isSquashed()); 6244032Sktlim@umich.edu 6252292SN/A // Check the recently completed loads to see if any match this store's 6262292SN/A // address. If so, then we have a memory ordering violation. 6272292SN/A int load_idx = store_inst->lqIdx; 6282292SN/A 6292292SN/A Fault store_fault = store_inst->initiateAcc(); 6302292SN/A 6317944SGiacomo.Gabrielli@arm.com if (store_inst->isTranslationDelayed() && 6327944SGiacomo.Gabrielli@arm.com store_fault == NoFault) 6337944SGiacomo.Gabrielli@arm.com return store_fault; 6347944SGiacomo.Gabrielli@arm.com 6357848SAli.Saidi@ARM.com if (store_inst->readPredicate() == false) 6367848SAli.Saidi@ARM.com store_inst->forwardOldRegs(); 6377848SAli.Saidi@ARM.com 6382329SN/A if (storeQueue[store_idx].size == 0) { 6397782Sminkyu.jeong@arm.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 6407720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6412292SN/A 6422292SN/A return store_fault; 6437782Sminkyu.jeong@arm.com } else if (store_inst->readPredicate() == false) { 6447782Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 6457782Sminkyu.jeong@arm.com store_inst->seqNum); 6467782Sminkyu.jeong@arm.com return store_fault; 6472292SN/A } 6482292SN/A 6492292SN/A assert(store_fault == NoFault); 6502292SN/A 6512336SN/A if (store_inst->isStoreConditional()) { 6522336SN/A // Store conditionals need to set themselves as able to 6532336SN/A // writeback if we haven't had a fault by here. 6542329SN/A storeQueue[store_idx].canWB = true; 6552292SN/A 6562329SN/A ++storesToWB; 6572292SN/A } 6582292SN/A 6598199SAli.Saidi@ARM.com return checkViolations(load_idx, store_inst); 6602292SN/A 6612292SN/A} 6622292SN/A 6632292SN/Atemplate <class Impl> 6642292SN/Avoid 6652292SN/ALSQUnit<Impl>::commitLoad() 6662292SN/A{ 6672292SN/A assert(loadQueue[loadHead]); 6682292SN/A 6697720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 6707720Sgblack@eecs.umich.edu loadQueue[loadHead]->pcState()); 6712292SN/A 6722292SN/A loadQueue[loadHead] = NULL; 6732292SN/A 6742292SN/A incrLdIdx(loadHead); 6752292SN/A 6762292SN/A --loads; 6772292SN/A} 6782292SN/A 6792292SN/Atemplate <class Impl> 6802292SN/Avoid 6812292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 6822292SN/A{ 6832292SN/A assert(loads == 0 || loadQueue[loadHead]); 6842292SN/A 6852292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 6862292SN/A commitLoad(); 6872292SN/A } 6882292SN/A} 6892292SN/A 6902292SN/Atemplate <class Impl> 6912292SN/Avoid 6922292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 6932292SN/A{ 6942292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 6952292SN/A 6962292SN/A int store_idx = storeHead; 6972292SN/A 6982292SN/A while (store_idx != storeTail) { 6992292SN/A assert(storeQueue[store_idx].inst); 7002329SN/A // Mark any stores that are now committed and have not yet 7012329SN/A // been marked as able to write back. 7022292SN/A if (!storeQueue[store_idx].canWB) { 7032292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 7042292SN/A break; 7052292SN/A } 7062292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 7077720Sgblack@eecs.umich.edu "%s [sn:%lli]\n", 7087720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 7092292SN/A storeQueue[store_idx].inst->seqNum); 7102292SN/A 7112292SN/A storeQueue[store_idx].canWB = true; 7122292SN/A 7132292SN/A ++storesToWB; 7142292SN/A } 7152292SN/A 7162292SN/A incrStIdx(store_idx); 7172292SN/A } 7182292SN/A} 7192292SN/A 7202292SN/Atemplate <class Impl> 7212292SN/Avoid 7226974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::writebackPendingStore() 7236974Stjones1@inf.ed.ac.uk{ 7246974Stjones1@inf.ed.ac.uk if (hasPendingPkt) { 7256974Stjones1@inf.ed.ac.uk assert(pendingPkt != NULL); 7266974Stjones1@inf.ed.ac.uk 7276974Stjones1@inf.ed.ac.uk // If the cache is blocked, this will store the packet for retry. 7286974Stjones1@inf.ed.ac.uk if (sendStore(pendingPkt)) { 7296974Stjones1@inf.ed.ac.uk storePostSend(pendingPkt); 7306974Stjones1@inf.ed.ac.uk } 7316974Stjones1@inf.ed.ac.uk pendingPkt = NULL; 7326974Stjones1@inf.ed.ac.uk hasPendingPkt = false; 7336974Stjones1@inf.ed.ac.uk } 7346974Stjones1@inf.ed.ac.uk} 7356974Stjones1@inf.ed.ac.uk 7366974Stjones1@inf.ed.ac.uktemplate <class Impl> 7376974Stjones1@inf.ed.ac.ukvoid 7382292SN/ALSQUnit<Impl>::writebackStores() 7392292SN/A{ 7406974Stjones1@inf.ed.ac.uk // First writeback the second packet from any split store that didn't 7416974Stjones1@inf.ed.ac.uk // complete last cycle because there weren't enough cache ports available. 7426974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 7436974Stjones1@inf.ed.ac.uk writebackPendingStore(); 7446974Stjones1@inf.ed.ac.uk } 7456974Stjones1@inf.ed.ac.uk 7462292SN/A while (storesToWB > 0 && 7472292SN/A storeWBIdx != storeTail && 7482292SN/A storeQueue[storeWBIdx].inst && 7492292SN/A storeQueue[storeWBIdx].canWB && 7508727Snilay@cs.wisc.edu ((!needsTSO) || (!storeInFlight)) && 7512292SN/A usedPorts < cachePorts) { 7522292SN/A 7532907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 7542678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 7552678Sktlim@umich.edu " is blocked!\n"); 7562678Sktlim@umich.edu break; 7572678Sktlim@umich.edu } 7582678Sktlim@umich.edu 7592329SN/A // Store didn't write any data so no need to write it back to 7602329SN/A // memory. 7612292SN/A if (storeQueue[storeWBIdx].size == 0) { 7622292SN/A completeStore(storeWBIdx); 7632292SN/A 7642292SN/A incrStIdx(storeWBIdx); 7652292SN/A 7662292SN/A continue; 7672292SN/A } 7682678Sktlim@umich.edu 7692292SN/A ++usedPorts; 7702292SN/A 7712292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 7722292SN/A incrStIdx(storeWBIdx); 7732292SN/A 7742292SN/A continue; 7752292SN/A } 7762292SN/A 7772292SN/A assert(storeQueue[storeWBIdx].req); 7782292SN/A assert(!storeQueue[storeWBIdx].committed); 7792292SN/A 7806974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 7816974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqLow); 7826974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqHigh); 7836974Stjones1@inf.ed.ac.uk } 7846974Stjones1@inf.ed.ac.uk 7852669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 7862669Sktlim@umich.edu 7872669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 7888481Sgblack@eecs.umich.edu RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 7898481Sgblack@eecs.umich.edu RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 7908481Sgblack@eecs.umich.edu 7912292SN/A storeQueue[storeWBIdx].committed = true; 7922292SN/A 7932669Sktlim@umich.edu assert(!inst->memData); 7942669Sktlim@umich.edu inst->memData = new uint8_t[64]; 7953772Sgblack@eecs.umich.edu 7964326Sgblack@eecs.umich.edu memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 7972669Sktlim@umich.edu 7984878Sstever@eecs.umich.edu MemCmd command = 7994878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 8006102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 8016974Stjones1@inf.ed.ac.uk PacketPtr data_pkt; 8026974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 8032292SN/A 8042678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 8052678Sktlim@umich.edu state->isLoad = false; 8062678Sktlim@umich.edu state->idx = storeWBIdx; 8072678Sktlim@umich.edu state->inst = inst; 8086974Stjones1@inf.ed.ac.uk 8096974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 8106974Stjones1@inf.ed.ac.uk 8116974Stjones1@inf.ed.ac.uk // Build a single data packet if the store isn't split. 8128949Sandreas.hansson@arm.com data_pkt = new Packet(req, command); 8136974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8146974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8156974Stjones1@inf.ed.ac.uk } else { 8166974Stjones1@inf.ed.ac.uk // Create two packets if the store is split in two. 8178949Sandreas.hansson@arm.com data_pkt = new Packet(sreqLow, command); 8188949Sandreas.hansson@arm.com snd_data_pkt = new Packet(sreqHigh, command); 8196974Stjones1@inf.ed.ac.uk 8206974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8216974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 8226974Stjones1@inf.ed.ac.uk 8236974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8246974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 8256974Stjones1@inf.ed.ac.uk 8266974Stjones1@inf.ed.ac.uk state->isSplit = true; 8276974Stjones1@inf.ed.ac.uk state->outstanding = 2; 8286974Stjones1@inf.ed.ac.uk 8296974Stjones1@inf.ed.ac.uk // Can delete the main request now. 8306974Stjones1@inf.ed.ac.uk delete req; 8316974Stjones1@inf.ed.ac.uk req = sreqLow; 8326974Stjones1@inf.ed.ac.uk } 8332678Sktlim@umich.edu 8347720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 8352292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 8367720Sgblack@eecs.umich.edu storeWBIdx, inst->pcState(), 8373797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 8383221Sktlim@umich.edu inst->seqNum); 8392292SN/A 8402693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 8414350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 8426974Stjones1@inf.ed.ac.uk assert(!storeQueue[storeWBIdx].isSplit); 8433326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 8443326Sktlim@umich.edu // misc regs normally updates the result, but this is not 8453326Sktlim@umich.edu // the desired behavior when handling store conditionals. 8469046SAli.Saidi@ARM.com inst->recordResult(false); 8473326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 8489046SAli.Saidi@ARM.com inst->recordResult(true); 8493326Sktlim@umich.edu 8503326Sktlim@umich.edu if (!success) { 8513326Sktlim@umich.edu // Instantly complete this store. 8523326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 8533326Sktlim@umich.edu "Instantly completing it.\n", 8543326Sktlim@umich.edu inst->seqNum); 8553326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 8567823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick() + 1); 8578887Sgeoffrey.blake@arm.com if (cpu->checker) { 8588887Sgeoffrey.blake@arm.com // Make sure to set the LLSC data for verification 8598887Sgeoffrey.blake@arm.com // if checker is loaded 8608887Sgeoffrey.blake@arm.com inst->reqToVerify->setExtraData(0); 8618887Sgeoffrey.blake@arm.com inst->completeAcc(data_pkt); 8628887Sgeoffrey.blake@arm.com } 8633326Sktlim@umich.edu completeStore(storeWBIdx); 8643326Sktlim@umich.edu incrStIdx(storeWBIdx); 8653326Sktlim@umich.edu continue; 8662693Sktlim@umich.edu } 8672693Sktlim@umich.edu } else { 8682693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 8692693Sktlim@umich.edu state->noWB = true; 8702693Sktlim@umich.edu } 8712693Sktlim@umich.edu 8728481Sgblack@eecs.umich.edu bool split = 8738481Sgblack@eecs.umich.edu TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 8748481Sgblack@eecs.umich.edu 8758481Sgblack@eecs.umich.edu ThreadContext *thread = cpu->tcBase(lsqID); 8768481Sgblack@eecs.umich.edu 8778481Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 8788481Sgblack@eecs.umich.edu assert(!inst->isStoreConditional()); 8798481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, data_pkt); 8808481Sgblack@eecs.umich.edu delete data_pkt; 8818481Sgblack@eecs.umich.edu if (split) { 8828481Sgblack@eecs.umich.edu assert(snd_data_pkt->req->isMmappedIpr()); 8838481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, snd_data_pkt); 8848481Sgblack@eecs.umich.edu delete snd_data_pkt; 8858481Sgblack@eecs.umich.edu delete sreqLow; 8868481Sgblack@eecs.umich.edu delete sreqHigh; 8878481Sgblack@eecs.umich.edu } 8888481Sgblack@eecs.umich.edu delete state; 8898481Sgblack@eecs.umich.edu delete req; 8908481Sgblack@eecs.umich.edu completeStore(storeWBIdx); 8918481Sgblack@eecs.umich.edu incrStIdx(storeWBIdx); 8928481Sgblack@eecs.umich.edu } else if (!sendStore(data_pkt)) { 8934032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 8943221Sktlim@umich.edu "retry later\n", 8953221Sktlim@umich.edu inst->seqNum); 8966974Stjones1@inf.ed.ac.uk 8976974Stjones1@inf.ed.ac.uk // Need to store the second packet, if split. 8988481Sgblack@eecs.umich.edu if (split) { 8996974Stjones1@inf.ed.ac.uk state->pktToSend = true; 9006974Stjones1@inf.ed.ac.uk state->pendingPacket = snd_data_pkt; 9016974Stjones1@inf.ed.ac.uk } 9022669Sktlim@umich.edu } else { 9036974Stjones1@inf.ed.ac.uk 9046974Stjones1@inf.ed.ac.uk // If split, try to send the second packet too 9058481Sgblack@eecs.umich.edu if (split) { 9066974Stjones1@inf.ed.ac.uk assert(snd_data_pkt); 9076974Stjones1@inf.ed.ac.uk 9086974Stjones1@inf.ed.ac.uk // Ensure there are enough ports to use. 9096974Stjones1@inf.ed.ac.uk if (usedPorts < cachePorts) { 9106974Stjones1@inf.ed.ac.uk ++usedPorts; 9116974Stjones1@inf.ed.ac.uk if (sendStore(snd_data_pkt)) { 9126974Stjones1@inf.ed.ac.uk storePostSend(snd_data_pkt); 9136974Stjones1@inf.ed.ac.uk } else { 9146974Stjones1@inf.ed.ac.uk DPRINTF(IEW, "D-Cache became blocked when writing" 9156974Stjones1@inf.ed.ac.uk " [sn:%lli] second packet, will retry later\n", 9166974Stjones1@inf.ed.ac.uk inst->seqNum); 9176974Stjones1@inf.ed.ac.uk } 9186974Stjones1@inf.ed.ac.uk } else { 9196974Stjones1@inf.ed.ac.uk 9206974Stjones1@inf.ed.ac.uk // Store the packet for when there's free ports. 9216974Stjones1@inf.ed.ac.uk assert(pendingPkt == NULL); 9226974Stjones1@inf.ed.ac.uk pendingPkt = snd_data_pkt; 9236974Stjones1@inf.ed.ac.uk hasPendingPkt = true; 9246974Stjones1@inf.ed.ac.uk } 9256974Stjones1@inf.ed.ac.uk } else { 9266974Stjones1@inf.ed.ac.uk 9276974Stjones1@inf.ed.ac.uk // Not a split store. 9286974Stjones1@inf.ed.ac.uk storePostSend(data_pkt); 9296974Stjones1@inf.ed.ac.uk } 9302292SN/A } 9312292SN/A } 9322292SN/A 9332292SN/A // Not sure this should set it to 0. 9342292SN/A usedPorts = 0; 9352292SN/A 9362292SN/A assert(stores >= 0 && storesToWB >= 0); 9372292SN/A} 9382292SN/A 9392292SN/A/*template <class Impl> 9402292SN/Avoid 9412292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 9422292SN/A{ 9432292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 9442292SN/A mshrSeqNums.end(), 9452292SN/A seqNum); 9462292SN/A 9472292SN/A if (mshr_it != mshrSeqNums.end()) { 9482292SN/A mshrSeqNums.erase(mshr_it); 9492292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 9502292SN/A } 9512292SN/A}*/ 9522292SN/A 9532292SN/Atemplate <class Impl> 9542292SN/Avoid 9552292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 9562292SN/A{ 9572292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 9582329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 9592292SN/A 9602292SN/A int load_idx = loadTail; 9612292SN/A decrLdIdx(load_idx); 9622292SN/A 9632292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 9647720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 9652292SN/A "[sn:%lli]\n", 9667720Sgblack@eecs.umich.edu loadQueue[load_idx]->pcState(), 9672292SN/A loadQueue[load_idx]->seqNum); 9682292SN/A 9692292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 9702292SN/A stalled = false; 9712292SN/A stallingStoreIsn = 0; 9722292SN/A stallingLoadIdx = 0; 9732292SN/A } 9742292SN/A 9752329SN/A // Clear the smart pointer to make sure it is decremented. 9762731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 9772292SN/A loadQueue[load_idx] = NULL; 9782292SN/A --loads; 9792292SN/A 9802292SN/A // Inefficient! 9812292SN/A loadTail = load_idx; 9822292SN/A 9832292SN/A decrLdIdx(load_idx); 9842727Sktlim@umich.edu ++lsqSquashedLoads; 9852292SN/A } 9862292SN/A 9872292SN/A if (isLoadBlocked) { 9882292SN/A if (squashed_num < blockedLoadSeqNum) { 9892292SN/A isLoadBlocked = false; 9902292SN/A loadBlockedHandled = false; 9912292SN/A blockedLoadSeqNum = 0; 9922292SN/A } 9932292SN/A } 9942292SN/A 9954032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 9964032Sktlim@umich.edu memDepViolator = NULL; 9974032Sktlim@umich.edu } 9984032Sktlim@umich.edu 9992292SN/A int store_idx = storeTail; 10002292SN/A decrStIdx(store_idx); 10012292SN/A 10022292SN/A while (stores != 0 && 10032292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 10042329SN/A // Instructions marked as can WB are already committed. 10052292SN/A if (storeQueue[store_idx].canWB) { 10062292SN/A break; 10072292SN/A } 10082292SN/A 10097720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 10102292SN/A "idx:%i [sn:%lli]\n", 10117720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 10122292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 10132292SN/A 10142329SN/A // I don't think this can happen. It should have been cleared 10152329SN/A // by the stalling load. 10162292SN/A if (isStalled() && 10172292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10182292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 10192292SN/A stalled = false; 10202292SN/A stallingStoreIsn = 0; 10212292SN/A } 10222292SN/A 10232329SN/A // Clear the smart pointer to make sure it is decremented. 10242731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 10252292SN/A storeQueue[store_idx].inst = NULL; 10262292SN/A storeQueue[store_idx].canWB = 0; 10272292SN/A 10284032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 10294032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 10304032Sktlim@umich.edu // place to really handle request deletes. 10314032Sktlim@umich.edu delete storeQueue[store_idx].req; 10326974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 10336974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqLow; 10346974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqHigh; 10356974Stjones1@inf.ed.ac.uk 10366974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = NULL; 10376974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = NULL; 10386974Stjones1@inf.ed.ac.uk } 10394032Sktlim@umich.edu 10402292SN/A storeQueue[store_idx].req = NULL; 10412292SN/A --stores; 10422292SN/A 10432292SN/A // Inefficient! 10442292SN/A storeTail = store_idx; 10452292SN/A 10462292SN/A decrStIdx(store_idx); 10472727Sktlim@umich.edu ++lsqSquashedStores; 10482292SN/A } 10492292SN/A} 10502292SN/A 10512292SN/Atemplate <class Impl> 10522292SN/Avoid 10533349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 10542693Sktlim@umich.edu{ 10552693Sktlim@umich.edu if (isStalled() && 10562693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 10572693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10582693Sktlim@umich.edu "load idx:%i\n", 10592693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 10602693Sktlim@umich.edu stalled = false; 10612693Sktlim@umich.edu stallingStoreIsn = 0; 10622693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10632693Sktlim@umich.edu } 10642693Sktlim@umich.edu 10652693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 10662693Sktlim@umich.edu // The store is basically completed at this time. This 10672693Sktlim@umich.edu // only works so long as the checker doesn't try to 10682693Sktlim@umich.edu // verify the value in memory for stores. 10692693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 10708887Sgeoffrey.blake@arm.com 10712693Sktlim@umich.edu if (cpu->checker) { 10722732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 10732693Sktlim@umich.edu } 10742693Sktlim@umich.edu } 10752693Sktlim@umich.edu 10768727Snilay@cs.wisc.edu if (needsTSO) { 10778727Snilay@cs.wisc.edu storeInFlight = true; 10788727Snilay@cs.wisc.edu } 10798727Snilay@cs.wisc.edu 10802693Sktlim@umich.edu incrStIdx(storeWBIdx); 10812693Sktlim@umich.edu} 10822693Sktlim@umich.edu 10832693Sktlim@umich.edutemplate <class Impl> 10842693Sktlim@umich.eduvoid 10852678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 10862678Sktlim@umich.edu{ 10872678Sktlim@umich.edu iewStage->wakeCPU(); 10882678Sktlim@umich.edu 10892678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 10902678Sktlim@umich.edu if (inst->isSquashed()) { 10912927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 10922678Sktlim@umich.edu assert(!inst->isStore()); 10932727Sktlim@umich.edu ++lsqIgnoredResponses; 10942678Sktlim@umich.edu return; 10952678Sktlim@umich.edu } 10962678Sktlim@umich.edu 10972678Sktlim@umich.edu if (!inst->isExecuted()) { 10982678Sktlim@umich.edu inst->setExecuted(); 10992678Sktlim@umich.edu 11002678Sktlim@umich.edu // Complete access to copy data to proper place. 11012678Sktlim@umich.edu inst->completeAcc(pkt); 11022678Sktlim@umich.edu } 11032678Sktlim@umich.edu 11042678Sktlim@umich.edu // Need to insert instruction into queue to commit 11052678Sktlim@umich.edu iewStage->instToCommit(inst); 11062678Sktlim@umich.edu 11072678Sktlim@umich.edu iewStage->activityThisCycle(); 11087598Sminkyu.jeong@arm.com 11097598Sminkyu.jeong@arm.com // see if this load changed the PC 11107598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 11112678Sktlim@umich.edu} 11122678Sktlim@umich.edu 11132678Sktlim@umich.edutemplate <class Impl> 11142678Sktlim@umich.eduvoid 11152292SN/ALSQUnit<Impl>::completeStore(int store_idx) 11162292SN/A{ 11172292SN/A assert(storeQueue[store_idx].inst); 11182292SN/A storeQueue[store_idx].completed = true; 11192292SN/A --storesToWB; 11202292SN/A // A bit conservative because a store completion may not free up entries, 11212292SN/A // but hopefully avoids two store completions in one cycle from making 11222292SN/A // the CPU tick twice. 11233126Sktlim@umich.edu cpu->wakeCPU(); 11242292SN/A cpu->activityThisCycle(); 11252292SN/A 11262292SN/A if (store_idx == storeHead) { 11272292SN/A do { 11282292SN/A incrStIdx(storeHead); 11292292SN/A 11302292SN/A --stores; 11312292SN/A } while (storeQueue[storeHead].completed && 11322292SN/A storeHead != storeTail); 11332292SN/A 11342292SN/A iewStage->updateLSQNextCycle = true; 11352292SN/A } 11362292SN/A 11372329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 11382329SN/A "idx:%i\n", 11392329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 11402292SN/A 11419527SMatt.Horsnell@arm.com#if TRACING_ON 11429527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 11439527SMatt.Horsnell@arm.com storeQueue[store_idx].inst->storeTick = 11449527SMatt.Horsnell@arm.com curTick() - storeQueue[store_idx].inst->fetchTick; 11459527SMatt.Horsnell@arm.com } 11469527SMatt.Horsnell@arm.com#endif 11479527SMatt.Horsnell@arm.com 11482292SN/A if (isStalled() && 11492292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 11502292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 11512292SN/A "load idx:%i\n", 11522292SN/A stallingStoreIsn, stallingLoadIdx); 11532292SN/A stalled = false; 11542292SN/A stallingStoreIsn = 0; 11552292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 11562292SN/A } 11572316SN/A 11582316SN/A storeQueue[store_idx].inst->setCompleted(); 11592329SN/A 11608727Snilay@cs.wisc.edu if (needsTSO) { 11618727Snilay@cs.wisc.edu storeInFlight = false; 11628727Snilay@cs.wisc.edu } 11638727Snilay@cs.wisc.edu 11642329SN/A // Tell the checker we've completed this instruction. Some stores 11652329SN/A // may get reported twice to the checker, but the checker can 11662329SN/A // handle that case. 11672316SN/A if (cpu->checker) { 11682732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 11692316SN/A } 11702292SN/A} 11712292SN/A 11722292SN/Atemplate <class Impl> 11736974Stjones1@inf.ed.ac.ukbool 11746974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::sendStore(PacketPtr data_pkt) 11756974Stjones1@inf.ed.ac.uk{ 11768975Sandreas.hansson@arm.com if (!dcachePort->sendTimingReq(data_pkt)) { 11776974Stjones1@inf.ed.ac.uk // Need to handle becoming blocked on a store. 11786974Stjones1@inf.ed.ac.uk isStoreBlocked = true; 11796974Stjones1@inf.ed.ac.uk ++lsqCacheBlocked; 11806974Stjones1@inf.ed.ac.uk assert(retryPkt == NULL); 11816974Stjones1@inf.ed.ac.uk retryPkt = data_pkt; 11826974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 11836974Stjones1@inf.ed.ac.uk return false; 11846974Stjones1@inf.ed.ac.uk } 11856974Stjones1@inf.ed.ac.uk return true; 11866974Stjones1@inf.ed.ac.uk} 11876974Stjones1@inf.ed.ac.uk 11886974Stjones1@inf.ed.ac.uktemplate <class Impl> 11892693Sktlim@umich.eduvoid 11902693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 11912693Sktlim@umich.edu{ 11922698Sktlim@umich.edu if (isStoreBlocked) { 11934985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 11942698Sktlim@umich.edu assert(retryPkt != NULL); 11952693Sktlim@umich.edu 11968587Snilay@cs.wisc.edu LSQSenderState *state = 11978587Snilay@cs.wisc.edu dynamic_cast<LSQSenderState *>(retryPkt->senderState); 11988587Snilay@cs.wisc.edu 11998975Sandreas.hansson@arm.com if (dcachePort->sendTimingReq(retryPkt)) { 12006974Stjones1@inf.ed.ac.uk // Don't finish the store unless this is the last packet. 12018133SAli.Saidi@ARM.com if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 12028133SAli.Saidi@ARM.com state->pendingPacket == retryPkt) { 12038133SAli.Saidi@ARM.com state->pktToSend = false; 12046974Stjones1@inf.ed.ac.uk storePostSend(retryPkt); 12056974Stjones1@inf.ed.ac.uk } 12062699Sktlim@umich.edu retryPkt = NULL; 12072693Sktlim@umich.edu isStoreBlocked = false; 12086221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 12096974Stjones1@inf.ed.ac.uk 12106974Stjones1@inf.ed.ac.uk // Send any outstanding packet. 12116974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 12126974Stjones1@inf.ed.ac.uk assert(state->pendingPacket); 12136974Stjones1@inf.ed.ac.uk if (sendStore(state->pendingPacket)) { 12146974Stjones1@inf.ed.ac.uk storePostSend(state->pendingPacket); 12156974Stjones1@inf.ed.ac.uk } 12166974Stjones1@inf.ed.ac.uk } 12172693Sktlim@umich.edu } else { 12182693Sktlim@umich.edu // Still blocked! 12192727Sktlim@umich.edu ++lsqCacheBlocked; 12202907Sktlim@umich.edu lsq->setRetryTid(lsqID); 12212693Sktlim@umich.edu } 12222693Sktlim@umich.edu } else if (isLoadBlocked) { 12232693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 12242693Sktlim@umich.edu "no need to resend packet.\n"); 12252693Sktlim@umich.edu } else { 12262693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 12272693Sktlim@umich.edu } 12282693Sktlim@umich.edu} 12292693Sktlim@umich.edu 12302693Sktlim@umich.edutemplate <class Impl> 12312292SN/Ainline void 12329440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::incrStIdx(int &store_idx) const 12332292SN/A{ 12342292SN/A if (++store_idx >= SQEntries) 12352292SN/A store_idx = 0; 12362292SN/A} 12372292SN/A 12382292SN/Atemplate <class Impl> 12392292SN/Ainline void 12409440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::decrStIdx(int &store_idx) const 12412292SN/A{ 12422292SN/A if (--store_idx < 0) 12432292SN/A store_idx += SQEntries; 12442292SN/A} 12452292SN/A 12462292SN/Atemplate <class Impl> 12472292SN/Ainline void 12489440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::incrLdIdx(int &load_idx) const 12492292SN/A{ 12502292SN/A if (++load_idx >= LQEntries) 12512292SN/A load_idx = 0; 12522292SN/A} 12532292SN/A 12542292SN/Atemplate <class Impl> 12552292SN/Ainline void 12569440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::decrLdIdx(int &load_idx) const 12572292SN/A{ 12582292SN/A if (--load_idx < 0) 12592292SN/A load_idx += LQEntries; 12602292SN/A} 12612329SN/A 12622329SN/Atemplate <class Impl> 12632329SN/Avoid 12649440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::dumpInsts() const 12652329SN/A{ 12662329SN/A cprintf("Load store queue: Dumping instructions.\n"); 12672329SN/A cprintf("Load queue size: %i\n", loads); 12682329SN/A cprintf("Load queue: "); 12692329SN/A 12702329SN/A int load_idx = loadHead; 12712329SN/A 12722329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 12739440SAndreas.Sandberg@ARM.com const DynInstPtr &inst(loadQueue[load_idx]); 12749440SAndreas.Sandberg@ARM.com cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 12752329SN/A 12762329SN/A incrLdIdx(load_idx); 12772329SN/A } 12789440SAndreas.Sandberg@ARM.com cprintf("\n"); 12792329SN/A 12802329SN/A cprintf("Store queue size: %i\n", stores); 12812329SN/A cprintf("Store queue: "); 12822329SN/A 12832329SN/A int store_idx = storeHead; 12842329SN/A 12852329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 12869440SAndreas.Sandberg@ARM.com const DynInstPtr &inst(storeQueue[store_idx].inst); 12879440SAndreas.Sandberg@ARM.com cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 12882329SN/A 12892329SN/A incrStIdx(store_idx); 12902329SN/A } 12912329SN/A 12922329SN/A cprintf("\n"); 12932329SN/A} 1294