impl.hh revision 3760
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com * 1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com * 2810259SAndrew.Bardsley@arm.com * Authors: Gabe Black 2910259SAndrew.Bardsley@arm.com */ 3010259SAndrew.Bardsley@arm.com 3110259SAndrew.Bardsley@arm.com#ifndef __CPU_O3_SPARC_IMPL_HH__ 3210259SAndrew.Bardsley@arm.com#define __CPU_O3_SPARC_IMPL_HH__ 3310259SAndrew.Bardsley@arm.com 3410259SAndrew.Bardsley@arm.com#include "arch/sparc/isa_traits.hh" 3510259SAndrew.Bardsley@arm.com 3610259SAndrew.Bardsley@arm.com#include "cpu/o3/sparc/params.hh" 3710259SAndrew.Bardsley@arm.com#include "cpu/o3/cpu_policy.hh" 3810259SAndrew.Bardsley@arm.com 3910259SAndrew.Bardsley@arm.com 4010259SAndrew.Bardsley@arm.com// Forward declarations. 4110259SAndrew.Bardsley@arm.comtemplate <class Impl> 4210259SAndrew.Bardsley@arm.comclass SparcDynInst; 4310259SAndrew.Bardsley@arm.com 4410259SAndrew.Bardsley@arm.comtemplate <class Impl> 4510259SAndrew.Bardsley@arm.comclass SparcO3CPU; 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.com/** Implementation specific struct that defines several key types to the 4810259SAndrew.Bardsley@arm.com * CPU, the stages within the CPU, the time buffers, and the DynInst. 4910259SAndrew.Bardsley@arm.com * The struct defines the ISA, the CPU policy, the specific DynInst, the 5010259SAndrew.Bardsley@arm.com * specific O3CPU, and all of the structs from the time buffers to do 5110259SAndrew.Bardsley@arm.com * communication. 5210259SAndrew.Bardsley@arm.com * This is one of the key things that must be defined for each hardware 5310259SAndrew.Bardsley@arm.com * specific CPU implementation. 5410259SAndrew.Bardsley@arm.com */ 5510259SAndrew.Bardsley@arm.comstruct SparcSimpleImpl 5610259SAndrew.Bardsley@arm.com{ 5710259SAndrew.Bardsley@arm.com /** The type of MachInst. */ 5810259SAndrew.Bardsley@arm.com typedef TheISA::MachInst MachInst; 5910259SAndrew.Bardsley@arm.com 6010259SAndrew.Bardsley@arm.com /** The CPU policy to be used, which defines all of the CPU stages. */ 6110259SAndrew.Bardsley@arm.com typedef SimpleCPUPolicy<SparcSimpleImpl> CPUPol; 6210259SAndrew.Bardsley@arm.com 6310259SAndrew.Bardsley@arm.com /** The DynInst type to be used. */ 6410259SAndrew.Bardsley@arm.com typedef SparcDynInst<SparcSimpleImpl> DynInst; 6510259SAndrew.Bardsley@arm.com 6610259SAndrew.Bardsley@arm.com /** The refcounted DynInst pointer to be used. In most cases this is 6710259SAndrew.Bardsley@arm.com * what should be used, and not DynInst *. 6810259SAndrew.Bardsley@arm.com */ 6910259SAndrew.Bardsley@arm.com typedef RefCountingPtr<DynInst> DynInstPtr; 7010259SAndrew.Bardsley@arm.com 7110259SAndrew.Bardsley@arm.com /** The O3CPU type to be used. */ 7210259SAndrew.Bardsley@arm.com typedef SparcO3CPU<SparcSimpleImpl> O3CPU; 7310259SAndrew.Bardsley@arm.com 7410259SAndrew.Bardsley@arm.com /** Same typedef, but for CPUType. BaseDynInst may not always use 7510259SAndrew.Bardsley@arm.com * an O3 CPU, so it's clearer to call it CPUType instead in that 7610259SAndrew.Bardsley@arm.com * case. 7710259SAndrew.Bardsley@arm.com */ 7810259SAndrew.Bardsley@arm.com typedef O3CPU CPUType; 7910259SAndrew.Bardsley@arm.com 8010259SAndrew.Bardsley@arm.com /** The Params to be passed to each stage. */ 8110259SAndrew.Bardsley@arm.com typedef SparcSimpleParams Params; 8210259SAndrew.Bardsley@arm.com 8310259SAndrew.Bardsley@arm.com enum { 8410259SAndrew.Bardsley@arm.com MaxWidth = 8, 8510259SAndrew.Bardsley@arm.com MaxThreads = 4 8610259SAndrew.Bardsley@arm.com }; 8710259SAndrew.Bardsley@arm.com}; 8810259SAndrew.Bardsley@arm.com 8910259SAndrew.Bardsley@arm.com/** The O3Impl to be used. */ 9010259SAndrew.Bardsley@arm.comtypedef SparcSimpleImpl O3CPUImpl; 9110259SAndrew.Bardsley@arm.com 9210259SAndrew.Bardsley@arm.com#endif // __CPU_O3_SPARC_IMPL_HH__ 9310259SAndrew.Bardsley@arm.com