iew_impl.hh revision 9527:68154bc0e0ea 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43// @todo: Fix the instantaneous communication among all the stages within
44// iew.  There's a clear delay between issue and execute, yet backwards
45// communication happens simultaneously.
46
47#include <queue>
48
49#include "arch/utility.hh"
50#include "config/the_isa.hh"
51#include "cpu/checker/cpu.hh"
52#include "cpu/o3/fu_pool.hh"
53#include "cpu/o3/iew.hh"
54#include "cpu/timebuf.hh"
55#include "debug/Activity.hh"
56#include "debug/Decode.hh"
57#include "debug/Drain.hh"
58#include "debug/IEW.hh"
59#include "debug/O3PipeView.hh"
60#include "params/DerivO3CPU.hh"
61
62using namespace std;
63
64template<class Impl>
65DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
66    : issueToExecQueue(params->backComSize, params->forwardComSize),
67      cpu(_cpu),
68      instQueue(_cpu, this, params),
69      ldstQueue(_cpu, this, params),
70      fuPool(params->fuPool),
71      commitToIEWDelay(params->commitToIEWDelay),
72      renameToIEWDelay(params->renameToIEWDelay),
73      issueToExecuteDelay(params->issueToExecuteDelay),
74      dispatchWidth(params->dispatchWidth),
75      issueWidth(params->issueWidth),
76      wbOutstanding(0),
77      wbWidth(params->wbWidth),
78      numThreads(params->numThreads)
79{
80    _status = Active;
81    exeStatus = Running;
82    wbStatus = Idle;
83
84    // Setup wire to read instructions coming from issue.
85    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
86
87    // Instruction queue needs the queue between issue and execute.
88    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
89
90    for (ThreadID tid = 0; tid < numThreads; tid++) {
91        dispatchStatus[tid] = Running;
92        stalls[tid].commit = false;
93        fetchRedirect[tid] = false;
94    }
95
96    wbMax = wbWidth * params->wbDepth;
97
98    updateLSQNextCycle = false;
99
100    ableToIssue = true;
101
102    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
103}
104
105template <class Impl>
106std::string
107DefaultIEW<Impl>::name() const
108{
109    return cpu->name() + ".iew";
110}
111
112template <class Impl>
113void
114DefaultIEW<Impl>::regStats()
115{
116    using namespace Stats;
117
118    instQueue.regStats();
119    ldstQueue.regStats();
120
121    iewIdleCycles
122        .name(name() + ".iewIdleCycles")
123        .desc("Number of cycles IEW is idle");
124
125    iewSquashCycles
126        .name(name() + ".iewSquashCycles")
127        .desc("Number of cycles IEW is squashing");
128
129    iewBlockCycles
130        .name(name() + ".iewBlockCycles")
131        .desc("Number of cycles IEW is blocking");
132
133    iewUnblockCycles
134        .name(name() + ".iewUnblockCycles")
135        .desc("Number of cycles IEW is unblocking");
136
137    iewDispatchedInsts
138        .name(name() + ".iewDispatchedInsts")
139        .desc("Number of instructions dispatched to IQ");
140
141    iewDispSquashedInsts
142        .name(name() + ".iewDispSquashedInsts")
143        .desc("Number of squashed instructions skipped by dispatch");
144
145    iewDispLoadInsts
146        .name(name() + ".iewDispLoadInsts")
147        .desc("Number of dispatched load instructions");
148
149    iewDispStoreInsts
150        .name(name() + ".iewDispStoreInsts")
151        .desc("Number of dispatched store instructions");
152
153    iewDispNonSpecInsts
154        .name(name() + ".iewDispNonSpecInsts")
155        .desc("Number of dispatched non-speculative instructions");
156
157    iewIQFullEvents
158        .name(name() + ".iewIQFullEvents")
159        .desc("Number of times the IQ has become full, causing a stall");
160
161    iewLSQFullEvents
162        .name(name() + ".iewLSQFullEvents")
163        .desc("Number of times the LSQ has become full, causing a stall");
164
165    memOrderViolationEvents
166        .name(name() + ".memOrderViolationEvents")
167        .desc("Number of memory order violations");
168
169    predictedTakenIncorrect
170        .name(name() + ".predictedTakenIncorrect")
171        .desc("Number of branches that were predicted taken incorrectly");
172
173    predictedNotTakenIncorrect
174        .name(name() + ".predictedNotTakenIncorrect")
175        .desc("Number of branches that were predicted not taken incorrectly");
176
177    branchMispredicts
178        .name(name() + ".branchMispredicts")
179        .desc("Number of branch mispredicts detected at execute");
180
181    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
182
183    iewExecutedInsts
184        .name(name() + ".iewExecutedInsts")
185        .desc("Number of executed instructions");
186
187    iewExecLoadInsts
188        .init(cpu->numThreads)
189        .name(name() + ".iewExecLoadInsts")
190        .desc("Number of load instructions executed")
191        .flags(total);
192
193    iewExecSquashedInsts
194        .name(name() + ".iewExecSquashedInsts")
195        .desc("Number of squashed instructions skipped in execute");
196
197    iewExecutedSwp
198        .init(cpu->numThreads)
199        .name(name() + ".exec_swp")
200        .desc("number of swp insts executed")
201        .flags(total);
202
203    iewExecutedNop
204        .init(cpu->numThreads)
205        .name(name() + ".exec_nop")
206        .desc("number of nop insts executed")
207        .flags(total);
208
209    iewExecutedRefs
210        .init(cpu->numThreads)
211        .name(name() + ".exec_refs")
212        .desc("number of memory reference insts executed")
213        .flags(total);
214
215    iewExecutedBranches
216        .init(cpu->numThreads)
217        .name(name() + ".exec_branches")
218        .desc("Number of branches executed")
219        .flags(total);
220
221    iewExecStoreInsts
222        .name(name() + ".exec_stores")
223        .desc("Number of stores executed")
224        .flags(total);
225    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
226
227    iewExecRate
228        .name(name() + ".exec_rate")
229        .desc("Inst execution rate")
230        .flags(total);
231
232    iewExecRate = iewExecutedInsts / cpu->numCycles;
233
234    iewInstsToCommit
235        .init(cpu->numThreads)
236        .name(name() + ".wb_sent")
237        .desc("cumulative count of insts sent to commit")
238        .flags(total);
239
240    writebackCount
241        .init(cpu->numThreads)
242        .name(name() + ".wb_count")
243        .desc("cumulative count of insts written-back")
244        .flags(total);
245
246    producerInst
247        .init(cpu->numThreads)
248        .name(name() + ".wb_producers")
249        .desc("num instructions producing a value")
250        .flags(total);
251
252    consumerInst
253        .init(cpu->numThreads)
254        .name(name() + ".wb_consumers")
255        .desc("num instructions consuming a value")
256        .flags(total);
257
258    wbPenalized
259        .init(cpu->numThreads)
260        .name(name() + ".wb_penalized")
261        .desc("number of instrctions required to write to 'other' IQ")
262        .flags(total);
263
264    wbPenalizedRate
265        .name(name() + ".wb_penalized_rate")
266        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
267        .flags(total);
268
269    wbPenalizedRate = wbPenalized / writebackCount;
270
271    wbFanout
272        .name(name() + ".wb_fanout")
273        .desc("average fanout of values written-back")
274        .flags(total);
275
276    wbFanout = producerInst / consumerInst;
277
278    wbRate
279        .name(name() + ".wb_rate")
280        .desc("insts written-back per cycle")
281        .flags(total);
282    wbRate = writebackCount / cpu->numCycles;
283}
284
285template<class Impl>
286void
287DefaultIEW<Impl>::startupStage()
288{
289    for (ThreadID tid = 0; tid < numThreads; tid++) {
290        toRename->iewInfo[tid].usedIQ = true;
291        toRename->iewInfo[tid].freeIQEntries =
292            instQueue.numFreeEntries(tid);
293
294        toRename->iewInfo[tid].usedLSQ = true;
295        toRename->iewInfo[tid].freeLSQEntries =
296            ldstQueue.numFreeEntries(tid);
297    }
298
299    // Initialize the checker's dcache port here
300    if (cpu->checker) {
301        cpu->checker->setDcachePort(&cpu->getDataPort());
302    }
303
304    cpu->activateStage(O3CPU::IEWIdx);
305}
306
307template<class Impl>
308void
309DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
310{
311    timeBuffer = tb_ptr;
312
313    // Setup wire to read information from time buffer, from commit.
314    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
315
316    // Setup wire to write information back to previous stages.
317    toRename = timeBuffer->getWire(0);
318
319    toFetch = timeBuffer->getWire(0);
320
321    // Instruction queue also needs main time buffer.
322    instQueue.setTimeBuffer(tb_ptr);
323}
324
325template<class Impl>
326void
327DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
328{
329    renameQueue = rq_ptr;
330
331    // Setup wire to read information from rename queue.
332    fromRename = renameQueue->getWire(-renameToIEWDelay);
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
338{
339    iewQueue = iq_ptr;
340
341    // Setup wire to write instructions to commit.
342    toCommit = iewQueue->getWire(0);
343}
344
345template<class Impl>
346void
347DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
348{
349    activeThreads = at_ptr;
350
351    ldstQueue.setActiveThreads(at_ptr);
352    instQueue.setActiveThreads(at_ptr);
353}
354
355template<class Impl>
356void
357DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
358{
359    scoreboard = sb_ptr;
360}
361
362template <class Impl>
363bool
364DefaultIEW<Impl>::isDrained() const
365{
366    bool drained(ldstQueue.isDrained());
367
368    for (ThreadID tid = 0; tid < numThreads; tid++) {
369        if (!insts[tid].empty()) {
370            DPRINTF(Drain, "%i: Insts not empty.\n", tid);
371            drained = false;
372        }
373        if (!skidBuffer[tid].empty()) {
374            DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
375            drained = false;
376        }
377    }
378
379    return drained;
380}
381
382template <class Impl>
383void
384DefaultIEW<Impl>::drainSanityCheck() const
385{
386    assert(isDrained());
387
388    instQueue.drainSanityCheck();
389    ldstQueue.drainSanityCheck();
390    fuPool->drainSanityCheck();
391}
392
393template <class Impl>
394void
395DefaultIEW<Impl>::takeOverFrom()
396{
397    // Reset all state.
398    _status = Active;
399    exeStatus = Running;
400    wbStatus = Idle;
401
402    instQueue.takeOverFrom();
403    ldstQueue.takeOverFrom();
404    fuPool->takeOverFrom();
405
406    startupStage();
407    cpu->activityThisCycle();
408
409    for (ThreadID tid = 0; tid < numThreads; tid++) {
410        dispatchStatus[tid] = Running;
411        stalls[tid].commit = false;
412        fetchRedirect[tid] = false;
413    }
414
415    updateLSQNextCycle = false;
416
417    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
418        issueToExecQueue.advance();
419    }
420}
421
422template<class Impl>
423void
424DefaultIEW<Impl>::squash(ThreadID tid)
425{
426    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
427
428    // Tell the IQ to start squashing.
429    instQueue.squash(tid);
430
431    // Tell the LDSTQ to start squashing.
432    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
433    updatedQueues = true;
434
435    // Clear the skid buffer in case it has any data in it.
436    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
437            tid, fromCommit->commitInfo[tid].doneSeqNum);
438
439    while (!skidBuffer[tid].empty()) {
440        if (skidBuffer[tid].front()->isLoad() ||
441            skidBuffer[tid].front()->isStore() ) {
442            toRename->iewInfo[tid].dispatchedToLSQ++;
443        }
444
445        toRename->iewInfo[tid].dispatched++;
446
447        skidBuffer[tid].pop();
448    }
449
450    emptyRenameInsts(tid);
451}
452
453template<class Impl>
454void
455DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
456{
457    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
458            "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
459
460    if (toCommit->squash[tid] == false ||
461            inst->seqNum < toCommit->squashedSeqNum[tid]) {
462        toCommit->squash[tid] = true;
463        toCommit->squashedSeqNum[tid] = inst->seqNum;
464        toCommit->branchTaken[tid] = inst->pcState().branching();
465
466        TheISA::PCState pc = inst->pcState();
467        TheISA::advancePC(pc, inst->staticInst);
468
469        toCommit->pc[tid] = pc;
470        toCommit->mispredictInst[tid] = inst;
471        toCommit->includeSquashInst[tid] = false;
472
473        wroteToTimeBuffer = true;
474    }
475
476}
477
478template<class Impl>
479void
480DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
481{
482    DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
483            "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
484    // Need to include inst->seqNum in the following comparison to cover the
485    // corner case when a branch misprediction and a memory violation for the
486    // same instruction (e.g. load PC) are detected in the same cycle.  In this
487    // case the memory violator should take precedence over the branch
488    // misprediction because it requires the violator itself to be included in
489    // the squash.
490    if (toCommit->squash[tid] == false ||
491            inst->seqNum <= toCommit->squashedSeqNum[tid]) {
492        toCommit->squash[tid] = true;
493
494        toCommit->squashedSeqNum[tid] = inst->seqNum;
495        toCommit->pc[tid] = inst->pcState();
496        toCommit->mispredictInst[tid] = NULL;
497
498        // Must include the memory violator in the squash.
499        toCommit->includeSquashInst[tid] = true;
500
501        wroteToTimeBuffer = true;
502    }
503}
504
505template<class Impl>
506void
507DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
508{
509    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
510            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
511    if (toCommit->squash[tid] == false ||
512            inst->seqNum < toCommit->squashedSeqNum[tid]) {
513        toCommit->squash[tid] = true;
514
515        toCommit->squashedSeqNum[tid] = inst->seqNum;
516        toCommit->pc[tid] = inst->pcState();
517        toCommit->mispredictInst[tid] = NULL;
518
519        // Must include the broadcasted SN in the squash.
520        toCommit->includeSquashInst[tid] = true;
521
522        ldstQueue.setLoadBlockedHandled(tid);
523
524        wroteToTimeBuffer = true;
525    }
526}
527
528template<class Impl>
529void
530DefaultIEW<Impl>::block(ThreadID tid)
531{
532    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
533
534    if (dispatchStatus[tid] != Blocked &&
535        dispatchStatus[tid] != Unblocking) {
536        toRename->iewBlock[tid] = true;
537        wroteToTimeBuffer = true;
538    }
539
540    // Add the current inputs to the skid buffer so they can be
541    // reprocessed when this stage unblocks.
542    skidInsert(tid);
543
544    dispatchStatus[tid] = Blocked;
545}
546
547template<class Impl>
548void
549DefaultIEW<Impl>::unblock(ThreadID tid)
550{
551    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
552            "buffer %u.\n",tid, tid);
553
554    // If the skid bufffer is empty, signal back to previous stages to unblock.
555    // Also switch status to running.
556    if (skidBuffer[tid].empty()) {
557        toRename->iewUnblock[tid] = true;
558        wroteToTimeBuffer = true;
559        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
560        dispatchStatus[tid] = Running;
561    }
562}
563
564template<class Impl>
565void
566DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
567{
568    instQueue.wakeDependents(inst);
569}
570
571template<class Impl>
572void
573DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
574{
575    instQueue.rescheduleMemInst(inst);
576}
577
578template<class Impl>
579void
580DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
581{
582    instQueue.replayMemInst(inst);
583}
584
585template<class Impl>
586void
587DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
588{
589    // This function should not be called after writebackInsts in a
590    // single cycle.  That will cause problems with an instruction
591    // being added to the queue to commit without being processed by
592    // writebackInsts prior to being sent to commit.
593
594    // First check the time slot that this instruction will write
595    // to.  If there are free write ports at the time, then go ahead
596    // and write the instruction to that time.  If there are not,
597    // keep looking back to see where's the first time there's a
598    // free slot.
599    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
600        ++wbNumInst;
601        if (wbNumInst == wbWidth) {
602            ++wbCycle;
603            wbNumInst = 0;
604        }
605
606        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
607    }
608
609    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
610            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
611    // Add finished instruction to queue to commit.
612    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
613    (*iewQueue)[wbCycle].size++;
614}
615
616template <class Impl>
617unsigned
618DefaultIEW<Impl>::validInstsFromRename()
619{
620    unsigned inst_count = 0;
621
622    for (int i=0; i<fromRename->size; i++) {
623        if (!fromRename->insts[i]->isSquashed())
624            inst_count++;
625    }
626
627    return inst_count;
628}
629
630template<class Impl>
631void
632DefaultIEW<Impl>::skidInsert(ThreadID tid)
633{
634    DynInstPtr inst = NULL;
635
636    while (!insts[tid].empty()) {
637        inst = insts[tid].front();
638
639        insts[tid].pop();
640
641        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
642                "dispatch skidBuffer %i\n",tid, inst->seqNum,
643                inst->pcState(),tid);
644
645        skidBuffer[tid].push(inst);
646    }
647
648    assert(skidBuffer[tid].size() <= skidBufferMax &&
649           "Skidbuffer Exceeded Max Size");
650}
651
652template<class Impl>
653int
654DefaultIEW<Impl>::skidCount()
655{
656    int max=0;
657
658    list<ThreadID>::iterator threads = activeThreads->begin();
659    list<ThreadID>::iterator end = activeThreads->end();
660
661    while (threads != end) {
662        ThreadID tid = *threads++;
663        unsigned thread_count = skidBuffer[tid].size();
664        if (max < thread_count)
665            max = thread_count;
666    }
667
668    return max;
669}
670
671template<class Impl>
672bool
673DefaultIEW<Impl>::skidsEmpty()
674{
675    list<ThreadID>::iterator threads = activeThreads->begin();
676    list<ThreadID>::iterator end = activeThreads->end();
677
678    while (threads != end) {
679        ThreadID tid = *threads++;
680
681        if (!skidBuffer[tid].empty())
682            return false;
683    }
684
685    return true;
686}
687
688template <class Impl>
689void
690DefaultIEW<Impl>::updateStatus()
691{
692    bool any_unblocking = false;
693
694    list<ThreadID>::iterator threads = activeThreads->begin();
695    list<ThreadID>::iterator end = activeThreads->end();
696
697    while (threads != end) {
698        ThreadID tid = *threads++;
699
700        if (dispatchStatus[tid] == Unblocking) {
701            any_unblocking = true;
702            break;
703        }
704    }
705
706    // If there are no ready instructions waiting to be scheduled by the IQ,
707    // and there's no stores waiting to write back, and dispatch is not
708    // unblocking, then there is no internal activity for the IEW stage.
709    instQueue.intInstQueueReads++;
710    if (_status == Active && !instQueue.hasReadyInsts() &&
711        !ldstQueue.willWB() && !any_unblocking) {
712        DPRINTF(IEW, "IEW switching to idle\n");
713
714        deactivateStage();
715
716        _status = Inactive;
717    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
718                                       ldstQueue.willWB() ||
719                                       any_unblocking)) {
720        // Otherwise there is internal activity.  Set to active.
721        DPRINTF(IEW, "IEW switching to active\n");
722
723        activateStage();
724
725        _status = Active;
726    }
727}
728
729template <class Impl>
730void
731DefaultIEW<Impl>::resetEntries()
732{
733    instQueue.resetEntries();
734    ldstQueue.resetEntries();
735}
736
737template <class Impl>
738void
739DefaultIEW<Impl>::readStallSignals(ThreadID tid)
740{
741    if (fromCommit->commitBlock[tid]) {
742        stalls[tid].commit = true;
743    }
744
745    if (fromCommit->commitUnblock[tid]) {
746        assert(stalls[tid].commit);
747        stalls[tid].commit = false;
748    }
749}
750
751template <class Impl>
752bool
753DefaultIEW<Impl>::checkStall(ThreadID tid)
754{
755    bool ret_val(false);
756
757    if (stalls[tid].commit) {
758        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
759        ret_val = true;
760    } else if (instQueue.isFull(tid)) {
761        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
762        ret_val = true;
763    } else if (ldstQueue.isFull(tid)) {
764        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
765
766        if (ldstQueue.numLoads(tid) > 0 ) {
767
768            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
769                    tid,ldstQueue.getLoadHeadSeqNum(tid));
770        }
771
772        if (ldstQueue.numStores(tid) > 0) {
773
774            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
775                    tid,ldstQueue.getStoreHeadSeqNum(tid));
776        }
777
778        ret_val = true;
779    } else if (ldstQueue.isStalled(tid)) {
780        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
781        ret_val = true;
782    }
783
784    return ret_val;
785}
786
787template <class Impl>
788void
789DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
790{
791    // Check if there's a squash signal, squash if there is
792    // Check stall signals, block if there is.
793    // If status was Blocked
794    //     if so then go to unblocking
795    // If status was Squashing
796    //     check if squashing is not high.  Switch to running this cycle.
797
798    readStallSignals(tid);
799
800    if (fromCommit->commitInfo[tid].squash) {
801        squash(tid);
802
803        if (dispatchStatus[tid] == Blocked ||
804            dispatchStatus[tid] == Unblocking) {
805            toRename->iewUnblock[tid] = true;
806            wroteToTimeBuffer = true;
807        }
808
809        dispatchStatus[tid] = Squashing;
810        fetchRedirect[tid] = false;
811        return;
812    }
813
814    if (fromCommit->commitInfo[tid].robSquashing) {
815        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
816
817        dispatchStatus[tid] = Squashing;
818        emptyRenameInsts(tid);
819        wroteToTimeBuffer = true;
820        return;
821    }
822
823    if (checkStall(tid)) {
824        block(tid);
825        dispatchStatus[tid] = Blocked;
826        return;
827    }
828
829    if (dispatchStatus[tid] == Blocked) {
830        // Status from previous cycle was blocked, but there are no more stall
831        // conditions.  Switch over to unblocking.
832        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
833                tid);
834
835        dispatchStatus[tid] = Unblocking;
836
837        unblock(tid);
838
839        return;
840    }
841
842    if (dispatchStatus[tid] == Squashing) {
843        // Switch status to running if rename isn't being told to block or
844        // squash this cycle.
845        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
846                tid);
847
848        dispatchStatus[tid] = Running;
849
850        return;
851    }
852}
853
854template <class Impl>
855void
856DefaultIEW<Impl>::sortInsts()
857{
858    int insts_from_rename = fromRename->size;
859#ifdef DEBUG
860    for (ThreadID tid = 0; tid < numThreads; tid++)
861        assert(insts[tid].empty());
862#endif
863    for (int i = 0; i < insts_from_rename; ++i) {
864        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
865    }
866}
867
868template <class Impl>
869void
870DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
871{
872    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
873
874    while (!insts[tid].empty()) {
875
876        if (insts[tid].front()->isLoad() ||
877            insts[tid].front()->isStore() ) {
878            toRename->iewInfo[tid].dispatchedToLSQ++;
879        }
880
881        toRename->iewInfo[tid].dispatched++;
882
883        insts[tid].pop();
884    }
885}
886
887template <class Impl>
888void
889DefaultIEW<Impl>::wakeCPU()
890{
891    cpu->wakeCPU();
892}
893
894template <class Impl>
895void
896DefaultIEW<Impl>::activityThisCycle()
897{
898    DPRINTF(Activity, "Activity this cycle.\n");
899    cpu->activityThisCycle();
900}
901
902template <class Impl>
903inline void
904DefaultIEW<Impl>::activateStage()
905{
906    DPRINTF(Activity, "Activating stage.\n");
907    cpu->activateStage(O3CPU::IEWIdx);
908}
909
910template <class Impl>
911inline void
912DefaultIEW<Impl>::deactivateStage()
913{
914    DPRINTF(Activity, "Deactivating stage.\n");
915    cpu->deactivateStage(O3CPU::IEWIdx);
916}
917
918template<class Impl>
919void
920DefaultIEW<Impl>::dispatch(ThreadID tid)
921{
922    // If status is Running or idle,
923    //     call dispatchInsts()
924    // If status is Unblocking,
925    //     buffer any instructions coming from rename
926    //     continue trying to empty skid buffer
927    //     check if stall conditions have passed
928
929    if (dispatchStatus[tid] == Blocked) {
930        ++iewBlockCycles;
931
932    } else if (dispatchStatus[tid] == Squashing) {
933        ++iewSquashCycles;
934    }
935
936    // Dispatch should try to dispatch as many instructions as its bandwidth
937    // will allow, as long as it is not currently blocked.
938    if (dispatchStatus[tid] == Running ||
939        dispatchStatus[tid] == Idle) {
940        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
941                "dispatch.\n", tid);
942
943        dispatchInsts(tid);
944    } else if (dispatchStatus[tid] == Unblocking) {
945        // Make sure that the skid buffer has something in it if the
946        // status is unblocking.
947        assert(!skidsEmpty());
948
949        // If the status was unblocking, then instructions from the skid
950        // buffer were used.  Remove those instructions and handle
951        // the rest of unblocking.
952        dispatchInsts(tid);
953
954        ++iewUnblockCycles;
955
956        if (validInstsFromRename()) {
957            // Add the current inputs to the skid buffer so they can be
958            // reprocessed when this stage unblocks.
959            skidInsert(tid);
960        }
961
962        unblock(tid);
963    }
964}
965
966template <class Impl>
967void
968DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
969{
970    // Obtain instructions from skid buffer if unblocking, or queue from rename
971    // otherwise.
972    std::queue<DynInstPtr> &insts_to_dispatch =
973        dispatchStatus[tid] == Unblocking ?
974        skidBuffer[tid] : insts[tid];
975
976    int insts_to_add = insts_to_dispatch.size();
977
978    DynInstPtr inst;
979    bool add_to_iq = false;
980    int dis_num_inst = 0;
981
982    // Loop through the instructions, putting them in the instruction
983    // queue.
984    for ( ; dis_num_inst < insts_to_add &&
985              dis_num_inst < dispatchWidth;
986          ++dis_num_inst)
987    {
988        inst = insts_to_dispatch.front();
989
990        if (dispatchStatus[tid] == Unblocking) {
991            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
992                    "buffer\n", tid);
993        }
994
995        // Make sure there's a valid instruction there.
996        assert(inst);
997
998        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
999                "IQ.\n",
1000                tid, inst->pcState(), inst->seqNum, inst->threadNumber);
1001
1002        // Be sure to mark these instructions as ready so that the
1003        // commit stage can go ahead and execute them, and mark
1004        // them as issued so the IQ doesn't reprocess them.
1005
1006        // Check for squashed instructions.
1007        if (inst->isSquashed()) {
1008            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1009                    "not adding to IQ.\n", tid);
1010
1011            ++iewDispSquashedInsts;
1012
1013            insts_to_dispatch.pop();
1014
1015            //Tell Rename That An Instruction has been processed
1016            if (inst->isLoad() || inst->isStore()) {
1017                toRename->iewInfo[tid].dispatchedToLSQ++;
1018            }
1019            toRename->iewInfo[tid].dispatched++;
1020
1021            continue;
1022        }
1023
1024        // Check for full conditions.
1025        if (instQueue.isFull(tid)) {
1026            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1027
1028            // Call function to start blocking.
1029            block(tid);
1030
1031            // Set unblock to false. Special case where we are using
1032            // skidbuffer (unblocking) instructions but then we still
1033            // get full in the IQ.
1034            toRename->iewUnblock[tid] = false;
1035
1036            ++iewIQFullEvents;
1037            break;
1038        } else if (ldstQueue.isFull(tid)) {
1039            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1040
1041            // Call function to start blocking.
1042            block(tid);
1043
1044            // Set unblock to false. Special case where we are using
1045            // skidbuffer (unblocking) instructions but then we still
1046            // get full in the IQ.
1047            toRename->iewUnblock[tid] = false;
1048
1049            ++iewLSQFullEvents;
1050            break;
1051        }
1052
1053        // Otherwise issue the instruction just fine.
1054        if (inst->isLoad()) {
1055            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1056                    "encountered, adding to LSQ.\n", tid);
1057
1058            // Reserve a spot in the load store queue for this
1059            // memory access.
1060            ldstQueue.insertLoad(inst);
1061
1062            ++iewDispLoadInsts;
1063
1064            add_to_iq = true;
1065
1066            toRename->iewInfo[tid].dispatchedToLSQ++;
1067        } else if (inst->isStore()) {
1068            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1069                    "encountered, adding to LSQ.\n", tid);
1070
1071            ldstQueue.insertStore(inst);
1072
1073            ++iewDispStoreInsts;
1074
1075            if (inst->isStoreConditional()) {
1076                // Store conditionals need to be set as "canCommit()"
1077                // so that commit can process them when they reach the
1078                // head of commit.
1079                // @todo: This is somewhat specific to Alpha.
1080                inst->setCanCommit();
1081                instQueue.insertNonSpec(inst);
1082                add_to_iq = false;
1083
1084                ++iewDispNonSpecInsts;
1085            } else {
1086                add_to_iq = true;
1087            }
1088
1089            toRename->iewInfo[tid].dispatchedToLSQ++;
1090        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1091            // Same as non-speculative stores.
1092            inst->setCanCommit();
1093            instQueue.insertBarrier(inst);
1094            add_to_iq = false;
1095        } else if (inst->isNop()) {
1096            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1097                    "skipping.\n", tid);
1098
1099            inst->setIssued();
1100            inst->setExecuted();
1101            inst->setCanCommit();
1102
1103            instQueue.recordProducer(inst);
1104
1105            iewExecutedNop[tid]++;
1106
1107            add_to_iq = false;
1108        } else if (inst->isExecuted()) {
1109            assert(0 && "Instruction shouldn't be executed.\n");
1110            DPRINTF(IEW, "Issue: Executed branch encountered, "
1111                    "skipping.\n");
1112
1113            inst->setIssued();
1114            inst->setCanCommit();
1115
1116            instQueue.recordProducer(inst);
1117
1118            add_to_iq = false;
1119        } else {
1120            add_to_iq = true;
1121        }
1122        if (inst->isNonSpeculative()) {
1123            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1124                    "encountered, skipping.\n", tid);
1125
1126            // Same as non-speculative stores.
1127            inst->setCanCommit();
1128
1129            // Specifically insert it as nonspeculative.
1130            instQueue.insertNonSpec(inst);
1131
1132            ++iewDispNonSpecInsts;
1133
1134            add_to_iq = false;
1135        }
1136
1137        // If the instruction queue is not full, then add the
1138        // instruction.
1139        if (add_to_iq) {
1140            instQueue.insert(inst);
1141        }
1142
1143        insts_to_dispatch.pop();
1144
1145        toRename->iewInfo[tid].dispatched++;
1146
1147        ++iewDispatchedInsts;
1148
1149#if TRACING_ON
1150        inst->dispatchTick = curTick() - inst->fetchTick;
1151#endif
1152    }
1153
1154    if (!insts_to_dispatch.empty()) {
1155        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1156        block(tid);
1157        toRename->iewUnblock[tid] = false;
1158    }
1159
1160    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1161        dispatchStatus[tid] = Running;
1162
1163        updatedQueues = true;
1164    }
1165
1166    dis_num_inst = 0;
1167}
1168
1169template <class Impl>
1170void
1171DefaultIEW<Impl>::printAvailableInsts()
1172{
1173    int inst = 0;
1174
1175    std::cout << "Available Instructions: ";
1176
1177    while (fromIssue->insts[inst]) {
1178
1179        if (inst%3==0) std::cout << "\n\t";
1180
1181        std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1182             << " TN: " << fromIssue->insts[inst]->threadNumber
1183             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1184
1185        inst++;
1186
1187    }
1188
1189    std::cout << "\n";
1190}
1191
1192template <class Impl>
1193void
1194DefaultIEW<Impl>::executeInsts()
1195{
1196    wbNumInst = 0;
1197    wbCycle = 0;
1198
1199    list<ThreadID>::iterator threads = activeThreads->begin();
1200    list<ThreadID>::iterator end = activeThreads->end();
1201
1202    while (threads != end) {
1203        ThreadID tid = *threads++;
1204        fetchRedirect[tid] = false;
1205    }
1206
1207    // Uncomment this if you want to see all available instructions.
1208    // @todo This doesn't actually work anymore, we should fix it.
1209//    printAvailableInsts();
1210
1211    // Execute/writeback any instructions that are available.
1212    int insts_to_execute = fromIssue->size;
1213    int inst_num = 0;
1214    for (; inst_num < insts_to_execute;
1215          ++inst_num) {
1216
1217        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1218
1219        DynInstPtr inst = instQueue.getInstToExecute();
1220
1221        DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1222                inst->pcState(), inst->threadNumber,inst->seqNum);
1223
1224        // Check if the instruction is squashed; if so then skip it
1225        if (inst->isSquashed()) {
1226            DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1227                         " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1228                         inst->seqNum);
1229
1230            // Consider this instruction executed so that commit can go
1231            // ahead and retire the instruction.
1232            inst->setExecuted();
1233
1234            // Not sure if I should set this here or just let commit try to
1235            // commit any squashed instructions.  I like the latter a bit more.
1236            inst->setCanCommit();
1237
1238            ++iewExecSquashedInsts;
1239
1240            decrWb(inst->seqNum);
1241            continue;
1242        }
1243
1244        Fault fault = NoFault;
1245
1246        // Execute instruction.
1247        // Note that if the instruction faults, it will be handled
1248        // at the commit stage.
1249        if (inst->isMemRef()) {
1250            DPRINTF(IEW, "Execute: Calculating address for memory "
1251                    "reference.\n");
1252
1253            // Tell the LDSTQ to execute this instruction (if it is a load).
1254            if (inst->isLoad()) {
1255                // Loads will mark themselves as executed, and their writeback
1256                // event adds the instruction to the queue to commit
1257                fault = ldstQueue.executeLoad(inst);
1258
1259                if (inst->isTranslationDelayed() &&
1260                    fault == NoFault) {
1261                    // A hw page table walk is currently going on; the
1262                    // instruction must be deferred.
1263                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1264                            "load.\n");
1265                    instQueue.deferMemInst(inst);
1266                    continue;
1267                }
1268
1269                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1270                    inst->fault = NoFault;
1271                }
1272            } else if (inst->isStore()) {
1273                fault = ldstQueue.executeStore(inst);
1274
1275                if (inst->isTranslationDelayed() &&
1276                    fault == NoFault) {
1277                    // A hw page table walk is currently going on; the
1278                    // instruction must be deferred.
1279                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1280                            "store.\n");
1281                    instQueue.deferMemInst(inst);
1282                    continue;
1283                }
1284
1285                // If the store had a fault then it may not have a mem req
1286                if (fault != NoFault || inst->readPredicate() == false ||
1287                        !inst->isStoreConditional()) {
1288                    // If the instruction faulted, then we need to send it along
1289                    // to commit without the instruction completing.
1290                    // Send this instruction to commit, also make sure iew stage
1291                    // realizes there is activity.
1292                    inst->setExecuted();
1293                    instToCommit(inst);
1294                    activityThisCycle();
1295                }
1296
1297                // Store conditionals will mark themselves as
1298                // executed, and their writeback event will add the
1299                // instruction to the queue to commit.
1300            } else {
1301                panic("Unexpected memory type!\n");
1302            }
1303
1304        } else {
1305            // If the instruction has already faulted, then skip executing it.
1306            // Such case can happen when it faulted during ITLB translation.
1307            // If we execute the instruction (even if it's a nop) the fault
1308            // will be replaced and we will lose it.
1309            if (inst->getFault() == NoFault) {
1310                inst->execute();
1311                if (inst->readPredicate() == false)
1312                    inst->forwardOldRegs();
1313            }
1314
1315            inst->setExecuted();
1316
1317            instToCommit(inst);
1318        }
1319
1320        updateExeInstStats(inst);
1321
1322        // Check if branch prediction was correct, if not then we need
1323        // to tell commit to squash in flight instructions.  Only
1324        // handle this if there hasn't already been something that
1325        // redirects fetch in this group of instructions.
1326
1327        // This probably needs to prioritize the redirects if a different
1328        // scheduler is used.  Currently the scheduler schedules the oldest
1329        // instruction first, so the branch resolution order will be correct.
1330        ThreadID tid = inst->threadNumber;
1331
1332        if (!fetchRedirect[tid] ||
1333            !toCommit->squash[tid] ||
1334            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1335
1336            // Prevent testing for misprediction on load instructions,
1337            // that have not been executed.
1338            bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1339
1340            if (inst->mispredicted() && !loadNotExecuted) {
1341                fetchRedirect[tid] = true;
1342
1343                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1344                DPRINTF(IEW, "Predicted target was PC: %s.\n",
1345                        inst->readPredTarg());
1346                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1347                        inst->pcState());
1348                // If incorrect, then signal the ROB that it must be squashed.
1349                squashDueToBranch(inst, tid);
1350
1351                if (inst->readPredTaken()) {
1352                    predictedTakenIncorrect++;
1353                } else {
1354                    predictedNotTakenIncorrect++;
1355                }
1356            } else if (ldstQueue.violation(tid)) {
1357                assert(inst->isMemRef());
1358                // If there was an ordering violation, then get the
1359                // DynInst that caused the violation.  Note that this
1360                // clears the violation signal.
1361                DynInstPtr violator;
1362                violator = ldstQueue.getMemDepViolator(tid);
1363
1364                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1365                        "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1366                        violator->pcState(), violator->seqNum,
1367                        inst->pcState(), inst->seqNum, inst->physEffAddr);
1368
1369                fetchRedirect[tid] = true;
1370
1371                // Tell the instruction queue that a violation has occured.
1372                instQueue.violation(inst, violator);
1373
1374                // Squash.
1375                squashDueToMemOrder(violator, tid);
1376
1377                ++memOrderViolationEvents;
1378            } else if (ldstQueue.loadBlocked(tid) &&
1379                       !ldstQueue.isLoadBlockedHandled(tid)) {
1380                fetchRedirect[tid] = true;
1381
1382                DPRINTF(IEW, "Load operation couldn't execute because the "
1383                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1384                        inst->pcState(), inst->seqNum);
1385
1386                squashDueToMemBlocked(inst, tid);
1387            }
1388        } else {
1389            // Reset any state associated with redirects that will not
1390            // be used.
1391            if (ldstQueue.violation(tid)) {
1392                assert(inst->isMemRef());
1393
1394                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1395
1396                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1397                        "%s, inst PC: %s.  Addr is: %#x.\n",
1398                        violator->pcState(), inst->pcState(),
1399                        inst->physEffAddr);
1400                DPRINTF(IEW, "Violation will not be handled because "
1401                        "already squashing\n");
1402
1403                ++memOrderViolationEvents;
1404            }
1405            if (ldstQueue.loadBlocked(tid) &&
1406                !ldstQueue.isLoadBlockedHandled(tid)) {
1407                DPRINTF(IEW, "Load operation couldn't execute because the "
1408                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1409                        inst->pcState(), inst->seqNum);
1410                DPRINTF(IEW, "Blocked load will not be handled because "
1411                        "already squashing\n");
1412
1413                ldstQueue.setLoadBlockedHandled(tid);
1414            }
1415
1416        }
1417    }
1418
1419    // Update and record activity if we processed any instructions.
1420    if (inst_num) {
1421        if (exeStatus == Idle) {
1422            exeStatus = Running;
1423        }
1424
1425        updatedQueues = true;
1426
1427        cpu->activityThisCycle();
1428    }
1429
1430    // Need to reset this in case a writeback event needs to write into the
1431    // iew queue.  That way the writeback event will write into the correct
1432    // spot in the queue.
1433    wbNumInst = 0;
1434
1435}
1436
1437template <class Impl>
1438void
1439DefaultIEW<Impl>::writebackInsts()
1440{
1441    // Loop through the head of the time buffer and wake any
1442    // dependents.  These instructions are about to write back.  Also
1443    // mark scoreboard that this instruction is finally complete.
1444    // Either have IEW have direct access to scoreboard, or have this
1445    // as part of backwards communication.
1446    for (int inst_num = 0; inst_num < wbWidth &&
1447             toCommit->insts[inst_num]; inst_num++) {
1448        DynInstPtr inst = toCommit->insts[inst_num];
1449        ThreadID tid = inst->threadNumber;
1450
1451        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1452                inst->seqNum, inst->pcState());
1453
1454        iewInstsToCommit[tid]++;
1455
1456        // Some instructions will be sent to commit without having
1457        // executed because they need commit to handle them.
1458        // E.g. Uncached loads have not actually executed when they
1459        // are first sent to commit.  Instead commit must tell the LSQ
1460        // when it's ready to execute the uncached load.
1461        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1462            int dependents = instQueue.wakeDependents(inst);
1463
1464            for (int i = 0; i < inst->numDestRegs(); i++) {
1465                //mark as Ready
1466                DPRINTF(IEW,"Setting Destination Register %i\n",
1467                        inst->renamedDestRegIdx(i));
1468                scoreboard->setReg(inst->renamedDestRegIdx(i));
1469            }
1470
1471            if (dependents) {
1472                producerInst[tid]++;
1473                consumerInst[tid]+= dependents;
1474            }
1475            writebackCount[tid]++;
1476        }
1477
1478        decrWb(inst->seqNum);
1479    }
1480}
1481
1482template<class Impl>
1483void
1484DefaultIEW<Impl>::tick()
1485{
1486    wbNumInst = 0;
1487    wbCycle = 0;
1488
1489    wroteToTimeBuffer = false;
1490    updatedQueues = false;
1491
1492    sortInsts();
1493
1494    // Free function units marked as being freed this cycle.
1495    fuPool->processFreeUnits();
1496
1497    list<ThreadID>::iterator threads = activeThreads->begin();
1498    list<ThreadID>::iterator end = activeThreads->end();
1499
1500    // Check stall and squash signals, dispatch any instructions.
1501    while (threads != end) {
1502        ThreadID tid = *threads++;
1503
1504        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1505
1506        checkSignalsAndUpdate(tid);
1507        dispatch(tid);
1508    }
1509
1510    if (exeStatus != Squashing) {
1511        executeInsts();
1512
1513        writebackInsts();
1514
1515        // Have the instruction queue try to schedule any ready instructions.
1516        // (In actuality, this scheduling is for instructions that will
1517        // be executed next cycle.)
1518        instQueue.scheduleReadyInsts();
1519
1520        // Also should advance its own time buffers if the stage ran.
1521        // Not the best place for it, but this works (hopefully).
1522        issueToExecQueue.advance();
1523    }
1524
1525    bool broadcast_free_entries = false;
1526
1527    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1528        exeStatus = Idle;
1529        updateLSQNextCycle = false;
1530
1531        broadcast_free_entries = true;
1532    }
1533
1534    // Writeback any stores using any leftover bandwidth.
1535    ldstQueue.writebackStores();
1536
1537    // Check the committed load/store signals to see if there's a load
1538    // or store to commit.  Also check if it's being told to execute a
1539    // nonspeculative instruction.
1540    // This is pretty inefficient...
1541
1542    threads = activeThreads->begin();
1543    while (threads != end) {
1544        ThreadID tid = (*threads++);
1545
1546        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1547
1548        // Update structures based on instructions committed.
1549        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1550            !fromCommit->commitInfo[tid].squash &&
1551            !fromCommit->commitInfo[tid].robSquashing) {
1552
1553            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1554
1555            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1556
1557            updateLSQNextCycle = true;
1558            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1559        }
1560
1561        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1562
1563            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1564            if (fromCommit->commitInfo[tid].uncached) {
1565                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1566                fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1567            } else {
1568                instQueue.scheduleNonSpec(
1569                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1570            }
1571        }
1572
1573        if (broadcast_free_entries) {
1574            toFetch->iewInfo[tid].iqCount =
1575                instQueue.getCount(tid);
1576            toFetch->iewInfo[tid].ldstqCount =
1577                ldstQueue.getCount(tid);
1578
1579            toRename->iewInfo[tid].usedIQ = true;
1580            toRename->iewInfo[tid].freeIQEntries =
1581                instQueue.numFreeEntries();
1582            toRename->iewInfo[tid].usedLSQ = true;
1583            toRename->iewInfo[tid].freeLSQEntries =
1584                ldstQueue.numFreeEntries(tid);
1585
1586            wroteToTimeBuffer = true;
1587        }
1588
1589        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1590                tid, toRename->iewInfo[tid].dispatched);
1591    }
1592
1593    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1594            "LSQ has %i free entries.\n",
1595            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1596            ldstQueue.numFreeEntries());
1597
1598    updateStatus();
1599
1600    if (wroteToTimeBuffer) {
1601        DPRINTF(Activity, "Activity this cycle.\n");
1602        cpu->activityThisCycle();
1603    }
1604}
1605
1606template <class Impl>
1607void
1608DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1609{
1610    ThreadID tid = inst->threadNumber;
1611
1612    iewExecutedInsts++;
1613
1614#if TRACING_ON
1615    if (DTRACE(O3PipeView)) {
1616        inst->completeTick = curTick() - inst->fetchTick;
1617    }
1618#endif
1619
1620    //
1621    //  Control operations
1622    //
1623    if (inst->isControl())
1624        iewExecutedBranches[tid]++;
1625
1626    //
1627    //  Memory operations
1628    //
1629    if (inst->isMemRef()) {
1630        iewExecutedRefs[tid]++;
1631
1632        if (inst->isLoad()) {
1633            iewExecLoadInsts[tid]++;
1634        }
1635    }
1636}
1637
1638template <class Impl>
1639void
1640DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1641{
1642    ThreadID tid = inst->threadNumber;
1643
1644    if (!fetchRedirect[tid] ||
1645        !toCommit->squash[tid] ||
1646        toCommit->squashedSeqNum[tid] > inst->seqNum) {
1647
1648        if (inst->mispredicted()) {
1649            fetchRedirect[tid] = true;
1650
1651            DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1652            DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1653                    inst->predInstAddr(), inst->predNextInstAddr());
1654            DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1655                    " NPC: %#x.\n", inst->nextInstAddr(),
1656                    inst->nextInstAddr());
1657            // If incorrect, then signal the ROB that it must be squashed.
1658            squashDueToBranch(inst, tid);
1659
1660            if (inst->readPredTaken()) {
1661                predictedTakenIncorrect++;
1662            } else {
1663                predictedNotTakenIncorrect++;
1664            }
1665        }
1666    }
1667}
1668