iew_impl.hh revision 8230:845c8eb5ac49 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43// @todo: Fix the instantaneous communication among all the stages within
44// iew.  There's a clear delay between issue and execute, yet backwards
45// communication happens simultaneously.
46
47#include <queue>
48
49#include "arch/utility.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/iew.hh"
53#include "cpu/timebuf.hh"
54#include "params/DerivO3CPU.hh"
55
56using namespace std;
57
58template<class Impl>
59DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
60    : issueToExecQueue(params->backComSize, params->forwardComSize),
61      cpu(_cpu),
62      instQueue(_cpu, this, params),
63      ldstQueue(_cpu, this, params),
64      fuPool(params->fuPool),
65      commitToIEWDelay(params->commitToIEWDelay),
66      renameToIEWDelay(params->renameToIEWDelay),
67      issueToExecuteDelay(params->issueToExecuteDelay),
68      dispatchWidth(params->dispatchWidth),
69      issueWidth(params->issueWidth),
70      wbOutstanding(0),
71      wbWidth(params->wbWidth),
72      numThreads(params->numThreads),
73      switchedOut(false)
74{
75    _status = Active;
76    exeStatus = Running;
77    wbStatus = Idle;
78
79    // Setup wire to read instructions coming from issue.
80    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
81
82    // Instruction queue needs the queue between issue and execute.
83    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
84
85    for (ThreadID tid = 0; tid < numThreads; tid++) {
86        dispatchStatus[tid] = Running;
87        stalls[tid].commit = false;
88        fetchRedirect[tid] = false;
89    }
90
91    wbMax = wbWidth * params->wbDepth;
92
93    updateLSQNextCycle = false;
94
95    ableToIssue = true;
96
97    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
98}
99
100template <class Impl>
101std::string
102DefaultIEW<Impl>::name() const
103{
104    return cpu->name() + ".iew";
105}
106
107template <class Impl>
108void
109DefaultIEW<Impl>::regStats()
110{
111    using namespace Stats;
112
113    instQueue.regStats();
114    ldstQueue.regStats();
115
116    iewIdleCycles
117        .name(name() + ".iewIdleCycles")
118        .desc("Number of cycles IEW is idle");
119
120    iewSquashCycles
121        .name(name() + ".iewSquashCycles")
122        .desc("Number of cycles IEW is squashing");
123
124    iewBlockCycles
125        .name(name() + ".iewBlockCycles")
126        .desc("Number of cycles IEW is blocking");
127
128    iewUnblockCycles
129        .name(name() + ".iewUnblockCycles")
130        .desc("Number of cycles IEW is unblocking");
131
132    iewDispatchedInsts
133        .name(name() + ".iewDispatchedInsts")
134        .desc("Number of instructions dispatched to IQ");
135
136    iewDispSquashedInsts
137        .name(name() + ".iewDispSquashedInsts")
138        .desc("Number of squashed instructions skipped by dispatch");
139
140    iewDispLoadInsts
141        .name(name() + ".iewDispLoadInsts")
142        .desc("Number of dispatched load instructions");
143
144    iewDispStoreInsts
145        .name(name() + ".iewDispStoreInsts")
146        .desc("Number of dispatched store instructions");
147
148    iewDispNonSpecInsts
149        .name(name() + ".iewDispNonSpecInsts")
150        .desc("Number of dispatched non-speculative instructions");
151
152    iewIQFullEvents
153        .name(name() + ".iewIQFullEvents")
154        .desc("Number of times the IQ has become full, causing a stall");
155
156    iewLSQFullEvents
157        .name(name() + ".iewLSQFullEvents")
158        .desc("Number of times the LSQ has become full, causing a stall");
159
160    memOrderViolationEvents
161        .name(name() + ".memOrderViolationEvents")
162        .desc("Number of memory order violations");
163
164    predictedTakenIncorrect
165        .name(name() + ".predictedTakenIncorrect")
166        .desc("Number of branches that were predicted taken incorrectly");
167
168    predictedNotTakenIncorrect
169        .name(name() + ".predictedNotTakenIncorrect")
170        .desc("Number of branches that were predicted not taken incorrectly");
171
172    branchMispredicts
173        .name(name() + ".branchMispredicts")
174        .desc("Number of branch mispredicts detected at execute");
175
176    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
177
178    iewExecutedInsts
179        .name(name() + ".iewExecutedInsts")
180        .desc("Number of executed instructions");
181
182    iewExecLoadInsts
183        .init(cpu->numThreads)
184        .name(name() + ".iewExecLoadInsts")
185        .desc("Number of load instructions executed")
186        .flags(total);
187
188    iewExecSquashedInsts
189        .name(name() + ".iewExecSquashedInsts")
190        .desc("Number of squashed instructions skipped in execute");
191
192    iewExecutedSwp
193        .init(cpu->numThreads)
194        .name(name() + ".EXEC:swp")
195        .desc("number of swp insts executed")
196        .flags(total);
197
198    iewExecutedNop
199        .init(cpu->numThreads)
200        .name(name() + ".EXEC:nop")
201        .desc("number of nop insts executed")
202        .flags(total);
203
204    iewExecutedRefs
205        .init(cpu->numThreads)
206        .name(name() + ".EXEC:refs")
207        .desc("number of memory reference insts executed")
208        .flags(total);
209
210    iewExecutedBranches
211        .init(cpu->numThreads)
212        .name(name() + ".EXEC:branches")
213        .desc("Number of branches executed")
214        .flags(total);
215
216    iewExecStoreInsts
217        .name(name() + ".EXEC:stores")
218        .desc("Number of stores executed")
219        .flags(total);
220    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
221
222    iewExecRate
223        .name(name() + ".EXEC:rate")
224        .desc("Inst execution rate")
225        .flags(total);
226
227    iewExecRate = iewExecutedInsts / cpu->numCycles;
228
229    iewInstsToCommit
230        .init(cpu->numThreads)
231        .name(name() + ".WB:sent")
232        .desc("cumulative count of insts sent to commit")
233        .flags(total);
234
235    writebackCount
236        .init(cpu->numThreads)
237        .name(name() + ".WB:count")
238        .desc("cumulative count of insts written-back")
239        .flags(total);
240
241    producerInst
242        .init(cpu->numThreads)
243        .name(name() + ".WB:producers")
244        .desc("num instructions producing a value")
245        .flags(total);
246
247    consumerInst
248        .init(cpu->numThreads)
249        .name(name() + ".WB:consumers")
250        .desc("num instructions consuming a value")
251        .flags(total);
252
253    wbPenalized
254        .init(cpu->numThreads)
255        .name(name() + ".WB:penalized")
256        .desc("number of instrctions required to write to 'other' IQ")
257        .flags(total);
258
259    wbPenalizedRate
260        .name(name() + ".WB:penalized_rate")
261        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
262        .flags(total);
263
264    wbPenalizedRate = wbPenalized / writebackCount;
265
266    wbFanout
267        .name(name() + ".WB:fanout")
268        .desc("average fanout of values written-back")
269        .flags(total);
270
271    wbFanout = producerInst / consumerInst;
272
273    wbRate
274        .name(name() + ".WB:rate")
275        .desc("insts written-back per cycle")
276        .flags(total);
277    wbRate = writebackCount / cpu->numCycles;
278}
279
280template<class Impl>
281void
282DefaultIEW<Impl>::initStage()
283{
284    for (ThreadID tid = 0; tid < numThreads; tid++) {
285        toRename->iewInfo[tid].usedIQ = true;
286        toRename->iewInfo[tid].freeIQEntries =
287            instQueue.numFreeEntries(tid);
288
289        toRename->iewInfo[tid].usedLSQ = true;
290        toRename->iewInfo[tid].freeLSQEntries =
291            ldstQueue.numFreeEntries(tid);
292    }
293
294    cpu->activateStage(O3CPU::IEWIdx);
295}
296
297template<class Impl>
298void
299DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
300{
301    timeBuffer = tb_ptr;
302
303    // Setup wire to read information from time buffer, from commit.
304    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
305
306    // Setup wire to write information back to previous stages.
307    toRename = timeBuffer->getWire(0);
308
309    toFetch = timeBuffer->getWire(0);
310
311    // Instruction queue also needs main time buffer.
312    instQueue.setTimeBuffer(tb_ptr);
313}
314
315template<class Impl>
316void
317DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
318{
319    renameQueue = rq_ptr;
320
321    // Setup wire to read information from rename queue.
322    fromRename = renameQueue->getWire(-renameToIEWDelay);
323}
324
325template<class Impl>
326void
327DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
328{
329    iewQueue = iq_ptr;
330
331    // Setup wire to write instructions to commit.
332    toCommit = iewQueue->getWire(0);
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
338{
339    activeThreads = at_ptr;
340
341    ldstQueue.setActiveThreads(at_ptr);
342    instQueue.setActiveThreads(at_ptr);
343}
344
345template<class Impl>
346void
347DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
348{
349    scoreboard = sb_ptr;
350}
351
352template <class Impl>
353bool
354DefaultIEW<Impl>::drain()
355{
356    // IEW is ready to drain at any time.
357    cpu->signalDrained();
358    return true;
359}
360
361template <class Impl>
362void
363DefaultIEW<Impl>::resume()
364{
365}
366
367template <class Impl>
368void
369DefaultIEW<Impl>::switchOut()
370{
371    // Clear any state.
372    switchedOut = true;
373    assert(insts[0].empty());
374    assert(skidBuffer[0].empty());
375
376    instQueue.switchOut();
377    ldstQueue.switchOut();
378    fuPool->switchOut();
379
380    for (ThreadID tid = 0; tid < numThreads; tid++) {
381        while (!insts[tid].empty())
382            insts[tid].pop();
383        while (!skidBuffer[tid].empty())
384            skidBuffer[tid].pop();
385    }
386}
387
388template <class Impl>
389void
390DefaultIEW<Impl>::takeOverFrom()
391{
392    // Reset all state.
393    _status = Active;
394    exeStatus = Running;
395    wbStatus = Idle;
396    switchedOut = false;
397
398    instQueue.takeOverFrom();
399    ldstQueue.takeOverFrom();
400    fuPool->takeOverFrom();
401
402    initStage();
403    cpu->activityThisCycle();
404
405    for (ThreadID tid = 0; tid < numThreads; tid++) {
406        dispatchStatus[tid] = Running;
407        stalls[tid].commit = false;
408        fetchRedirect[tid] = false;
409    }
410
411    updateLSQNextCycle = false;
412
413    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
414        issueToExecQueue.advance();
415    }
416}
417
418template<class Impl>
419void
420DefaultIEW<Impl>::squash(ThreadID tid)
421{
422    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
423
424    // Tell the IQ to start squashing.
425    instQueue.squash(tid);
426
427    // Tell the LDSTQ to start squashing.
428    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
429    updatedQueues = true;
430
431    // Clear the skid buffer in case it has any data in it.
432    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
433            tid, fromCommit->commitInfo[tid].doneSeqNum);
434
435    while (!skidBuffer[tid].empty()) {
436        if (skidBuffer[tid].front()->isLoad() ||
437            skidBuffer[tid].front()->isStore() ) {
438            toRename->iewInfo[tid].dispatchedToLSQ++;
439        }
440
441        toRename->iewInfo[tid].dispatched++;
442
443        skidBuffer[tid].pop();
444    }
445
446    emptyRenameInsts(tid);
447}
448
449template<class Impl>
450void
451DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
452{
453    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
454            "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
455
456    if (toCommit->squash[tid] == false ||
457            inst->seqNum < toCommit->squashedSeqNum[tid]) {
458        toCommit->squash[tid] = true;
459        toCommit->squashedSeqNum[tid] = inst->seqNum;
460        toCommit->branchTaken[tid] = inst->pcState().branching();
461
462        TheISA::PCState pc = inst->pcState();
463        TheISA::advancePC(pc, inst->staticInst);
464
465        toCommit->pc[tid] = pc;
466        toCommit->mispredictInst[tid] = inst;
467        toCommit->includeSquashInst[tid] = false;
468
469        wroteToTimeBuffer = true;
470    }
471
472}
473
474template<class Impl>
475void
476DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
477{
478    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
479            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
480
481    if (toCommit->squash[tid] == false ||
482            inst->seqNum < toCommit->squashedSeqNum[tid]) {
483        toCommit->squash[tid] = true;
484        toCommit->squashedSeqNum[tid] = inst->seqNum;
485        TheISA::PCState pc = inst->pcState();
486        TheISA::advancePC(pc, inst->staticInst);
487        toCommit->pc[tid] = pc;
488        toCommit->mispredictInst[tid] = NULL;
489
490        toCommit->includeSquashInst[tid] = false;
491
492        wroteToTimeBuffer = true;
493    }
494}
495
496template<class Impl>
497void
498DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
499{
500    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
501            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
502    if (toCommit->squash[tid] == false ||
503            inst->seqNum < toCommit->squashedSeqNum[tid]) {
504        toCommit->squash[tid] = true;
505
506        toCommit->squashedSeqNum[tid] = inst->seqNum;
507        toCommit->pc[tid] = inst->pcState();
508        toCommit->mispredictInst[tid] = NULL;
509
510        // Must include the broadcasted SN in the squash.
511        toCommit->includeSquashInst[tid] = true;
512
513        ldstQueue.setLoadBlockedHandled(tid);
514
515        wroteToTimeBuffer = true;
516    }
517}
518
519template<class Impl>
520void
521DefaultIEW<Impl>::block(ThreadID tid)
522{
523    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
524
525    if (dispatchStatus[tid] != Blocked &&
526        dispatchStatus[tid] != Unblocking) {
527        toRename->iewBlock[tid] = true;
528        wroteToTimeBuffer = true;
529    }
530
531    // Add the current inputs to the skid buffer so they can be
532    // reprocessed when this stage unblocks.
533    skidInsert(tid);
534
535    dispatchStatus[tid] = Blocked;
536}
537
538template<class Impl>
539void
540DefaultIEW<Impl>::unblock(ThreadID tid)
541{
542    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
543            "buffer %u.\n",tid, tid);
544
545    // If the skid bufffer is empty, signal back to previous stages to unblock.
546    // Also switch status to running.
547    if (skidBuffer[tid].empty()) {
548        toRename->iewUnblock[tid] = true;
549        wroteToTimeBuffer = true;
550        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
551        dispatchStatus[tid] = Running;
552    }
553}
554
555template<class Impl>
556void
557DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
558{
559    instQueue.wakeDependents(inst);
560}
561
562template<class Impl>
563void
564DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
565{
566    instQueue.rescheduleMemInst(inst);
567}
568
569template<class Impl>
570void
571DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
572{
573    instQueue.replayMemInst(inst);
574}
575
576template<class Impl>
577void
578DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
579{
580    // This function should not be called after writebackInsts in a
581    // single cycle.  That will cause problems with an instruction
582    // being added to the queue to commit without being processed by
583    // writebackInsts prior to being sent to commit.
584
585    // First check the time slot that this instruction will write
586    // to.  If there are free write ports at the time, then go ahead
587    // and write the instruction to that time.  If there are not,
588    // keep looking back to see where's the first time there's a
589    // free slot.
590    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
591        ++wbNumInst;
592        if (wbNumInst == wbWidth) {
593            ++wbCycle;
594            wbNumInst = 0;
595        }
596
597        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
598    }
599
600    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
601            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
602    // Add finished instruction to queue to commit.
603    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
604    (*iewQueue)[wbCycle].size++;
605}
606
607template <class Impl>
608unsigned
609DefaultIEW<Impl>::validInstsFromRename()
610{
611    unsigned inst_count = 0;
612
613    for (int i=0; i<fromRename->size; i++) {
614        if (!fromRename->insts[i]->isSquashed())
615            inst_count++;
616    }
617
618    return inst_count;
619}
620
621template<class Impl>
622void
623DefaultIEW<Impl>::skidInsert(ThreadID tid)
624{
625    DynInstPtr inst = NULL;
626
627    while (!insts[tid].empty()) {
628        inst = insts[tid].front();
629
630        insts[tid].pop();
631
632        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
633                "dispatch skidBuffer %i\n",tid, inst->seqNum,
634                inst->pcState(),tid);
635
636        skidBuffer[tid].push(inst);
637    }
638
639    assert(skidBuffer[tid].size() <= skidBufferMax &&
640           "Skidbuffer Exceeded Max Size");
641}
642
643template<class Impl>
644int
645DefaultIEW<Impl>::skidCount()
646{
647    int max=0;
648
649    list<ThreadID>::iterator threads = activeThreads->begin();
650    list<ThreadID>::iterator end = activeThreads->end();
651
652    while (threads != end) {
653        ThreadID tid = *threads++;
654        unsigned thread_count = skidBuffer[tid].size();
655        if (max < thread_count)
656            max = thread_count;
657    }
658
659    return max;
660}
661
662template<class Impl>
663bool
664DefaultIEW<Impl>::skidsEmpty()
665{
666    list<ThreadID>::iterator threads = activeThreads->begin();
667    list<ThreadID>::iterator end = activeThreads->end();
668
669    while (threads != end) {
670        ThreadID tid = *threads++;
671
672        if (!skidBuffer[tid].empty())
673            return false;
674    }
675
676    return true;
677}
678
679template <class Impl>
680void
681DefaultIEW<Impl>::updateStatus()
682{
683    bool any_unblocking = false;
684
685    list<ThreadID>::iterator threads = activeThreads->begin();
686    list<ThreadID>::iterator end = activeThreads->end();
687
688    while (threads != end) {
689        ThreadID tid = *threads++;
690
691        if (dispatchStatus[tid] == Unblocking) {
692            any_unblocking = true;
693            break;
694        }
695    }
696
697    // If there are no ready instructions waiting to be scheduled by the IQ,
698    // and there's no stores waiting to write back, and dispatch is not
699    // unblocking, then there is no internal activity for the IEW stage.
700    instQueue.intInstQueueReads++;
701    if (_status == Active && !instQueue.hasReadyInsts() &&
702        !ldstQueue.willWB() && !any_unblocking) {
703        DPRINTF(IEW, "IEW switching to idle\n");
704
705        deactivateStage();
706
707        _status = Inactive;
708    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
709                                       ldstQueue.willWB() ||
710                                       any_unblocking)) {
711        // Otherwise there is internal activity.  Set to active.
712        DPRINTF(IEW, "IEW switching to active\n");
713
714        activateStage();
715
716        _status = Active;
717    }
718}
719
720template <class Impl>
721void
722DefaultIEW<Impl>::resetEntries()
723{
724    instQueue.resetEntries();
725    ldstQueue.resetEntries();
726}
727
728template <class Impl>
729void
730DefaultIEW<Impl>::readStallSignals(ThreadID tid)
731{
732    if (fromCommit->commitBlock[tid]) {
733        stalls[tid].commit = true;
734    }
735
736    if (fromCommit->commitUnblock[tid]) {
737        assert(stalls[tid].commit);
738        stalls[tid].commit = false;
739    }
740}
741
742template <class Impl>
743bool
744DefaultIEW<Impl>::checkStall(ThreadID tid)
745{
746    bool ret_val(false);
747
748    if (stalls[tid].commit) {
749        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
750        ret_val = true;
751    } else if (instQueue.isFull(tid)) {
752        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
753        ret_val = true;
754    } else if (ldstQueue.isFull(tid)) {
755        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
756
757        if (ldstQueue.numLoads(tid) > 0 ) {
758
759            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
760                    tid,ldstQueue.getLoadHeadSeqNum(tid));
761        }
762
763        if (ldstQueue.numStores(tid) > 0) {
764
765            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
766                    tid,ldstQueue.getStoreHeadSeqNum(tid));
767        }
768
769        ret_val = true;
770    } else if (ldstQueue.isStalled(tid)) {
771        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
772        ret_val = true;
773    }
774
775    return ret_val;
776}
777
778template <class Impl>
779void
780DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
781{
782    // Check if there's a squash signal, squash if there is
783    // Check stall signals, block if there is.
784    // If status was Blocked
785    //     if so then go to unblocking
786    // If status was Squashing
787    //     check if squashing is not high.  Switch to running this cycle.
788
789    readStallSignals(tid);
790
791    if (fromCommit->commitInfo[tid].squash) {
792        squash(tid);
793
794        if (dispatchStatus[tid] == Blocked ||
795            dispatchStatus[tid] == Unblocking) {
796            toRename->iewUnblock[tid] = true;
797            wroteToTimeBuffer = true;
798        }
799
800        dispatchStatus[tid] = Squashing;
801        fetchRedirect[tid] = false;
802        return;
803    }
804
805    if (fromCommit->commitInfo[tid].robSquashing) {
806        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
807
808        dispatchStatus[tid] = Squashing;
809        emptyRenameInsts(tid);
810        wroteToTimeBuffer = true;
811        return;
812    }
813
814    if (checkStall(tid)) {
815        block(tid);
816        dispatchStatus[tid] = Blocked;
817        return;
818    }
819
820    if (dispatchStatus[tid] == Blocked) {
821        // Status from previous cycle was blocked, but there are no more stall
822        // conditions.  Switch over to unblocking.
823        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
824                tid);
825
826        dispatchStatus[tid] = Unblocking;
827
828        unblock(tid);
829
830        return;
831    }
832
833    if (dispatchStatus[tid] == Squashing) {
834        // Switch status to running if rename isn't being told to block or
835        // squash this cycle.
836        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
837                tid);
838
839        dispatchStatus[tid] = Running;
840
841        return;
842    }
843}
844
845template <class Impl>
846void
847DefaultIEW<Impl>::sortInsts()
848{
849    int insts_from_rename = fromRename->size;
850#ifdef DEBUG
851    for (ThreadID tid = 0; tid < numThreads; tid++)
852        assert(insts[tid].empty());
853#endif
854    for (int i = 0; i < insts_from_rename; ++i) {
855        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
856    }
857}
858
859template <class Impl>
860void
861DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
862{
863    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
864
865    while (!insts[tid].empty()) {
866
867        if (insts[tid].front()->isLoad() ||
868            insts[tid].front()->isStore() ) {
869            toRename->iewInfo[tid].dispatchedToLSQ++;
870        }
871
872        toRename->iewInfo[tid].dispatched++;
873
874        insts[tid].pop();
875    }
876}
877
878template <class Impl>
879void
880DefaultIEW<Impl>::wakeCPU()
881{
882    cpu->wakeCPU();
883}
884
885template <class Impl>
886void
887DefaultIEW<Impl>::activityThisCycle()
888{
889    DPRINTF(Activity, "Activity this cycle.\n");
890    cpu->activityThisCycle();
891}
892
893template <class Impl>
894inline void
895DefaultIEW<Impl>::activateStage()
896{
897    DPRINTF(Activity, "Activating stage.\n");
898    cpu->activateStage(O3CPU::IEWIdx);
899}
900
901template <class Impl>
902inline void
903DefaultIEW<Impl>::deactivateStage()
904{
905    DPRINTF(Activity, "Deactivating stage.\n");
906    cpu->deactivateStage(O3CPU::IEWIdx);
907}
908
909template<class Impl>
910void
911DefaultIEW<Impl>::dispatch(ThreadID tid)
912{
913    // If status is Running or idle,
914    //     call dispatchInsts()
915    // If status is Unblocking,
916    //     buffer any instructions coming from rename
917    //     continue trying to empty skid buffer
918    //     check if stall conditions have passed
919
920    if (dispatchStatus[tid] == Blocked) {
921        ++iewBlockCycles;
922
923    } else if (dispatchStatus[tid] == Squashing) {
924        ++iewSquashCycles;
925    }
926
927    // Dispatch should try to dispatch as many instructions as its bandwidth
928    // will allow, as long as it is not currently blocked.
929    if (dispatchStatus[tid] == Running ||
930        dispatchStatus[tid] == Idle) {
931        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
932                "dispatch.\n", tid);
933
934        dispatchInsts(tid);
935    } else if (dispatchStatus[tid] == Unblocking) {
936        // Make sure that the skid buffer has something in it if the
937        // status is unblocking.
938        assert(!skidsEmpty());
939
940        // If the status was unblocking, then instructions from the skid
941        // buffer were used.  Remove those instructions and handle
942        // the rest of unblocking.
943        dispatchInsts(tid);
944
945        ++iewUnblockCycles;
946
947        if (validInstsFromRename()) {
948            // Add the current inputs to the skid buffer so they can be
949            // reprocessed when this stage unblocks.
950            skidInsert(tid);
951        }
952
953        unblock(tid);
954    }
955}
956
957template <class Impl>
958void
959DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
960{
961    // Obtain instructions from skid buffer if unblocking, or queue from rename
962    // otherwise.
963    std::queue<DynInstPtr> &insts_to_dispatch =
964        dispatchStatus[tid] == Unblocking ?
965        skidBuffer[tid] : insts[tid];
966
967    int insts_to_add = insts_to_dispatch.size();
968
969    DynInstPtr inst;
970    bool add_to_iq = false;
971    int dis_num_inst = 0;
972
973    // Loop through the instructions, putting them in the instruction
974    // queue.
975    for ( ; dis_num_inst < insts_to_add &&
976              dis_num_inst < dispatchWidth;
977          ++dis_num_inst)
978    {
979        inst = insts_to_dispatch.front();
980
981        if (dispatchStatus[tid] == Unblocking) {
982            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
983                    "buffer\n", tid);
984        }
985
986        // Make sure there's a valid instruction there.
987        assert(inst);
988
989        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
990                "IQ.\n",
991                tid, inst->pcState(), inst->seqNum, inst->threadNumber);
992
993        // Be sure to mark these instructions as ready so that the
994        // commit stage can go ahead and execute them, and mark
995        // them as issued so the IQ doesn't reprocess them.
996
997        // Check for squashed instructions.
998        if (inst->isSquashed()) {
999            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1000                    "not adding to IQ.\n", tid);
1001
1002            ++iewDispSquashedInsts;
1003
1004            insts_to_dispatch.pop();
1005
1006            //Tell Rename That An Instruction has been processed
1007            if (inst->isLoad() || inst->isStore()) {
1008                toRename->iewInfo[tid].dispatchedToLSQ++;
1009            }
1010            toRename->iewInfo[tid].dispatched++;
1011
1012            continue;
1013        }
1014
1015        // Check for full conditions.
1016        if (instQueue.isFull(tid)) {
1017            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1018
1019            // Call function to start blocking.
1020            block(tid);
1021
1022            // Set unblock to false. Special case where we are using
1023            // skidbuffer (unblocking) instructions but then we still
1024            // get full in the IQ.
1025            toRename->iewUnblock[tid] = false;
1026
1027            ++iewIQFullEvents;
1028            break;
1029        } else if (ldstQueue.isFull(tid)) {
1030            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1031
1032            // Call function to start blocking.
1033            block(tid);
1034
1035            // Set unblock to false. Special case where we are using
1036            // skidbuffer (unblocking) instructions but then we still
1037            // get full in the IQ.
1038            toRename->iewUnblock[tid] = false;
1039
1040            ++iewLSQFullEvents;
1041            break;
1042        }
1043
1044        // Otherwise issue the instruction just fine.
1045        if (inst->isLoad()) {
1046            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1047                    "encountered, adding to LSQ.\n", tid);
1048
1049            // Reserve a spot in the load store queue for this
1050            // memory access.
1051            ldstQueue.insertLoad(inst);
1052
1053            ++iewDispLoadInsts;
1054
1055            add_to_iq = true;
1056
1057            toRename->iewInfo[tid].dispatchedToLSQ++;
1058        } else if (inst->isStore()) {
1059            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1060                    "encountered, adding to LSQ.\n", tid);
1061
1062            ldstQueue.insertStore(inst);
1063
1064            ++iewDispStoreInsts;
1065
1066            if (inst->isStoreConditional()) {
1067                // Store conditionals need to be set as "canCommit()"
1068                // so that commit can process them when they reach the
1069                // head of commit.
1070                // @todo: This is somewhat specific to Alpha.
1071                inst->setCanCommit();
1072                instQueue.insertNonSpec(inst);
1073                add_to_iq = false;
1074
1075                ++iewDispNonSpecInsts;
1076            } else {
1077                add_to_iq = true;
1078            }
1079
1080            toRename->iewInfo[tid].dispatchedToLSQ++;
1081        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1082            // Same as non-speculative stores.
1083            inst->setCanCommit();
1084            instQueue.insertBarrier(inst);
1085            add_to_iq = false;
1086        } else if (inst->isNop()) {
1087            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1088                    "skipping.\n", tid);
1089
1090            inst->setIssued();
1091            inst->setExecuted();
1092            inst->setCanCommit();
1093
1094            instQueue.recordProducer(inst);
1095
1096            iewExecutedNop[tid]++;
1097
1098            add_to_iq = false;
1099        } else if (inst->isExecuted()) {
1100            assert(0 && "Instruction shouldn't be executed.\n");
1101            DPRINTF(IEW, "Issue: Executed branch encountered, "
1102                    "skipping.\n");
1103
1104            inst->setIssued();
1105            inst->setCanCommit();
1106
1107            instQueue.recordProducer(inst);
1108
1109            add_to_iq = false;
1110        } else {
1111            add_to_iq = true;
1112        }
1113        if (inst->isNonSpeculative()) {
1114            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1115                    "encountered, skipping.\n", tid);
1116
1117            // Same as non-speculative stores.
1118            inst->setCanCommit();
1119
1120            // Specifically insert it as nonspeculative.
1121            instQueue.insertNonSpec(inst);
1122
1123            ++iewDispNonSpecInsts;
1124
1125            add_to_iq = false;
1126        }
1127
1128        // If the instruction queue is not full, then add the
1129        // instruction.
1130        if (add_to_iq) {
1131            instQueue.insert(inst);
1132        }
1133
1134        insts_to_dispatch.pop();
1135
1136        toRename->iewInfo[tid].dispatched++;
1137
1138        ++iewDispatchedInsts;
1139    }
1140
1141    if (!insts_to_dispatch.empty()) {
1142        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1143        block(tid);
1144        toRename->iewUnblock[tid] = false;
1145    }
1146
1147    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1148        dispatchStatus[tid] = Running;
1149
1150        updatedQueues = true;
1151    }
1152
1153    dis_num_inst = 0;
1154}
1155
1156template <class Impl>
1157void
1158DefaultIEW<Impl>::printAvailableInsts()
1159{
1160    int inst = 0;
1161
1162    std::cout << "Available Instructions: ";
1163
1164    while (fromIssue->insts[inst]) {
1165
1166        if (inst%3==0) std::cout << "\n\t";
1167
1168        std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1169             << " TN: " << fromIssue->insts[inst]->threadNumber
1170             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1171
1172        inst++;
1173
1174    }
1175
1176    std::cout << "\n";
1177}
1178
1179template <class Impl>
1180void
1181DefaultIEW<Impl>::executeInsts()
1182{
1183    wbNumInst = 0;
1184    wbCycle = 0;
1185
1186    list<ThreadID>::iterator threads = activeThreads->begin();
1187    list<ThreadID>::iterator end = activeThreads->end();
1188
1189    while (threads != end) {
1190        ThreadID tid = *threads++;
1191        fetchRedirect[tid] = false;
1192    }
1193
1194    // Uncomment this if you want to see all available instructions.
1195    // @todo This doesn't actually work anymore, we should fix it.
1196//    printAvailableInsts();
1197
1198    // Execute/writeback any instructions that are available.
1199    int insts_to_execute = fromIssue->size;
1200    int inst_num = 0;
1201    for (; inst_num < insts_to_execute;
1202          ++inst_num) {
1203
1204        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1205
1206        DynInstPtr inst = instQueue.getInstToExecute();
1207
1208        DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1209                inst->pcState(), inst->threadNumber,inst->seqNum);
1210
1211        // Check if the instruction is squashed; if so then skip it
1212        if (inst->isSquashed()) {
1213            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1214
1215            // Consider this instruction executed so that commit can go
1216            // ahead and retire the instruction.
1217            inst->setExecuted();
1218
1219            // Not sure if I should set this here or just let commit try to
1220            // commit any squashed instructions.  I like the latter a bit more.
1221            inst->setCanCommit();
1222
1223            ++iewExecSquashedInsts;
1224
1225            decrWb(inst->seqNum);
1226            continue;
1227        }
1228
1229        Fault fault = NoFault;
1230
1231        // Execute instruction.
1232        // Note that if the instruction faults, it will be handled
1233        // at the commit stage.
1234        if (inst->isMemRef()) {
1235            DPRINTF(IEW, "Execute: Calculating address for memory "
1236                    "reference.\n");
1237
1238            // Tell the LDSTQ to execute this instruction (if it is a load).
1239            if (inst->isLoad()) {
1240                // Loads will mark themselves as executed, and their writeback
1241                // event adds the instruction to the queue to commit
1242                fault = ldstQueue.executeLoad(inst);
1243
1244                if (inst->isTranslationDelayed() &&
1245                    fault == NoFault) {
1246                    // A hw page table walk is currently going on; the
1247                    // instruction must be deferred.
1248                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1249                            "load.\n");
1250                    instQueue.deferMemInst(inst);
1251                    continue;
1252                }
1253
1254                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1255                    inst->fault = NoFault;
1256                }
1257            } else if (inst->isStore()) {
1258                fault = ldstQueue.executeStore(inst);
1259
1260                if (inst->isTranslationDelayed() &&
1261                    fault == NoFault) {
1262                    // A hw page table walk is currently going on; the
1263                    // instruction must be deferred.
1264                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1265                            "store.\n");
1266                    instQueue.deferMemInst(inst);
1267                    continue;
1268                }
1269
1270                // If the store had a fault then it may not have a mem req
1271                if (fault != NoFault || inst->readPredicate() == false ||
1272                        !inst->isStoreConditional()) {
1273                    // If the instruction faulted, then we need to send it along
1274                    // to commit without the instruction completing.
1275                    // Send this instruction to commit, also make sure iew stage
1276                    // realizes there is activity.
1277                    inst->setExecuted();
1278                    instToCommit(inst);
1279                    activityThisCycle();
1280                }
1281
1282                // Store conditionals will mark themselves as
1283                // executed, and their writeback event will add the
1284                // instruction to the queue to commit.
1285            } else {
1286                panic("Unexpected memory type!\n");
1287            }
1288
1289        } else {
1290            // If the instruction has already faulted, then skip executing it.
1291            // Such case can happen when it faulted during ITLB translation.
1292            // If we execute the instruction (even if it's a nop) the fault
1293            // will be replaced and we will lose it.
1294            if (inst->getFault() == NoFault) {
1295                inst->execute();
1296                if (inst->readPredicate() == false)
1297                    inst->forwardOldRegs();
1298            }
1299
1300            inst->setExecuted();
1301
1302            instToCommit(inst);
1303        }
1304
1305        updateExeInstStats(inst);
1306
1307        // Check if branch prediction was correct, if not then we need
1308        // to tell commit to squash in flight instructions.  Only
1309        // handle this if there hasn't already been something that
1310        // redirects fetch in this group of instructions.
1311
1312        // This probably needs to prioritize the redirects if a different
1313        // scheduler is used.  Currently the scheduler schedules the oldest
1314        // instruction first, so the branch resolution order will be correct.
1315        ThreadID tid = inst->threadNumber;
1316
1317        if (!fetchRedirect[tid] ||
1318            !toCommit->squash[tid] ||
1319            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1320
1321            // Prevent testing for misprediction on load instructions,
1322            // that have not been executed.
1323            bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1324
1325            if (inst->mispredicted() && !loadNotExecuted) {
1326                fetchRedirect[tid] = true;
1327
1328                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1329                DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1330                        inst->predInstAddr(), inst->predNextInstAddr());
1331                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1332                        inst->pcState(), inst->nextInstAddr());
1333                // If incorrect, then signal the ROB that it must be squashed.
1334                squashDueToBranch(inst, tid);
1335
1336                if (inst->readPredTaken()) {
1337                    predictedTakenIncorrect++;
1338                } else {
1339                    predictedNotTakenIncorrect++;
1340                }
1341            } else if (ldstQueue.violation(tid)) {
1342                assert(inst->isMemRef());
1343                // If there was an ordering violation, then get the
1344                // DynInst that caused the violation.  Note that this
1345                // clears the violation signal.
1346                DynInstPtr violator;
1347                violator = ldstQueue.getMemDepViolator(tid);
1348
1349                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1350                        "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1351                        violator->pcState(), violator->seqNum,
1352                        inst->pcState(), inst->seqNum, inst->physEffAddr);
1353
1354                fetchRedirect[tid] = true;
1355
1356                // Tell the instruction queue that a violation has occured.
1357                instQueue.violation(inst, violator);
1358
1359                // Squash.
1360                squashDueToMemOrder(inst,tid);
1361
1362                ++memOrderViolationEvents;
1363            } else if (ldstQueue.loadBlocked(tid) &&
1364                       !ldstQueue.isLoadBlockedHandled(tid)) {
1365                fetchRedirect[tid] = true;
1366
1367                DPRINTF(IEW, "Load operation couldn't execute because the "
1368                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1369                        inst->pcState(), inst->seqNum);
1370
1371                squashDueToMemBlocked(inst, tid);
1372            }
1373        } else {
1374            // Reset any state associated with redirects that will not
1375            // be used.
1376            if (ldstQueue.violation(tid)) {
1377                assert(inst->isMemRef());
1378
1379                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1380
1381                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1382                        "%s, inst PC: %s.  Addr is: %#x.\n",
1383                        violator->pcState(), inst->pcState(),
1384                        inst->physEffAddr);
1385                DPRINTF(IEW, "Violation will not be handled because "
1386                        "already squashing\n");
1387
1388                ++memOrderViolationEvents;
1389            }
1390            if (ldstQueue.loadBlocked(tid) &&
1391                !ldstQueue.isLoadBlockedHandled(tid)) {
1392                DPRINTF(IEW, "Load operation couldn't execute because the "
1393                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1394                        inst->pcState(), inst->seqNum);
1395                DPRINTF(IEW, "Blocked load will not be handled because "
1396                        "already squashing\n");
1397
1398                ldstQueue.setLoadBlockedHandled(tid);
1399            }
1400
1401        }
1402    }
1403
1404    // Update and record activity if we processed any instructions.
1405    if (inst_num) {
1406        if (exeStatus == Idle) {
1407            exeStatus = Running;
1408        }
1409
1410        updatedQueues = true;
1411
1412        cpu->activityThisCycle();
1413    }
1414
1415    // Need to reset this in case a writeback event needs to write into the
1416    // iew queue.  That way the writeback event will write into the correct
1417    // spot in the queue.
1418    wbNumInst = 0;
1419
1420}
1421
1422template <class Impl>
1423void
1424DefaultIEW<Impl>::writebackInsts()
1425{
1426    // Loop through the head of the time buffer and wake any
1427    // dependents.  These instructions are about to write back.  Also
1428    // mark scoreboard that this instruction is finally complete.
1429    // Either have IEW have direct access to scoreboard, or have this
1430    // as part of backwards communication.
1431    for (int inst_num = 0; inst_num < wbWidth &&
1432             toCommit->insts[inst_num]; inst_num++) {
1433        DynInstPtr inst = toCommit->insts[inst_num];
1434        ThreadID tid = inst->threadNumber;
1435
1436        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1437                inst->seqNum, inst->pcState());
1438
1439        iewInstsToCommit[tid]++;
1440
1441        // Some instructions will be sent to commit without having
1442        // executed because they need commit to handle them.
1443        // E.g. Uncached loads have not actually executed when they
1444        // are first sent to commit.  Instead commit must tell the LSQ
1445        // when it's ready to execute the uncached load.
1446        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1447            int dependents = instQueue.wakeDependents(inst);
1448
1449            for (int i = 0; i < inst->numDestRegs(); i++) {
1450                //mark as Ready
1451                DPRINTF(IEW,"Setting Destination Register %i\n",
1452                        inst->renamedDestRegIdx(i));
1453                scoreboard->setReg(inst->renamedDestRegIdx(i));
1454            }
1455
1456            if (dependents) {
1457                producerInst[tid]++;
1458                consumerInst[tid]+= dependents;
1459            }
1460            writebackCount[tid]++;
1461        }
1462
1463        decrWb(inst->seqNum);
1464    }
1465}
1466
1467template<class Impl>
1468void
1469DefaultIEW<Impl>::tick()
1470{
1471    wbNumInst = 0;
1472    wbCycle = 0;
1473
1474    wroteToTimeBuffer = false;
1475    updatedQueues = false;
1476
1477    sortInsts();
1478
1479    // Free function units marked as being freed this cycle.
1480    fuPool->processFreeUnits();
1481
1482    list<ThreadID>::iterator threads = activeThreads->begin();
1483    list<ThreadID>::iterator end = activeThreads->end();
1484
1485    // Check stall and squash signals, dispatch any instructions.
1486    while (threads != end) {
1487        ThreadID tid = *threads++;
1488
1489        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1490
1491        checkSignalsAndUpdate(tid);
1492        dispatch(tid);
1493    }
1494
1495    if (exeStatus != Squashing) {
1496        executeInsts();
1497
1498        writebackInsts();
1499
1500        // Have the instruction queue try to schedule any ready instructions.
1501        // (In actuality, this scheduling is for instructions that will
1502        // be executed next cycle.)
1503        instQueue.scheduleReadyInsts();
1504
1505        // Also should advance its own time buffers if the stage ran.
1506        // Not the best place for it, but this works (hopefully).
1507        issueToExecQueue.advance();
1508    }
1509
1510    bool broadcast_free_entries = false;
1511
1512    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1513        exeStatus = Idle;
1514        updateLSQNextCycle = false;
1515
1516        broadcast_free_entries = true;
1517    }
1518
1519    // Writeback any stores using any leftover bandwidth.
1520    ldstQueue.writebackStores();
1521
1522    // Check the committed load/store signals to see if there's a load
1523    // or store to commit.  Also check if it's being told to execute a
1524    // nonspeculative instruction.
1525    // This is pretty inefficient...
1526
1527    threads = activeThreads->begin();
1528    while (threads != end) {
1529        ThreadID tid = (*threads++);
1530
1531        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1532
1533        // Update structures based on instructions committed.
1534        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1535            !fromCommit->commitInfo[tid].squash &&
1536            !fromCommit->commitInfo[tid].robSquashing) {
1537
1538            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1539
1540            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1541
1542            updateLSQNextCycle = true;
1543            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1544        }
1545
1546        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1547
1548            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1549            if (fromCommit->commitInfo[tid].uncached) {
1550                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1551                fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1552            } else {
1553                instQueue.scheduleNonSpec(
1554                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1555            }
1556        }
1557
1558        if (broadcast_free_entries) {
1559            toFetch->iewInfo[tid].iqCount =
1560                instQueue.getCount(tid);
1561            toFetch->iewInfo[tid].ldstqCount =
1562                ldstQueue.getCount(tid);
1563
1564            toRename->iewInfo[tid].usedIQ = true;
1565            toRename->iewInfo[tid].freeIQEntries =
1566                instQueue.numFreeEntries();
1567            toRename->iewInfo[tid].usedLSQ = true;
1568            toRename->iewInfo[tid].freeLSQEntries =
1569                ldstQueue.numFreeEntries(tid);
1570
1571            wroteToTimeBuffer = true;
1572        }
1573
1574        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1575                tid, toRename->iewInfo[tid].dispatched);
1576    }
1577
1578    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1579            "LSQ has %i free entries.\n",
1580            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1581            ldstQueue.numFreeEntries());
1582
1583    updateStatus();
1584
1585    if (wroteToTimeBuffer) {
1586        DPRINTF(Activity, "Activity this cycle.\n");
1587        cpu->activityThisCycle();
1588    }
1589}
1590
1591template <class Impl>
1592void
1593DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1594{
1595    ThreadID tid = inst->threadNumber;
1596
1597    //
1598    //  Pick off the software prefetches
1599    //
1600#ifdef TARGET_ALPHA
1601    if (inst->isDataPrefetch())
1602        iewExecutedSwp[tid]++;
1603    else
1604        iewIewExecutedcutedInsts++;
1605#else
1606    iewExecutedInsts++;
1607#endif
1608
1609    //
1610    //  Control operations
1611    //
1612    if (inst->isControl())
1613        iewExecutedBranches[tid]++;
1614
1615    //
1616    //  Memory operations
1617    //
1618    if (inst->isMemRef()) {
1619        iewExecutedRefs[tid]++;
1620
1621        if (inst->isLoad()) {
1622            iewExecLoadInsts[tid]++;
1623        }
1624    }
1625}
1626
1627template <class Impl>
1628void
1629DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1630{
1631    ThreadID tid = inst->threadNumber;
1632
1633    if (!fetchRedirect[tid] ||
1634        !toCommit->squash[tid] ||
1635        toCommit->squashedSeqNum[tid] > inst->seqNum) {
1636
1637        if (inst->mispredicted()) {
1638            fetchRedirect[tid] = true;
1639
1640            DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1641            DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1642                    inst->predInstAddr(), inst->predNextInstAddr());
1643            DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1644                    " NPC: %#x.\n", inst->nextInstAddr(),
1645                    inst->nextInstAddr());
1646            // If incorrect, then signal the ROB that it must be squashed.
1647            squashDueToBranch(inst, tid);
1648
1649            if (inst->readPredTaken()) {
1650                predictedTakenIncorrect++;
1651            } else {
1652                predictedNotTakenIncorrect++;
1653            }
1654        }
1655    }
1656}
1657