iew_impl.hh revision 3969 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew.  There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41template<class Impl>
42DefaultIEW<Impl>::DefaultIEW(Params *params)
43    : issueToExecQueue(params->backComSize, params->forwardComSize),
44      instQueue(params),
45      ldstQueue(params),
46      fuPool(params->fuPool),
47      commitToIEWDelay(params->commitToIEWDelay),
48      renameToIEWDelay(params->renameToIEWDelay),
49      issueToExecuteDelay(params->issueToExecuteDelay),
50      dispatchWidth(params->dispatchWidth),
51      issueWidth(params->issueWidth),
52      wbOutstanding(0),
53      wbWidth(params->wbWidth),
54      numThreads(params->numberOfThreads),
55      switchedOut(false)
56{
57    _status = Active;
58    exeStatus = Running;
59    wbStatus = Idle;
60
61    // Setup wire to read instructions coming from issue.
62    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
63
64    // Instruction queue needs the queue between issue and execute.
65    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
66
67    instQueue.setIEW(this);
68    ldstQueue.setIEW(this);
69
70    for (int i=0; i < numThreads; i++) {
71        dispatchStatus[i] = Running;
72        stalls[i].commit = false;
73        fetchRedirect[i] = false;
74        bdelayDoneSeqNum[i] = 0;
75    }
76
77    wbMax = wbWidth * params->wbDepth;
78
79    updateLSQNextCycle = false;
80
81    ableToIssue = true;
82
83    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
84}
85
86template <class Impl>
87std::string
88DefaultIEW<Impl>::name() const
89{
90    return cpu->name() + ".iew";
91}
92
93template <class Impl>
94void
95DefaultIEW<Impl>::regStats()
96{
97    using namespace Stats;
98
99    instQueue.regStats();
100    ldstQueue.regStats();
101
102    iewIdleCycles
103        .name(name() + ".iewIdleCycles")
104        .desc("Number of cycles IEW is idle");
105
106    iewSquashCycles
107        .name(name() + ".iewSquashCycles")
108        .desc("Number of cycles IEW is squashing");
109
110    iewBlockCycles
111        .name(name() + ".iewBlockCycles")
112        .desc("Number of cycles IEW is blocking");
113
114    iewUnblockCycles
115        .name(name() + ".iewUnblockCycles")
116        .desc("Number of cycles IEW is unblocking");
117
118    iewDispatchedInsts
119        .name(name() + ".iewDispatchedInsts")
120        .desc("Number of instructions dispatched to IQ");
121
122    iewDispSquashedInsts
123        .name(name() + ".iewDispSquashedInsts")
124        .desc("Number of squashed instructions skipped by dispatch");
125
126    iewDispLoadInsts
127        .name(name() + ".iewDispLoadInsts")
128        .desc("Number of dispatched load instructions");
129
130    iewDispStoreInsts
131        .name(name() + ".iewDispStoreInsts")
132        .desc("Number of dispatched store instructions");
133
134    iewDispNonSpecInsts
135        .name(name() + ".iewDispNonSpecInsts")
136        .desc("Number of dispatched non-speculative instructions");
137
138    iewIQFullEvents
139        .name(name() + ".iewIQFullEvents")
140        .desc("Number of times the IQ has become full, causing a stall");
141
142    iewLSQFullEvents
143        .name(name() + ".iewLSQFullEvents")
144        .desc("Number of times the LSQ has become full, causing a stall");
145
146    memOrderViolationEvents
147        .name(name() + ".memOrderViolationEvents")
148        .desc("Number of memory order violations");
149
150    predictedTakenIncorrect
151        .name(name() + ".predictedTakenIncorrect")
152        .desc("Number of branches that were predicted taken incorrectly");
153
154    predictedNotTakenIncorrect
155        .name(name() + ".predictedNotTakenIncorrect")
156        .desc("Number of branches that were predicted not taken incorrectly");
157
158    branchMispredicts
159        .name(name() + ".branchMispredicts")
160        .desc("Number of branch mispredicts detected at execute");
161
162    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
163
164    iewExecutedInsts
165        .name(name() + ".iewExecutedInsts")
166        .desc("Number of executed instructions");
167
168    iewExecLoadInsts
169        .init(cpu->number_of_threads)
170        .name(name() + ".iewExecLoadInsts")
171        .desc("Number of load instructions executed")
172        .flags(total);
173
174    iewExecSquashedInsts
175        .name(name() + ".iewExecSquashedInsts")
176        .desc("Number of squashed instructions skipped in execute");
177
178    iewExecutedSwp
179        .init(cpu->number_of_threads)
180        .name(name() + ".EXEC:swp")
181        .desc("number of swp insts executed")
182        .flags(total);
183
184    iewExecutedNop
185        .init(cpu->number_of_threads)
186        .name(name() + ".EXEC:nop")
187        .desc("number of nop insts executed")
188        .flags(total);
189
190    iewExecutedRefs
191        .init(cpu->number_of_threads)
192        .name(name() + ".EXEC:refs")
193        .desc("number of memory reference insts executed")
194        .flags(total);
195
196    iewExecutedBranches
197        .init(cpu->number_of_threads)
198        .name(name() + ".EXEC:branches")
199        .desc("Number of branches executed")
200        .flags(total);
201
202    iewExecStoreInsts
203        .name(name() + ".EXEC:stores")
204        .desc("Number of stores executed")
205        .flags(total);
206    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
207
208    iewExecRate
209        .name(name() + ".EXEC:rate")
210        .desc("Inst execution rate")
211        .flags(total);
212
213    iewExecRate = iewExecutedInsts / cpu->numCycles;
214
215    iewInstsToCommit
216        .init(cpu->number_of_threads)
217        .name(name() + ".WB:sent")
218        .desc("cumulative count of insts sent to commit")
219        .flags(total);
220
221    writebackCount
222        .init(cpu->number_of_threads)
223        .name(name() + ".WB:count")
224        .desc("cumulative count of insts written-back")
225        .flags(total);
226
227    producerInst
228        .init(cpu->number_of_threads)
229        .name(name() + ".WB:producers")
230        .desc("num instructions producing a value")
231        .flags(total);
232
233    consumerInst
234        .init(cpu->number_of_threads)
235        .name(name() + ".WB:consumers")
236        .desc("num instructions consuming a value")
237        .flags(total);
238
239    wbPenalized
240        .init(cpu->number_of_threads)
241        .name(name() + ".WB:penalized")
242        .desc("number of instrctions required to write to 'other' IQ")
243        .flags(total);
244
245    wbPenalizedRate
246        .name(name() + ".WB:penalized_rate")
247        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
248        .flags(total);
249
250    wbPenalizedRate = wbPenalized / writebackCount;
251
252    wbFanout
253        .name(name() + ".WB:fanout")
254        .desc("average fanout of values written-back")
255        .flags(total);
256
257    wbFanout = producerInst / consumerInst;
258
259    wbRate
260        .name(name() + ".WB:rate")
261        .desc("insts written-back per cycle")
262        .flags(total);
263    wbRate = writebackCount / cpu->numCycles;
264}
265
266template<class Impl>
267void
268DefaultIEW<Impl>::initStage()
269{
270    for (int tid=0; tid < numThreads; tid++) {
271        toRename->iewInfo[tid].usedIQ = true;
272        toRename->iewInfo[tid].freeIQEntries =
273            instQueue.numFreeEntries(tid);
274
275        toRename->iewInfo[tid].usedLSQ = true;
276        toRename->iewInfo[tid].freeLSQEntries =
277            ldstQueue.numFreeEntries(tid);
278    }
279}
280
281template<class Impl>
282void
283DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
284{
285    DPRINTF(IEW, "Setting CPU pointer.\n");
286    cpu = cpu_ptr;
287
288    instQueue.setCPU(cpu_ptr);
289    ldstQueue.setCPU(cpu_ptr);
290
291    cpu->activateStage(O3CPU::IEWIdx);
292}
293
294template<class Impl>
295void
296DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
297{
298    DPRINTF(IEW, "Setting time buffer pointer.\n");
299    timeBuffer = tb_ptr;
300
301    // Setup wire to read information from time buffer, from commit.
302    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
303
304    // Setup wire to write information back to previous stages.
305    toRename = timeBuffer->getWire(0);
306
307    toFetch = timeBuffer->getWire(0);
308
309    // Instruction queue also needs main time buffer.
310    instQueue.setTimeBuffer(tb_ptr);
311}
312
313template<class Impl>
314void
315DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
316{
317    DPRINTF(IEW, "Setting rename queue pointer.\n");
318    renameQueue = rq_ptr;
319
320    // Setup wire to read information from rename queue.
321    fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328    DPRINTF(IEW, "Setting IEW queue pointer.\n");
329    iewQueue = iq_ptr;
330
331    // Setup wire to write instructions to commit.
332    toCommit = iewQueue->getWire(0);
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
338{
339    DPRINTF(IEW, "Setting active threads list pointer.\n");
340    activeThreads = at_ptr;
341
342    ldstQueue.setActiveThreads(at_ptr);
343    instQueue.setActiveThreads(at_ptr);
344}
345
346template<class Impl>
347void
348DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
349{
350    DPRINTF(IEW, "Setting scoreboard pointer.\n");
351    scoreboard = sb_ptr;
352}
353
354template <class Impl>
355bool
356DefaultIEW<Impl>::drain()
357{
358    // IEW is ready to drain at any time.
359    cpu->signalDrained();
360    return true;
361}
362
363template <class Impl>
364void
365DefaultIEW<Impl>::resume()
366{
367}
368
369template <class Impl>
370void
371DefaultIEW<Impl>::switchOut()
372{
373    // Clear any state.
374    switchedOut = true;
375    assert(insts[0].empty());
376    assert(skidBuffer[0].empty());
377
378    instQueue.switchOut();
379    ldstQueue.switchOut();
380    fuPool->switchOut();
381
382    for (int i = 0; i < numThreads; i++) {
383        while (!insts[i].empty())
384            insts[i].pop();
385        while (!skidBuffer[i].empty())
386            skidBuffer[i].pop();
387    }
388}
389
390template <class Impl>
391void
392DefaultIEW<Impl>::takeOverFrom()
393{
394    // Reset all state.
395    _status = Active;
396    exeStatus = Running;
397    wbStatus = Idle;
398    switchedOut = false;
399
400    instQueue.takeOverFrom();
401    ldstQueue.takeOverFrom();
402    fuPool->takeOverFrom();
403
404    initStage();
405    cpu->activityThisCycle();
406
407    for (int i=0; i < numThreads; i++) {
408        dispatchStatus[i] = Running;
409        stalls[i].commit = false;
410        fetchRedirect[i] = false;
411    }
412
413    updateLSQNextCycle = false;
414
415    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
416        issueToExecQueue.advance();
417    }
418}
419
420template<class Impl>
421void
422DefaultIEW<Impl>::squash(unsigned tid)
423{
424    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
425            tid);
426
427    // Tell the IQ to start squashing.
428    instQueue.squash(tid);
429
430    // Tell the LDSTQ to start squashing.
431#if ISA_HAS_DELAY_SLOT
432    ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
433#else
434    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
435#endif
436    updatedQueues = true;
437
438    // Clear the skid buffer in case it has any data in it.
439    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
440            tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
441
442    while (!skidBuffer[tid].empty()) {
443#if ISA_HAS_DELAY_SLOT
444        if (skidBuffer[tid].front()->seqNum <=
445            fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
446            DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
447                    "that occur before delay slot [sn:%i].\n",
448                    fromCommit->commitInfo[tid].bdelayDoneSeqNum,
449                    tid);
450            break;
451        } else {
452            DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
453                    "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
454        }
455#endif
456        if (skidBuffer[tid].front()->isLoad() ||
457            skidBuffer[tid].front()->isStore() ) {
458            toRename->iewInfo[tid].dispatchedToLSQ++;
459        }
460
461        toRename->iewInfo[tid].dispatched++;
462
463        skidBuffer[tid].pop();
464    }
465
466    bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
467
468    emptyRenameInsts(tid);
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
474{
475    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476            "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478    toCommit->squash[tid] = true;
479    toCommit->squashedSeqNum[tid] = inst->seqNum;
480    toCommit->mispredPC[tid] = inst->readPC();
481    toCommit->branchMispredict[tid] = true;
482
483    int instSize = sizeof(TheISA::MachInst);
484#if ISA_HAS_DELAY_SLOT
485    bool branch_taken =
486        !(inst->readNextPC() + instSize == inst->readNextNPC() &&
487          (inst->readNextPC() == inst->readPC() + instSize ||
488           inst->readNextPC() == inst->readPC() + 2 * instSize));
489    DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
490            branch_taken ? "true": "false", inst->seqNum);
491
492    toCommit->branchTaken[tid] = branch_taken;
493
494    bool squashDelaySlot = true;
495//	(inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst));
496    DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n",
497            squashDelaySlot ? "true": "false", inst->seqNum);
498    toCommit->squashDelaySlot[tid] = squashDelaySlot;
499    //If we're squashing the delay slot, we need to pick back up at NextPC.
500    //Otherwise, NextPC isn't being squashed, so we should pick back up at
501    //NextNPC.
502    if (squashDelaySlot) {
503        toCommit->nextPC[tid] = inst->readNextPC();
504        toCommit->nextNPC[tid] = inst->readNextNPC();
505    } else {
506        toCommit->nextPC[tid] = inst->readNextNPC();
507        toCommit->nextNPC[tid] = inst->readNextNPC() + instSize;
508    }
509#else
510    toCommit->branchTaken[tid] = inst->readNextPC() !=
511        (inst->readPC() + sizeof(TheISA::MachInst));
512    toCommit->nextPC[tid] = inst->readNextPC();
513    toCommit->nextNPC[tid] = inst->readNextPC() + instSize;
514#endif
515
516    toCommit->includeSquashInst[tid] = false;
517
518    wroteToTimeBuffer = true;
519}
520
521template<class Impl>
522void
523DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
524{
525    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
526            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
527
528    toCommit->squash[tid] = true;
529    toCommit->squashedSeqNum[tid] = inst->seqNum;
530    toCommit->nextPC[tid] = inst->readNextPC();
531#if ISA_HAS_DELAY_SLOT
532    toCommit->nextNPC[tid] = inst->readNextNPC();
533#else
534    toCommit->nextNPC[tid] = inst->readNextPC() + sizeof(TheISA::MachInst);
535#endif
536    toCommit->branchMispredict[tid] = false;
537
538    toCommit->includeSquashInst[tid] = false;
539
540    wroteToTimeBuffer = true;
541}
542
543template<class Impl>
544void
545DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
546{
547    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
548            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
549
550    toCommit->squash[tid] = true;
551    toCommit->squashedSeqNum[tid] = inst->seqNum;
552    toCommit->nextPC[tid] = inst->readPC();
553#if ISA_HAS_DELAY_SLOT
554    toCommit->nextNPC[tid] = inst->readNextPC();
555#else
556    toCommit->nextNPC[tid] = inst->readPC() + sizeof(TheISA::MachInst);
557#endif
558    toCommit->branchMispredict[tid] = false;
559
560    // Must include the broadcasted SN in the squash.
561    toCommit->includeSquashInst[tid] = true;
562
563    ldstQueue.setLoadBlockedHandled(tid);
564
565    wroteToTimeBuffer = true;
566}
567
568template<class Impl>
569void
570DefaultIEW<Impl>::block(unsigned tid)
571{
572    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
573
574    if (dispatchStatus[tid] != Blocked &&
575        dispatchStatus[tid] != Unblocking) {
576        toRename->iewBlock[tid] = true;
577        wroteToTimeBuffer = true;
578    }
579
580    // Add the current inputs to the skid buffer so they can be
581    // reprocessed when this stage unblocks.
582    skidInsert(tid);
583
584    dispatchStatus[tid] = Blocked;
585}
586
587template<class Impl>
588void
589DefaultIEW<Impl>::unblock(unsigned tid)
590{
591    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
592            "buffer %u.\n",tid, tid);
593
594    // If the skid bufffer is empty, signal back to previous stages to unblock.
595    // Also switch status to running.
596    if (skidBuffer[tid].empty()) {
597        toRename->iewUnblock[tid] = true;
598        wroteToTimeBuffer = true;
599        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
600        dispatchStatus[tid] = Running;
601    }
602}
603
604template<class Impl>
605void
606DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
607{
608    instQueue.wakeDependents(inst);
609}
610
611template<class Impl>
612void
613DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
614{
615    instQueue.rescheduleMemInst(inst);
616}
617
618template<class Impl>
619void
620DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
621{
622    instQueue.replayMemInst(inst);
623}
624
625template<class Impl>
626void
627DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
628{
629    // This function should not be called after writebackInsts in a
630    // single cycle.  That will cause problems with an instruction
631    // being added to the queue to commit without being processed by
632    // writebackInsts prior to being sent to commit.
633
634    // First check the time slot that this instruction will write
635    // to.  If there are free write ports at the time, then go ahead
636    // and write the instruction to that time.  If there are not,
637    // keep looking back to see where's the first time there's a
638    // free slot.
639    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
640        ++wbNumInst;
641        if (wbNumInst == wbWidth) {
642            ++wbCycle;
643            wbNumInst = 0;
644        }
645
646        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
647    }
648
649    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
650            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
651    // Add finished instruction to queue to commit.
652    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
653    (*iewQueue)[wbCycle].size++;
654}
655
656template <class Impl>
657unsigned
658DefaultIEW<Impl>::validInstsFromRename()
659{
660    unsigned inst_count = 0;
661
662    for (int i=0; i<fromRename->size; i++) {
663        if (!fromRename->insts[i]->isSquashed())
664            inst_count++;
665    }
666
667    return inst_count;
668}
669
670template<class Impl>
671void
672DefaultIEW<Impl>::skidInsert(unsigned tid)
673{
674    DynInstPtr inst = NULL;
675
676    while (!insts[tid].empty()) {
677        inst = insts[tid].front();
678
679        insts[tid].pop();
680
681        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
682                "dispatch skidBuffer %i\n",tid, inst->seqNum,
683                inst->readPC(),tid);
684
685        skidBuffer[tid].push(inst);
686    }
687
688    assert(skidBuffer[tid].size() <= skidBufferMax &&
689           "Skidbuffer Exceeded Max Size");
690}
691
692template<class Impl>
693int
694DefaultIEW<Impl>::skidCount()
695{
696    int max=0;
697
698    std::list<unsigned>::iterator threads = (*activeThreads).begin();
699
700    while (threads != (*activeThreads).end()) {
701        unsigned thread_count = skidBuffer[*threads++].size();
702        if (max < thread_count)
703            max = thread_count;
704    }
705
706    return max;
707}
708
709template<class Impl>
710bool
711DefaultIEW<Impl>::skidsEmpty()
712{
713    std::list<unsigned>::iterator threads = (*activeThreads).begin();
714
715    while (threads != (*activeThreads).end()) {
716        if (!skidBuffer[*threads++].empty())
717            return false;
718    }
719
720    return true;
721}
722
723template <class Impl>
724void
725DefaultIEW<Impl>::updateStatus()
726{
727    bool any_unblocking = false;
728
729    std::list<unsigned>::iterator threads = (*activeThreads).begin();
730
731    threads = (*activeThreads).begin();
732
733    while (threads != (*activeThreads).end()) {
734        unsigned tid = *threads++;
735
736        if (dispatchStatus[tid] == Unblocking) {
737            any_unblocking = true;
738            break;
739        }
740    }
741
742    // If there are no ready instructions waiting to be scheduled by the IQ,
743    // and there's no stores waiting to write back, and dispatch is not
744    // unblocking, then there is no internal activity for the IEW stage.
745    if (_status == Active && !instQueue.hasReadyInsts() &&
746        !ldstQueue.willWB() && !any_unblocking) {
747        DPRINTF(IEW, "IEW switching to idle\n");
748
749        deactivateStage();
750
751        _status = Inactive;
752    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
753                                       ldstQueue.willWB() ||
754                                       any_unblocking)) {
755        // Otherwise there is internal activity.  Set to active.
756        DPRINTF(IEW, "IEW switching to active\n");
757
758        activateStage();
759
760        _status = Active;
761    }
762}
763
764template <class Impl>
765void
766DefaultIEW<Impl>::resetEntries()
767{
768    instQueue.resetEntries();
769    ldstQueue.resetEntries();
770}
771
772template <class Impl>
773void
774DefaultIEW<Impl>::readStallSignals(unsigned tid)
775{
776    if (fromCommit->commitBlock[tid]) {
777        stalls[tid].commit = true;
778    }
779
780    if (fromCommit->commitUnblock[tid]) {
781        assert(stalls[tid].commit);
782        stalls[tid].commit = false;
783    }
784}
785
786template <class Impl>
787bool
788DefaultIEW<Impl>::checkStall(unsigned tid)
789{
790    bool ret_val(false);
791
792    if (stalls[tid].commit) {
793        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
794        ret_val = true;
795    } else if (instQueue.isFull(tid)) {
796        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
797        ret_val = true;
798    } else if (ldstQueue.isFull(tid)) {
799        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
800
801        if (ldstQueue.numLoads(tid) > 0 ) {
802
803            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
804                    tid,ldstQueue.getLoadHeadSeqNum(tid));
805        }
806
807        if (ldstQueue.numStores(tid) > 0) {
808
809            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
810                    tid,ldstQueue.getStoreHeadSeqNum(tid));
811        }
812
813        ret_val = true;
814    } else if (ldstQueue.isStalled(tid)) {
815        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
816        ret_val = true;
817    }
818
819    return ret_val;
820}
821
822template <class Impl>
823void
824DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
825{
826    // Check if there's a squash signal, squash if there is
827    // Check stall signals, block if there is.
828    // If status was Blocked
829    //     if so then go to unblocking
830    // If status was Squashing
831    //     check if squashing is not high.  Switch to running this cycle.
832
833    readStallSignals(tid);
834
835    if (fromCommit->commitInfo[tid].squash) {
836        squash(tid);
837
838        if (dispatchStatus[tid] == Blocked ||
839            dispatchStatus[tid] == Unblocking) {
840            toRename->iewUnblock[tid] = true;
841            wroteToTimeBuffer = true;
842        }
843
844        dispatchStatus[tid] = Squashing;
845
846        fetchRedirect[tid] = false;
847        return;
848    }
849
850    if (fromCommit->commitInfo[tid].robSquashing) {
851        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
852
853        dispatchStatus[tid] = Squashing;
854
855        emptyRenameInsts(tid);
856        wroteToTimeBuffer = true;
857        return;
858    }
859
860    if (checkStall(tid)) {
861        block(tid);
862        dispatchStatus[tid] = Blocked;
863        return;
864    }
865
866    if (dispatchStatus[tid] == Blocked) {
867        // Status from previous cycle was blocked, but there are no more stall
868        // conditions.  Switch over to unblocking.
869        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
870                tid);
871
872        dispatchStatus[tid] = Unblocking;
873
874        unblock(tid);
875
876        return;
877    }
878
879    if (dispatchStatus[tid] == Squashing) {
880        // Switch status to running if rename isn't being told to block or
881        // squash this cycle.
882        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
883                tid);
884
885        dispatchStatus[tid] = Running;
886
887        return;
888    }
889}
890
891template <class Impl>
892void
893DefaultIEW<Impl>::sortInsts()
894{
895    int insts_from_rename = fromRename->size;
896#ifdef DEBUG
897#if !ISA_HAS_DELAY_SLOT
898    for (int i = 0; i < numThreads; i++)
899        assert(insts[i].empty());
900#endif
901#endif
902    for (int i = 0; i < insts_from_rename; ++i) {
903        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
904    }
905}
906
907template <class Impl>
908void
909DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
910{
911    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
912            "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
913
914    while (!insts[tid].empty()) {
915#if ISA_HAS_DELAY_SLOT
916        if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
917            DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
918                    " that occurs at or before delay slot [sn:%i].\n",
919                    tid, bdelayDoneSeqNum[tid]);
920            break;
921        } else {
922            DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
923                    "[sn:%i].\n", tid, insts[tid].front()->seqNum);
924        }
925#endif
926
927        if (insts[tid].front()->isLoad() ||
928            insts[tid].front()->isStore() ) {
929            toRename->iewInfo[tid].dispatchedToLSQ++;
930        }
931
932        toRename->iewInfo[tid].dispatched++;
933
934        insts[tid].pop();
935    }
936}
937
938template <class Impl>
939void
940DefaultIEW<Impl>::wakeCPU()
941{
942    cpu->wakeCPU();
943}
944
945template <class Impl>
946void
947DefaultIEW<Impl>::activityThisCycle()
948{
949    DPRINTF(Activity, "Activity this cycle.\n");
950    cpu->activityThisCycle();
951}
952
953template <class Impl>
954inline void
955DefaultIEW<Impl>::activateStage()
956{
957    DPRINTF(Activity, "Activating stage.\n");
958    cpu->activateStage(O3CPU::IEWIdx);
959}
960
961template <class Impl>
962inline void
963DefaultIEW<Impl>::deactivateStage()
964{
965    DPRINTF(Activity, "Deactivating stage.\n");
966    cpu->deactivateStage(O3CPU::IEWIdx);
967}
968
969template<class Impl>
970void
971DefaultIEW<Impl>::dispatch(unsigned tid)
972{
973    // If status is Running or idle,
974    //     call dispatchInsts()
975    // If status is Unblocking,
976    //     buffer any instructions coming from rename
977    //     continue trying to empty skid buffer
978    //     check if stall conditions have passed
979
980    if (dispatchStatus[tid] == Blocked) {
981        ++iewBlockCycles;
982
983    } else if (dispatchStatus[tid] == Squashing) {
984        ++iewSquashCycles;
985    }
986
987    // Dispatch should try to dispatch as many instructions as its bandwidth
988    // will allow, as long as it is not currently blocked.
989    if (dispatchStatus[tid] == Running ||
990        dispatchStatus[tid] == Idle) {
991        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
992                "dispatch.\n", tid);
993
994        dispatchInsts(tid);
995    } else if (dispatchStatus[tid] == Unblocking) {
996        // Make sure that the skid buffer has something in it if the
997        // status is unblocking.
998        assert(!skidsEmpty());
999
1000        // If the status was unblocking, then instructions from the skid
1001        // buffer were used.  Remove those instructions and handle
1002        // the rest of unblocking.
1003        dispatchInsts(tid);
1004
1005        ++iewUnblockCycles;
1006
1007        if (validInstsFromRename() && dispatchedAllInsts) {
1008            // Add the current inputs to the skid buffer so they can be
1009            // reprocessed when this stage unblocks.
1010            skidInsert(tid);
1011        }
1012
1013        unblock(tid);
1014    }
1015}
1016
1017template <class Impl>
1018void
1019DefaultIEW<Impl>::dispatchInsts(unsigned tid)
1020{
1021    dispatchedAllInsts = true;
1022
1023    // Obtain instructions from skid buffer if unblocking, or queue from rename
1024    // otherwise.
1025    std::queue<DynInstPtr> &insts_to_dispatch =
1026        dispatchStatus[tid] == Unblocking ?
1027        skidBuffer[tid] : insts[tid];
1028
1029    int insts_to_add = insts_to_dispatch.size();
1030
1031    DynInstPtr inst;
1032    bool add_to_iq = false;
1033    int dis_num_inst = 0;
1034
1035    // Loop through the instructions, putting them in the instruction
1036    // queue.
1037    for ( ; dis_num_inst < insts_to_add &&
1038              dis_num_inst < dispatchWidth;
1039          ++dis_num_inst)
1040    {
1041        inst = insts_to_dispatch.front();
1042
1043        if (dispatchStatus[tid] == Unblocking) {
1044            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1045                    "buffer\n", tid);
1046        }
1047
1048        // Make sure there's a valid instruction there.
1049        assert(inst);
1050
1051        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1052                "IQ.\n",
1053                tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1054
1055        // Be sure to mark these instructions as ready so that the
1056        // commit stage can go ahead and execute them, and mark
1057        // them as issued so the IQ doesn't reprocess them.
1058
1059        // Check for squashed instructions.
1060        if (inst->isSquashed()) {
1061            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1062                    "not adding to IQ.\n", tid);
1063
1064            ++iewDispSquashedInsts;
1065
1066            insts_to_dispatch.pop();
1067
1068            //Tell Rename That An Instruction has been processed
1069            if (inst->isLoad() || inst->isStore()) {
1070                toRename->iewInfo[tid].dispatchedToLSQ++;
1071            }
1072            toRename->iewInfo[tid].dispatched++;
1073
1074            continue;
1075        }
1076
1077        // Check for full conditions.
1078        if (instQueue.isFull(tid)) {
1079            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1080
1081            // Call function to start blocking.
1082            block(tid);
1083
1084            // Set unblock to false. Special case where we are using
1085            // skidbuffer (unblocking) instructions but then we still
1086            // get full in the IQ.
1087            toRename->iewUnblock[tid] = false;
1088
1089            dispatchedAllInsts = false;
1090
1091            ++iewIQFullEvents;
1092            break;
1093        } else if (ldstQueue.isFull(tid)) {
1094            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1095
1096            // Call function to start blocking.
1097            block(tid);
1098
1099            // Set unblock to false. Special case where we are using
1100            // skidbuffer (unblocking) instructions but then we still
1101            // get full in the IQ.
1102            toRename->iewUnblock[tid] = false;
1103
1104            dispatchedAllInsts = false;
1105
1106            ++iewLSQFullEvents;
1107            break;
1108        }
1109
1110        // Otherwise issue the instruction just fine.
1111        if (inst->isLoad()) {
1112            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1113                    "encountered, adding to LSQ.\n", tid);
1114
1115            // Reserve a spot in the load store queue for this
1116            // memory access.
1117            ldstQueue.insertLoad(inst);
1118
1119            ++iewDispLoadInsts;
1120
1121            add_to_iq = true;
1122
1123            toRename->iewInfo[tid].dispatchedToLSQ++;
1124        } else if (inst->isStore()) {
1125            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1126                    "encountered, adding to LSQ.\n", tid);
1127
1128            ldstQueue.insertStore(inst);
1129
1130            ++iewDispStoreInsts;
1131
1132            if (inst->isStoreConditional()) {
1133                // Store conditionals need to be set as "canCommit()"
1134                // so that commit can process them when they reach the
1135                // head of commit.
1136                // @todo: This is somewhat specific to Alpha.
1137                inst->setCanCommit();
1138                instQueue.insertNonSpec(inst);
1139                add_to_iq = false;
1140
1141                ++iewDispNonSpecInsts;
1142            } else {
1143                add_to_iq = true;
1144            }
1145
1146            toRename->iewInfo[tid].dispatchedToLSQ++;
1147#if FULL_SYSTEM
1148        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1149            // Same as non-speculative stores.
1150            inst->setCanCommit();
1151            instQueue.insertBarrier(inst);
1152            add_to_iq = false;
1153#endif
1154        } else if (inst->isNonSpeculative()) {
1155            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1156                    "encountered, skipping.\n", tid);
1157
1158            // Same as non-speculative stores.
1159            inst->setCanCommit();
1160
1161            // Specifically insert it as nonspeculative.
1162            instQueue.insertNonSpec(inst);
1163
1164            ++iewDispNonSpecInsts;
1165
1166            add_to_iq = false;
1167        } else if (inst->isNop()) {
1168            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1169                    "skipping.\n", tid);
1170
1171            inst->setIssued();
1172            inst->setExecuted();
1173            inst->setCanCommit();
1174
1175            instQueue.recordProducer(inst);
1176
1177            iewExecutedNop[tid]++;
1178
1179            add_to_iq = false;
1180        } else if (inst->isExecuted()) {
1181            assert(0 && "Instruction shouldn't be executed.\n");
1182            DPRINTF(IEW, "Issue: Executed branch encountered, "
1183                    "skipping.\n");
1184
1185            inst->setIssued();
1186            inst->setCanCommit();
1187
1188            instQueue.recordProducer(inst);
1189
1190            add_to_iq = false;
1191        } else {
1192            add_to_iq = true;
1193        }
1194
1195        // If the instruction queue is not full, then add the
1196        // instruction.
1197        if (add_to_iq) {
1198            instQueue.insert(inst);
1199        }
1200
1201        insts_to_dispatch.pop();
1202
1203        toRename->iewInfo[tid].dispatched++;
1204
1205        ++iewDispatchedInsts;
1206    }
1207
1208    if (!insts_to_dispatch.empty()) {
1209        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1210        block(tid);
1211        toRename->iewUnblock[tid] = false;
1212    }
1213
1214    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1215        dispatchStatus[tid] = Running;
1216
1217        updatedQueues = true;
1218    }
1219
1220    dis_num_inst = 0;
1221}
1222
1223template <class Impl>
1224void
1225DefaultIEW<Impl>::printAvailableInsts()
1226{
1227    int inst = 0;
1228
1229    std::cout << "Available Instructions: ";
1230
1231    while (fromIssue->insts[inst]) {
1232
1233        if (inst%3==0) std::cout << "\n\t";
1234
1235        std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1236             << " TN: " << fromIssue->insts[inst]->threadNumber
1237             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1238
1239        inst++;
1240
1241    }
1242
1243    std::cout << "\n";
1244}
1245
1246template <class Impl>
1247void
1248DefaultIEW<Impl>::executeInsts()
1249{
1250    wbNumInst = 0;
1251    wbCycle = 0;
1252
1253    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1254
1255    while (threads != (*activeThreads).end()) {
1256        unsigned tid = *threads++;
1257        fetchRedirect[tid] = false;
1258    }
1259
1260    // Uncomment this if you want to see all available instructions.
1261//    printAvailableInsts();
1262
1263    // Execute/writeback any instructions that are available.
1264    int insts_to_execute = fromIssue->size;
1265    int inst_num = 0;
1266    for (; inst_num < insts_to_execute;
1267          ++inst_num) {
1268
1269        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1270
1271        DynInstPtr inst = instQueue.getInstToExecute();
1272
1273        DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1274                inst->readPC(), inst->threadNumber,inst->seqNum);
1275
1276        // Check if the instruction is squashed; if so then skip it
1277        if (inst->isSquashed()) {
1278            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1279
1280            // Consider this instruction executed so that commit can go
1281            // ahead and retire the instruction.
1282            inst->setExecuted();
1283
1284            // Not sure if I should set this here or just let commit try to
1285            // commit any squashed instructions.  I like the latter a bit more.
1286            inst->setCanCommit();
1287
1288            ++iewExecSquashedInsts;
1289
1290            decrWb(inst->seqNum);
1291            continue;
1292        }
1293
1294        Fault fault = NoFault;
1295
1296        // Execute instruction.
1297        // Note that if the instruction faults, it will be handled
1298        // at the commit stage.
1299        if (inst->isMemRef() &&
1300            (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1301            DPRINTF(IEW, "Execute: Calculating address for memory "
1302                    "reference.\n");
1303
1304            // Tell the LDSTQ to execute this instruction (if it is a load).
1305            if (inst->isLoad()) {
1306                // Loads will mark themselves as executed, and their writeback
1307                // event adds the instruction to the queue to commit
1308                fault = ldstQueue.executeLoad(inst);
1309            } else if (inst->isStore()) {
1310                fault = ldstQueue.executeStore(inst);
1311
1312                // If the store had a fault then it may not have a mem req
1313                if (!inst->isStoreConditional() && fault == NoFault) {
1314                    inst->setExecuted();
1315
1316                    instToCommit(inst);
1317                } else if (fault != NoFault) {
1318                    // If the instruction faulted, then we need to send it along to commit
1319                    // without the instruction completing.
1320                    DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
1321                            fault->name(), inst->seqNum);
1322
1323                    // Send this instruction to commit, also make sure iew stage
1324                    // realizes there is activity.
1325                    inst->setExecuted();
1326
1327                    instToCommit(inst);
1328                    activityThisCycle();
1329                }
1330
1331                // Store conditionals will mark themselves as
1332                // executed, and their writeback event will add the
1333                // instruction to the queue to commit.
1334            } else {
1335                panic("Unexpected memory type!\n");
1336            }
1337
1338        } else {
1339            inst->execute();
1340
1341            inst->setExecuted();
1342
1343            instToCommit(inst);
1344        }
1345
1346        updateExeInstStats(inst);
1347
1348        // Check if branch prediction was correct, if not then we need
1349        // to tell commit to squash in flight instructions.  Only
1350        // handle this if there hasn't already been something that
1351        // redirects fetch in this group of instructions.
1352
1353        // This probably needs to prioritize the redirects if a different
1354        // scheduler is used.  Currently the scheduler schedules the oldest
1355        // instruction first, so the branch resolution order will be correct.
1356        unsigned tid = inst->threadNumber;
1357
1358        if (!fetchRedirect[tid] ||
1359            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1360
1361            if (inst->mispredicted()) {
1362                fetchRedirect[tid] = true;
1363
1364                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1365                DPRINTF(IEW, "Predicted target was %#x, %#x.\n",
1366                        inst->readPredPC(), inst->readPredNPC());
1367                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1368                        " NPC: %#x.\n", inst->readNextPC(),
1369                        inst->readNextNPC());
1370                // If incorrect, then signal the ROB that it must be squashed.
1371                squashDueToBranch(inst, tid);
1372
1373                if (inst->readPredTaken()) {
1374                    predictedTakenIncorrect++;
1375                } else {
1376                    predictedNotTakenIncorrect++;
1377                }
1378            } else if (ldstQueue.violation(tid)) {
1379                // If there was an ordering violation, then get the
1380                // DynInst that caused the violation.  Note that this
1381                // clears the violation signal.
1382                DynInstPtr violator;
1383                violator = ldstQueue.getMemDepViolator(tid);
1384
1385                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1386                        "%#x, inst PC: %#x.  Addr is: %#x.\n",
1387                        violator->readPC(), inst->readPC(), inst->physEffAddr);
1388
1389                // Ensure the violating instruction is older than
1390                // current squash
1391                if (fetchRedirect[tid] &&
1392                    violator->seqNum >= toCommit->squashedSeqNum[tid])
1393                    continue;
1394
1395                fetchRedirect[tid] = true;
1396
1397                // Tell the instruction queue that a violation has occured.
1398                instQueue.violation(inst, violator);
1399
1400                // Squash.
1401                squashDueToMemOrder(inst,tid);
1402
1403                ++memOrderViolationEvents;
1404            } else if (ldstQueue.loadBlocked(tid) &&
1405                       !ldstQueue.isLoadBlockedHandled(tid)) {
1406                fetchRedirect[tid] = true;
1407
1408                DPRINTF(IEW, "Load operation couldn't execute because the "
1409                        "memory system is blocked.  PC: %#x [sn:%lli]\n",
1410                        inst->readPC(), inst->seqNum);
1411
1412                squashDueToMemBlocked(inst, tid);
1413            }
1414        }
1415    }
1416
1417    // Update and record activity if we processed any instructions.
1418    if (inst_num) {
1419        if (exeStatus == Idle) {
1420            exeStatus = Running;
1421        }
1422
1423        updatedQueues = true;
1424
1425        cpu->activityThisCycle();
1426    }
1427
1428    // Need to reset this in case a writeback event needs to write into the
1429    // iew queue.  That way the writeback event will write into the correct
1430    // spot in the queue.
1431    wbNumInst = 0;
1432}
1433
1434template <class Impl>
1435void
1436DefaultIEW<Impl>::writebackInsts()
1437{
1438    // Loop through the head of the time buffer and wake any
1439    // dependents.  These instructions are about to write back.  Also
1440    // mark scoreboard that this instruction is finally complete.
1441    // Either have IEW have direct access to scoreboard, or have this
1442    // as part of backwards communication.
1443    for (int inst_num = 0; inst_num < wbWidth &&
1444             toCommit->insts[inst_num]; inst_num++) {
1445        DynInstPtr inst = toCommit->insts[inst_num];
1446        int tid = inst->threadNumber;
1447
1448        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1449                inst->seqNum, inst->readPC());
1450
1451        iewInstsToCommit[tid]++;
1452
1453        // Some instructions will be sent to commit without having
1454        // executed because they need commit to handle them.
1455        // E.g. Uncached loads have not actually executed when they
1456        // are first sent to commit.  Instead commit must tell the LSQ
1457        // when it's ready to execute the uncached load.
1458        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1459            int dependents = instQueue.wakeDependents(inst);
1460
1461            for (int i = 0; i < inst->numDestRegs(); i++) {
1462                //mark as Ready
1463                DPRINTF(IEW,"Setting Destination Register %i\n",
1464                        inst->renamedDestRegIdx(i));
1465                scoreboard->setReg(inst->renamedDestRegIdx(i));
1466            }
1467
1468            if (dependents) {
1469                producerInst[tid]++;
1470                consumerInst[tid]+= dependents;
1471            }
1472            writebackCount[tid]++;
1473        }
1474
1475        decrWb(inst->seqNum);
1476    }
1477}
1478
1479template<class Impl>
1480void
1481DefaultIEW<Impl>::tick()
1482{
1483    wbNumInst = 0;
1484    wbCycle = 0;
1485
1486    wroteToTimeBuffer = false;
1487    updatedQueues = false;
1488
1489    sortInsts();
1490
1491    // Free function units marked as being freed this cycle.
1492    fuPool->processFreeUnits();
1493
1494    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1495
1496    // Check stall and squash signals, dispatch any instructions.
1497    while (threads != (*activeThreads).end()) {
1498           unsigned tid = *threads++;
1499
1500        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1501
1502        checkSignalsAndUpdate(tid);
1503        dispatch(tid);
1504    }
1505
1506    if (exeStatus != Squashing) {
1507        executeInsts();
1508
1509        writebackInsts();
1510
1511        // Have the instruction queue try to schedule any ready instructions.
1512        // (In actuality, this scheduling is for instructions that will
1513        // be executed next cycle.)
1514        instQueue.scheduleReadyInsts();
1515
1516        // Also should advance its own time buffers if the stage ran.
1517        // Not the best place for it, but this works (hopefully).
1518        issueToExecQueue.advance();
1519    }
1520
1521    bool broadcast_free_entries = false;
1522
1523    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1524        exeStatus = Idle;
1525        updateLSQNextCycle = false;
1526
1527        broadcast_free_entries = true;
1528    }
1529
1530    // Writeback any stores using any leftover bandwidth.
1531    ldstQueue.writebackStores();
1532
1533    // Check the committed load/store signals to see if there's a load
1534    // or store to commit.  Also check if it's being told to execute a
1535    // nonspeculative instruction.
1536    // This is pretty inefficient...
1537
1538    threads = (*activeThreads).begin();
1539    while (threads != (*activeThreads).end()) {
1540        unsigned tid = (*threads++);
1541
1542        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1543
1544        // Update structures based on instructions committed.
1545        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1546            !fromCommit->commitInfo[tid].squash &&
1547            !fromCommit->commitInfo[tid].robSquashing) {
1548
1549            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1550
1551            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1552
1553            updateLSQNextCycle = true;
1554            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1555        }
1556
1557        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1558
1559            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1560            if (fromCommit->commitInfo[tid].uncached) {
1561                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1562            } else {
1563                instQueue.scheduleNonSpec(
1564                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1565            }
1566        }
1567
1568        if (broadcast_free_entries) {
1569            toFetch->iewInfo[tid].iqCount =
1570                instQueue.getCount(tid);
1571            toFetch->iewInfo[tid].ldstqCount =
1572                ldstQueue.getCount(tid);
1573
1574            toRename->iewInfo[tid].usedIQ = true;
1575            toRename->iewInfo[tid].freeIQEntries =
1576                instQueue.numFreeEntries();
1577            toRename->iewInfo[tid].usedLSQ = true;
1578            toRename->iewInfo[tid].freeLSQEntries =
1579                ldstQueue.numFreeEntries(tid);
1580
1581            wroteToTimeBuffer = true;
1582        }
1583
1584        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1585                tid, toRename->iewInfo[tid].dispatched);
1586    }
1587
1588    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1589            "LSQ has %i free entries.\n",
1590            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1591            ldstQueue.numFreeEntries());
1592
1593    updateStatus();
1594
1595    if (wroteToTimeBuffer) {
1596        DPRINTF(Activity, "Activity this cycle.\n");
1597        cpu->activityThisCycle();
1598    }
1599}
1600
1601template <class Impl>
1602void
1603DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1604{
1605    int thread_number = inst->threadNumber;
1606
1607    //
1608    //  Pick off the software prefetches
1609    //
1610#ifdef TARGET_ALPHA
1611    if (inst->isDataPrefetch())
1612        iewExecutedSwp[thread_number]++;
1613    else
1614        iewIewExecutedcutedInsts++;
1615#else
1616    iewExecutedInsts++;
1617#endif
1618
1619    //
1620    //  Control operations
1621    //
1622    if (inst->isControl())
1623        iewExecutedBranches[thread_number]++;
1624
1625    //
1626    //  Memory operations
1627    //
1628    if (inst->isMemRef()) {
1629        iewExecutedRefs[thread_number]++;
1630
1631        if (inst->isLoad()) {
1632            iewExecLoadInsts[thread_number]++;
1633        }
1634    }
1635}
1636