iew_impl.hh revision 3125:febd811bccc6 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew.  There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41template<class Impl>
42DefaultIEW<Impl>::DefaultIEW(Params *params)
43    : issueToExecQueue(params->backComSize, params->forwardComSize),
44      instQueue(params),
45      ldstQueue(params),
46      fuPool(params->fuPool),
47      commitToIEWDelay(params->commitToIEWDelay),
48      renameToIEWDelay(params->renameToIEWDelay),
49      issueToExecuteDelay(params->issueToExecuteDelay),
50      dispatchWidth(params->dispatchWidth),
51      issueWidth(params->issueWidth),
52      wbOutstanding(0),
53      wbWidth(params->wbWidth),
54      numThreads(params->numberOfThreads),
55      switchedOut(false)
56{
57    _status = Active;
58    exeStatus = Running;
59    wbStatus = Idle;
60
61    // Setup wire to read instructions coming from issue.
62    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
63
64    // Instruction queue needs the queue between issue and execute.
65    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
66
67    instQueue.setIEW(this);
68    ldstQueue.setIEW(this);
69
70    for (int i=0; i < numThreads; i++) {
71        dispatchStatus[i] = Running;
72        stalls[i].commit = false;
73        fetchRedirect[i] = false;
74        bdelayDoneSeqNum[i] = 0;
75    }
76
77    wbMax = wbWidth * params->wbDepth;
78
79    updateLSQNextCycle = false;
80
81    ableToIssue = true;
82
83    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
84}
85
86template <class Impl>
87std::string
88DefaultIEW<Impl>::name() const
89{
90    return cpu->name() + ".iew";
91}
92
93template <class Impl>
94void
95DefaultIEW<Impl>::regStats()
96{
97    using namespace Stats;
98
99    instQueue.regStats();
100    ldstQueue.regStats();
101
102    iewIdleCycles
103        .name(name() + ".iewIdleCycles")
104        .desc("Number of cycles IEW is idle");
105
106    iewSquashCycles
107        .name(name() + ".iewSquashCycles")
108        .desc("Number of cycles IEW is squashing");
109
110    iewBlockCycles
111        .name(name() + ".iewBlockCycles")
112        .desc("Number of cycles IEW is blocking");
113
114    iewUnblockCycles
115        .name(name() + ".iewUnblockCycles")
116        .desc("Number of cycles IEW is unblocking");
117
118    iewDispatchedInsts
119        .name(name() + ".iewDispatchedInsts")
120        .desc("Number of instructions dispatched to IQ");
121
122    iewDispSquashedInsts
123        .name(name() + ".iewDispSquashedInsts")
124        .desc("Number of squashed instructions skipped by dispatch");
125
126    iewDispLoadInsts
127        .name(name() + ".iewDispLoadInsts")
128        .desc("Number of dispatched load instructions");
129
130    iewDispStoreInsts
131        .name(name() + ".iewDispStoreInsts")
132        .desc("Number of dispatched store instructions");
133
134    iewDispNonSpecInsts
135        .name(name() + ".iewDispNonSpecInsts")
136        .desc("Number of dispatched non-speculative instructions");
137
138    iewIQFullEvents
139        .name(name() + ".iewIQFullEvents")
140        .desc("Number of times the IQ has become full, causing a stall");
141
142    iewLSQFullEvents
143        .name(name() + ".iewLSQFullEvents")
144        .desc("Number of times the LSQ has become full, causing a stall");
145
146    memOrderViolationEvents
147        .name(name() + ".memOrderViolationEvents")
148        .desc("Number of memory order violations");
149
150    predictedTakenIncorrect
151        .name(name() + ".predictedTakenIncorrect")
152        .desc("Number of branches that were predicted taken incorrectly");
153
154    predictedNotTakenIncorrect
155        .name(name() + ".predictedNotTakenIncorrect")
156        .desc("Number of branches that were predicted not taken incorrectly");
157
158    branchMispredicts
159        .name(name() + ".branchMispredicts")
160        .desc("Number of branch mispredicts detected at execute");
161
162    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
163
164    iewExecutedInsts
165        .name(name() + ".iewExecutedInsts")
166        .desc("Number of executed instructions");
167
168    iewExecLoadInsts
169        .init(cpu->number_of_threads)
170        .name(name() + ".iewExecLoadInsts")
171        .desc("Number of load instructions executed")
172        .flags(total);
173
174    iewExecSquashedInsts
175        .name(name() + ".iewExecSquashedInsts")
176        .desc("Number of squashed instructions skipped in execute");
177
178    iewExecutedSwp
179        .init(cpu->number_of_threads)
180        .name(name() + ".EXEC:swp")
181        .desc("number of swp insts executed")
182        .flags(total);
183
184    iewExecutedNop
185        .init(cpu->number_of_threads)
186        .name(name() + ".EXEC:nop")
187        .desc("number of nop insts executed")
188        .flags(total);
189
190    iewExecutedRefs
191        .init(cpu->number_of_threads)
192        .name(name() + ".EXEC:refs")
193        .desc("number of memory reference insts executed")
194        .flags(total);
195
196    iewExecutedBranches
197        .init(cpu->number_of_threads)
198        .name(name() + ".EXEC:branches")
199        .desc("Number of branches executed")
200        .flags(total);
201
202    iewExecStoreInsts
203        .name(name() + ".EXEC:stores")
204        .desc("Number of stores executed")
205        .flags(total);
206    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
207
208    iewExecRate
209        .name(name() + ".EXEC:rate")
210        .desc("Inst execution rate")
211        .flags(total);
212
213    iewExecRate = iewExecutedInsts / cpu->numCycles;
214
215    iewInstsToCommit
216        .init(cpu->number_of_threads)
217        .name(name() + ".WB:sent")
218        .desc("cumulative count of insts sent to commit")
219        .flags(total);
220
221    writebackCount
222        .init(cpu->number_of_threads)
223        .name(name() + ".WB:count")
224        .desc("cumulative count of insts written-back")
225        .flags(total);
226
227    producerInst
228        .init(cpu->number_of_threads)
229        .name(name() + ".WB:producers")
230        .desc("num instructions producing a value")
231        .flags(total);
232
233    consumerInst
234        .init(cpu->number_of_threads)
235        .name(name() + ".WB:consumers")
236        .desc("num instructions consuming a value")
237        .flags(total);
238
239    wbPenalized
240        .init(cpu->number_of_threads)
241        .name(name() + ".WB:penalized")
242        .desc("number of instrctions required to write to 'other' IQ")
243        .flags(total);
244
245    wbPenalizedRate
246        .name(name() + ".WB:penalized_rate")
247        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
248        .flags(total);
249
250    wbPenalizedRate = wbPenalized / writebackCount;
251
252    wbFanout
253        .name(name() + ".WB:fanout")
254        .desc("average fanout of values written-back")
255        .flags(total);
256
257    wbFanout = producerInst / consumerInst;
258
259    wbRate
260        .name(name() + ".WB:rate")
261        .desc("insts written-back per cycle")
262        .flags(total);
263    wbRate = writebackCount / cpu->numCycles;
264}
265
266template<class Impl>
267void
268DefaultIEW<Impl>::initStage()
269{
270    for (int tid=0; tid < numThreads; tid++) {
271        toRename->iewInfo[tid].usedIQ = true;
272        toRename->iewInfo[tid].freeIQEntries =
273            instQueue.numFreeEntries(tid);
274
275        toRename->iewInfo[tid].usedLSQ = true;
276        toRename->iewInfo[tid].freeLSQEntries =
277            ldstQueue.numFreeEntries(tid);
278    }
279}
280
281template<class Impl>
282void
283DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
284{
285    DPRINTF(IEW, "Setting CPU pointer.\n");
286    cpu = cpu_ptr;
287
288    instQueue.setCPU(cpu_ptr);
289    ldstQueue.setCPU(cpu_ptr);
290
291    cpu->activateStage(O3CPU::IEWIdx);
292}
293
294template<class Impl>
295void
296DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
297{
298    DPRINTF(IEW, "Setting time buffer pointer.\n");
299    timeBuffer = tb_ptr;
300
301    // Setup wire to read information from time buffer, from commit.
302    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
303
304    // Setup wire to write information back to previous stages.
305    toRename = timeBuffer->getWire(0);
306
307    toFetch = timeBuffer->getWire(0);
308
309    // Instruction queue also needs main time buffer.
310    instQueue.setTimeBuffer(tb_ptr);
311}
312
313template<class Impl>
314void
315DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
316{
317    DPRINTF(IEW, "Setting rename queue pointer.\n");
318    renameQueue = rq_ptr;
319
320    // Setup wire to read information from rename queue.
321    fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328    DPRINTF(IEW, "Setting IEW queue pointer.\n");
329    iewQueue = iq_ptr;
330
331    // Setup wire to write instructions to commit.
332    toCommit = iewQueue->getWire(0);
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
338{
339    DPRINTF(IEW, "Setting active threads list pointer.\n");
340    activeThreads = at_ptr;
341
342    ldstQueue.setActiveThreads(at_ptr);
343    instQueue.setActiveThreads(at_ptr);
344}
345
346template<class Impl>
347void
348DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
349{
350    DPRINTF(IEW, "Setting scoreboard pointer.\n");
351    scoreboard = sb_ptr;
352}
353
354template <class Impl>
355bool
356DefaultIEW<Impl>::drain()
357{
358    // IEW is ready to drain at any time.
359    cpu->signalDrained();
360    return true;
361}
362
363template <class Impl>
364void
365DefaultIEW<Impl>::resume()
366{
367}
368
369template <class Impl>
370void
371DefaultIEW<Impl>::switchOut()
372{
373    // Clear any state.
374    switchedOut = true;
375    assert(insts[0].empty());
376    assert(skidBuffer[0].empty());
377
378    instQueue.switchOut();
379    ldstQueue.switchOut();
380    fuPool->switchOut();
381
382    for (int i = 0; i < numThreads; i++) {
383        while (!insts[i].empty())
384            insts[i].pop();
385        while (!skidBuffer[i].empty())
386            skidBuffer[i].pop();
387    }
388}
389
390template <class Impl>
391void
392DefaultIEW<Impl>::takeOverFrom()
393{
394    // Reset all state.
395    _status = Active;
396    exeStatus = Running;
397    wbStatus = Idle;
398    switchedOut = false;
399
400    instQueue.takeOverFrom();
401    ldstQueue.takeOverFrom();
402    fuPool->takeOverFrom();
403
404    initStage();
405    cpu->activityThisCycle();
406
407    for (int i=0; i < numThreads; i++) {
408        dispatchStatus[i] = Running;
409        stalls[i].commit = false;
410        fetchRedirect[i] = false;
411    }
412
413    updateLSQNextCycle = false;
414
415    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
416        issueToExecQueue.advance();
417    }
418}
419
420template<class Impl>
421void
422DefaultIEW<Impl>::squash(unsigned tid)
423{
424    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
425            tid);
426
427    // Tell the IQ to start squashing.
428    instQueue.squash(tid);
429
430    // Tell the LDSTQ to start squashing.
431#if ISA_HAS_DELAY_SLOT
432    ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
433#else
434    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
435#endif
436    updatedQueues = true;
437
438    // Clear the skid buffer in case it has any data in it.
439    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
440            tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
441
442    while (!skidBuffer[tid].empty()) {
443#if ISA_HAS_DELAY_SLOT
444        if (skidBuffer[tid].front()->seqNum <=
445            fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
446            DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
447                    "that occur before delay slot [sn:%i].\n",
448                    fromCommit->commitInfo[tid].bdelayDoneSeqNum,
449                    tid);
450            break;
451        } else {
452            DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
453                    "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
454        }
455#endif
456        if (skidBuffer[tid].front()->isLoad() ||
457            skidBuffer[tid].front()->isStore() ) {
458            toRename->iewInfo[tid].dispatchedToLSQ++;
459        }
460
461        toRename->iewInfo[tid].dispatched++;
462
463        skidBuffer[tid].pop();
464    }
465
466    bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
467
468    emptyRenameInsts(tid);
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
474{
475    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476            "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478    toCommit->squash[tid] = true;
479    toCommit->squashedSeqNum[tid] = inst->seqNum;
480    toCommit->mispredPC[tid] = inst->readPC();
481    toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
484    bool branch_taken = inst->readNextNPC() !=
485        (inst->readNextPC() + sizeof(TheISA::MachInst));
486
487    toCommit->branchTaken[tid] = branch_taken;
488
489    toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
490
491    if (inst->isCondDelaySlot() && branch_taken) {
492        toCommit->nextPC[tid] = inst->readNextPC();
493    } else {
494        toCommit->nextPC[tid] = inst->readNextNPC();
495    }
496#else
497    toCommit->branchTaken[tid] = inst->readNextPC() !=
498        (inst->readPC() + sizeof(TheISA::MachInst));
499    toCommit->nextPC[tid] = inst->readNextPC();
500#endif
501
502    toCommit->includeSquashInst[tid] = false;
503
504    wroteToTimeBuffer = true;
505}
506
507template<class Impl>
508void
509DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
510{
511    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
512            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
513
514    toCommit->squash[tid] = true;
515    toCommit->squashedSeqNum[tid] = inst->seqNum;
516    toCommit->nextPC[tid] = inst->readNextPC();
517
518    toCommit->includeSquashInst[tid] = false;
519
520    wroteToTimeBuffer = true;
521}
522
523template<class Impl>
524void
525DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
526{
527    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
528            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
529
530    toCommit->squash[tid] = true;
531    toCommit->squashedSeqNum[tid] = inst->seqNum;
532    toCommit->nextPC[tid] = inst->readPC();
533
534    // Must include the broadcasted SN in the squash.
535    toCommit->includeSquashInst[tid] = true;
536
537    ldstQueue.setLoadBlockedHandled(tid);
538
539    wroteToTimeBuffer = true;
540}
541
542template<class Impl>
543void
544DefaultIEW<Impl>::block(unsigned tid)
545{
546    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
547
548    if (dispatchStatus[tid] != Blocked &&
549        dispatchStatus[tid] != Unblocking) {
550        toRename->iewBlock[tid] = true;
551        wroteToTimeBuffer = true;
552    }
553
554    // Add the current inputs to the skid buffer so they can be
555    // reprocessed when this stage unblocks.
556    skidInsert(tid);
557
558    dispatchStatus[tid] = Blocked;
559}
560
561template<class Impl>
562void
563DefaultIEW<Impl>::unblock(unsigned tid)
564{
565    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
566            "buffer %u.\n",tid, tid);
567
568    // If the skid bufffer is empty, signal back to previous stages to unblock.
569    // Also switch status to running.
570    if (skidBuffer[tid].empty()) {
571        toRename->iewUnblock[tid] = true;
572        wroteToTimeBuffer = true;
573        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
574        dispatchStatus[tid] = Running;
575    }
576}
577
578template<class Impl>
579void
580DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
581{
582    instQueue.wakeDependents(inst);
583}
584
585template<class Impl>
586void
587DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
588{
589    instQueue.rescheduleMemInst(inst);
590}
591
592template<class Impl>
593void
594DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
595{
596    instQueue.replayMemInst(inst);
597}
598
599template<class Impl>
600void
601DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
602{
603    // First check the time slot that this instruction will write
604    // to.  If there are free write ports at the time, then go ahead
605    // and write the instruction to that time.  If there are not,
606    // keep looking back to see where's the first time there's a
607    // free slot.
608    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
609        ++wbNumInst;
610        if (wbNumInst == wbWidth) {
611            ++wbCycle;
612            wbNumInst = 0;
613        }
614
615        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
616    }
617
618    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
619            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
620    // Add finished instruction to queue to commit.
621    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
622    (*iewQueue)[wbCycle].size++;
623}
624
625template <class Impl>
626unsigned
627DefaultIEW<Impl>::validInstsFromRename()
628{
629    unsigned inst_count = 0;
630
631    for (int i=0; i<fromRename->size; i++) {
632        if (!fromRename->insts[i]->isSquashed())
633            inst_count++;
634    }
635
636    return inst_count;
637}
638
639template<class Impl>
640void
641DefaultIEW<Impl>::skidInsert(unsigned tid)
642{
643    DynInstPtr inst = NULL;
644
645    while (!insts[tid].empty()) {
646        inst = insts[tid].front();
647
648        insts[tid].pop();
649
650        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
651                "dispatch skidBuffer %i\n",tid, inst->seqNum,
652                inst->readPC(),tid);
653
654        skidBuffer[tid].push(inst);
655    }
656
657    assert(skidBuffer[tid].size() <= skidBufferMax &&
658           "Skidbuffer Exceeded Max Size");
659}
660
661template<class Impl>
662int
663DefaultIEW<Impl>::skidCount()
664{
665    int max=0;
666
667    std::list<unsigned>::iterator threads = (*activeThreads).begin();
668
669    while (threads != (*activeThreads).end()) {
670        unsigned thread_count = skidBuffer[*threads++].size();
671        if (max < thread_count)
672            max = thread_count;
673    }
674
675    return max;
676}
677
678template<class Impl>
679bool
680DefaultIEW<Impl>::skidsEmpty()
681{
682    std::list<unsigned>::iterator threads = (*activeThreads).begin();
683
684    while (threads != (*activeThreads).end()) {
685        if (!skidBuffer[*threads++].empty())
686            return false;
687    }
688
689    return true;
690}
691
692template <class Impl>
693void
694DefaultIEW<Impl>::updateStatus()
695{
696    bool any_unblocking = false;
697
698    std::list<unsigned>::iterator threads = (*activeThreads).begin();
699
700    threads = (*activeThreads).begin();
701
702    while (threads != (*activeThreads).end()) {
703        unsigned tid = *threads++;
704
705        if (dispatchStatus[tid] == Unblocking) {
706            any_unblocking = true;
707            break;
708        }
709    }
710
711    // If there are no ready instructions waiting to be scheduled by the IQ,
712    // and there's no stores waiting to write back, and dispatch is not
713    // unblocking, then there is no internal activity for the IEW stage.
714    if (_status == Active && !instQueue.hasReadyInsts() &&
715        !ldstQueue.willWB() && !any_unblocking) {
716        DPRINTF(IEW, "IEW switching to idle\n");
717
718        deactivateStage();
719
720        _status = Inactive;
721    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
722                                       ldstQueue.willWB() ||
723                                       any_unblocking)) {
724        // Otherwise there is internal activity.  Set to active.
725        DPRINTF(IEW, "IEW switching to active\n");
726
727        activateStage();
728
729        _status = Active;
730    }
731}
732
733template <class Impl>
734void
735DefaultIEW<Impl>::resetEntries()
736{
737    instQueue.resetEntries();
738    ldstQueue.resetEntries();
739}
740
741template <class Impl>
742void
743DefaultIEW<Impl>::readStallSignals(unsigned tid)
744{
745    if (fromCommit->commitBlock[tid]) {
746        stalls[tid].commit = true;
747    }
748
749    if (fromCommit->commitUnblock[tid]) {
750        assert(stalls[tid].commit);
751        stalls[tid].commit = false;
752    }
753}
754
755template <class Impl>
756bool
757DefaultIEW<Impl>::checkStall(unsigned tid)
758{
759    bool ret_val(false);
760
761    if (stalls[tid].commit) {
762        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
763        ret_val = true;
764    } else if (instQueue.isFull(tid)) {
765        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
766        ret_val = true;
767    } else if (ldstQueue.isFull(tid)) {
768        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
769
770        if (ldstQueue.numLoads(tid) > 0 ) {
771
772            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
773                    tid,ldstQueue.getLoadHeadSeqNum(tid));
774        }
775
776        if (ldstQueue.numStores(tid) > 0) {
777
778            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
779                    tid,ldstQueue.getStoreHeadSeqNum(tid));
780        }
781
782        ret_val = true;
783    } else if (ldstQueue.isStalled(tid)) {
784        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
785        ret_val = true;
786    }
787
788    return ret_val;
789}
790
791template <class Impl>
792void
793DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
794{
795    // Check if there's a squash signal, squash if there is
796    // Check stall signals, block if there is.
797    // If status was Blocked
798    //     if so then go to unblocking
799    // If status was Squashing
800    //     check if squashing is not high.  Switch to running this cycle.
801
802    readStallSignals(tid);
803
804    if (fromCommit->commitInfo[tid].squash) {
805        squash(tid);
806
807        if (dispatchStatus[tid] == Blocked ||
808            dispatchStatus[tid] == Unblocking) {
809            toRename->iewUnblock[tid] = true;
810            wroteToTimeBuffer = true;
811        }
812
813        dispatchStatus[tid] = Squashing;
814
815        fetchRedirect[tid] = false;
816        return;
817    }
818
819    if (fromCommit->commitInfo[tid].robSquashing) {
820        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
821
822        dispatchStatus[tid] = Squashing;
823
824        emptyRenameInsts(tid);
825        wroteToTimeBuffer = true;
826        return;
827    }
828
829    if (checkStall(tid)) {
830        block(tid);
831        dispatchStatus[tid] = Blocked;
832        return;
833    }
834
835    if (dispatchStatus[tid] == Blocked) {
836        // Status from previous cycle was blocked, but there are no more stall
837        // conditions.  Switch over to unblocking.
838        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
839                tid);
840
841        dispatchStatus[tid] = Unblocking;
842
843        unblock(tid);
844
845        return;
846    }
847
848    if (dispatchStatus[tid] == Squashing) {
849        // Switch status to running if rename isn't being told to block or
850        // squash this cycle.
851        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
852                tid);
853
854        dispatchStatus[tid] = Running;
855
856        return;
857    }
858}
859
860template <class Impl>
861void
862DefaultIEW<Impl>::sortInsts()
863{
864    int insts_from_rename = fromRename->size;
865#ifdef DEBUG
866#if !ISA_HAS_DELAY_SLOT
867    for (int i = 0; i < numThreads; i++)
868        assert(insts[i].empty());
869#endif
870#endif
871    for (int i = 0; i < insts_from_rename; ++i) {
872        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
873    }
874}
875
876template <class Impl>
877void
878DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
879{
880    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
881            "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
882
883    while (!insts[tid].empty()) {
884#if ISA_HAS_DELAY_SLOT
885        if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
886            DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
887                    " that occurs at or before delay slot [sn:%i].\n",
888                    tid, bdelayDoneSeqNum[tid]);
889            break;
890        } else {
891            DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
892                    "[sn:%i].\n", tid, insts[tid].front()->seqNum);
893        }
894#endif
895
896        if (insts[tid].front()->isLoad() ||
897            insts[tid].front()->isStore() ) {
898            toRename->iewInfo[tid].dispatchedToLSQ++;
899        }
900
901        toRename->iewInfo[tid].dispatched++;
902
903        insts[tid].pop();
904    }
905}
906
907template <class Impl>
908void
909DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
910{
911    while (!insts[tid].empty()) {
912        if (insts[tid].front()->isLoad() ||
913            insts[tid].front()->isStore() ) {
914            toRename->iewInfo[tid].dispatchedToLSQ++;
915        }
916
917        toRename->iewInfo[tid].dispatched++;
918
919        insts[tid].pop();
920    }
921}
922
923template <class Impl>
924void
925DefaultIEW<Impl>::wakeCPU()
926{
927    cpu->wakeCPU();
928}
929
930template <class Impl>
931void
932DefaultIEW<Impl>::activityThisCycle()
933{
934    DPRINTF(Activity, "Activity this cycle.\n");
935    cpu->activityThisCycle();
936}
937
938template <class Impl>
939inline void
940DefaultIEW<Impl>::activateStage()
941{
942    DPRINTF(Activity, "Activating stage.\n");
943    cpu->activateStage(O3CPU::IEWIdx);
944}
945
946template <class Impl>
947inline void
948DefaultIEW<Impl>::deactivateStage()
949{
950    DPRINTF(Activity, "Deactivating stage.\n");
951    cpu->deactivateStage(O3CPU::IEWIdx);
952}
953
954template<class Impl>
955void
956DefaultIEW<Impl>::dispatch(unsigned tid)
957{
958    // If status is Running or idle,
959    //     call dispatchInsts()
960    // If status is Unblocking,
961    //     buffer any instructions coming from rename
962    //     continue trying to empty skid buffer
963    //     check if stall conditions have passed
964
965    if (dispatchStatus[tid] == Blocked) {
966        ++iewBlockCycles;
967
968    } else if (dispatchStatus[tid] == Squashing) {
969        ++iewSquashCycles;
970    }
971
972    // Dispatch should try to dispatch as many instructions as its bandwidth
973    // will allow, as long as it is not currently blocked.
974    if (dispatchStatus[tid] == Running ||
975        dispatchStatus[tid] == Idle) {
976        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
977                "dispatch.\n", tid);
978
979        dispatchInsts(tid);
980    } else if (dispatchStatus[tid] == Unblocking) {
981        // Make sure that the skid buffer has something in it if the
982        // status is unblocking.
983        assert(!skidsEmpty());
984
985        // If the status was unblocking, then instructions from the skid
986        // buffer were used.  Remove those instructions and handle
987        // the rest of unblocking.
988        dispatchInsts(tid);
989
990        ++iewUnblockCycles;
991
992        if (validInstsFromRename() && dispatchedAllInsts) {
993            // Add the current inputs to the skid buffer so they can be
994            // reprocessed when this stage unblocks.
995            skidInsert(tid);
996        }
997
998        unblock(tid);
999    }
1000}
1001
1002template <class Impl>
1003void
1004DefaultIEW<Impl>::dispatchInsts(unsigned tid)
1005{
1006    dispatchedAllInsts = true;
1007
1008    // Obtain instructions from skid buffer if unblocking, or queue from rename
1009    // otherwise.
1010    std::queue<DynInstPtr> &insts_to_dispatch =
1011        dispatchStatus[tid] == Unblocking ?
1012        skidBuffer[tid] : insts[tid];
1013
1014    int insts_to_add = insts_to_dispatch.size();
1015
1016    DynInstPtr inst;
1017    bool add_to_iq = false;
1018    int dis_num_inst = 0;
1019
1020    // Loop through the instructions, putting them in the instruction
1021    // queue.
1022    for ( ; dis_num_inst < insts_to_add &&
1023              dis_num_inst < dispatchWidth;
1024          ++dis_num_inst)
1025    {
1026        inst = insts_to_dispatch.front();
1027
1028        if (dispatchStatus[tid] == Unblocking) {
1029            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1030                    "buffer\n", tid);
1031        }
1032
1033        // Make sure there's a valid instruction there.
1034        assert(inst);
1035
1036        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1037                "IQ.\n",
1038                tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1039
1040        // Be sure to mark these instructions as ready so that the
1041        // commit stage can go ahead and execute them, and mark
1042        // them as issued so the IQ doesn't reprocess them.
1043
1044        // Check for squashed instructions.
1045        if (inst->isSquashed()) {
1046            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1047                    "not adding to IQ.\n", tid);
1048
1049            ++iewDispSquashedInsts;
1050
1051            insts_to_dispatch.pop();
1052
1053            //Tell Rename That An Instruction has been processed
1054            if (inst->isLoad() || inst->isStore()) {
1055                toRename->iewInfo[tid].dispatchedToLSQ++;
1056            }
1057            toRename->iewInfo[tid].dispatched++;
1058
1059            continue;
1060        }
1061
1062        // Check for full conditions.
1063        if (instQueue.isFull(tid)) {
1064            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1065
1066            // Call function to start blocking.
1067            block(tid);
1068
1069            // Set unblock to false. Special case where we are using
1070            // skidbuffer (unblocking) instructions but then we still
1071            // get full in the IQ.
1072            toRename->iewUnblock[tid] = false;
1073
1074            dispatchedAllInsts = false;
1075
1076            ++iewIQFullEvents;
1077            break;
1078        } else if (ldstQueue.isFull(tid)) {
1079            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1080
1081            // Call function to start blocking.
1082            block(tid);
1083
1084            // Set unblock to false. Special case where we are using
1085            // skidbuffer (unblocking) instructions but then we still
1086            // get full in the IQ.
1087            toRename->iewUnblock[tid] = false;
1088
1089            dispatchedAllInsts = false;
1090
1091            ++iewLSQFullEvents;
1092            break;
1093        }
1094
1095        // Otherwise issue the instruction just fine.
1096        if (inst->isLoad()) {
1097            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1098                    "encountered, adding to LSQ.\n", tid);
1099
1100            // Reserve a spot in the load store queue for this
1101            // memory access.
1102            ldstQueue.insertLoad(inst);
1103
1104            ++iewDispLoadInsts;
1105
1106            add_to_iq = true;
1107
1108            toRename->iewInfo[tid].dispatchedToLSQ++;
1109        } else if (inst->isStore()) {
1110            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1111                    "encountered, adding to LSQ.\n", tid);
1112
1113            ldstQueue.insertStore(inst);
1114
1115            ++iewDispStoreInsts;
1116
1117            if (inst->isStoreConditional()) {
1118                // Store conditionals need to be set as "canCommit()"
1119                // so that commit can process them when they reach the
1120                // head of commit.
1121                // @todo: This is somewhat specific to Alpha.
1122                inst->setCanCommit();
1123                instQueue.insertNonSpec(inst);
1124                add_to_iq = false;
1125
1126                ++iewDispNonSpecInsts;
1127            } else {
1128                add_to_iq = true;
1129            }
1130
1131            toRename->iewInfo[tid].dispatchedToLSQ++;
1132#if FULL_SYSTEM
1133        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1134            // Same as non-speculative stores.
1135            inst->setCanCommit();
1136            instQueue.insertBarrier(inst);
1137            add_to_iq = false;
1138#endif
1139        } else if (inst->isNonSpeculative()) {
1140            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1141                    "encountered, skipping.\n", tid);
1142
1143            // Same as non-speculative stores.
1144            inst->setCanCommit();
1145
1146            // Specifically insert it as nonspeculative.
1147            instQueue.insertNonSpec(inst);
1148
1149            ++iewDispNonSpecInsts;
1150
1151            add_to_iq = false;
1152        } else if (inst->isNop()) {
1153            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1154                    "skipping.\n", tid);
1155
1156            inst->setIssued();
1157            inst->setExecuted();
1158            inst->setCanCommit();
1159
1160            instQueue.recordProducer(inst);
1161
1162            iewExecutedNop[tid]++;
1163
1164            add_to_iq = false;
1165        } else if (inst->isExecuted()) {
1166            assert(0 && "Instruction shouldn't be executed.\n");
1167            DPRINTF(IEW, "Issue: Executed branch encountered, "
1168                    "skipping.\n");
1169
1170            inst->setIssued();
1171            inst->setCanCommit();
1172
1173            instQueue.recordProducer(inst);
1174
1175            add_to_iq = false;
1176        } else {
1177            add_to_iq = true;
1178        }
1179
1180        // If the instruction queue is not full, then add the
1181        // instruction.
1182        if (add_to_iq) {
1183            instQueue.insert(inst);
1184        }
1185
1186        insts_to_dispatch.pop();
1187
1188        toRename->iewInfo[tid].dispatched++;
1189
1190        ++iewDispatchedInsts;
1191    }
1192
1193    if (!insts_to_dispatch.empty()) {
1194        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1195        block(tid);
1196        toRename->iewUnblock[tid] = false;
1197    }
1198
1199    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1200        dispatchStatus[tid] = Running;
1201
1202        updatedQueues = true;
1203    }
1204
1205    dis_num_inst = 0;
1206}
1207
1208template <class Impl>
1209void
1210DefaultIEW<Impl>::printAvailableInsts()
1211{
1212    int inst = 0;
1213
1214    std::cout << "Available Instructions: ";
1215
1216    while (fromIssue->insts[inst]) {
1217
1218        if (inst%3==0) std::cout << "\n\t";
1219
1220        std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1221             << " TN: " << fromIssue->insts[inst]->threadNumber
1222             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1223
1224        inst++;
1225
1226    }
1227
1228    std::cout << "\n";
1229}
1230
1231template <class Impl>
1232void
1233DefaultIEW<Impl>::executeInsts()
1234{
1235    wbNumInst = 0;
1236    wbCycle = 0;
1237
1238    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1239
1240    while (threads != (*activeThreads).end()) {
1241        unsigned tid = *threads++;
1242        fetchRedirect[tid] = false;
1243    }
1244
1245    // Uncomment this if you want to see all available instructions.
1246//    printAvailableInsts();
1247
1248    // Execute/writeback any instructions that are available.
1249    int insts_to_execute = fromIssue->size;
1250    int inst_num = 0;
1251    for (; inst_num < insts_to_execute;
1252          ++inst_num) {
1253
1254        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1255
1256        DynInstPtr inst = instQueue.getInstToExecute();
1257
1258        DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1259                inst->readPC(), inst->threadNumber,inst->seqNum);
1260
1261        // Check if the instruction is squashed; if so then skip it
1262        if (inst->isSquashed()) {
1263            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1264
1265            // Consider this instruction executed so that commit can go
1266            // ahead and retire the instruction.
1267            inst->setExecuted();
1268
1269            // Not sure if I should set this here or just let commit try to
1270            // commit any squashed instructions.  I like the latter a bit more.
1271            inst->setCanCommit();
1272
1273            ++iewExecSquashedInsts;
1274
1275            decrWb(inst->seqNum);
1276            continue;
1277        }
1278
1279        Fault fault = NoFault;
1280
1281        // Execute instruction.
1282        // Note that if the instruction faults, it will be handled
1283        // at the commit stage.
1284        if (inst->isMemRef() &&
1285            (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1286            DPRINTF(IEW, "Execute: Calculating address for memory "
1287                    "reference.\n");
1288
1289            // Tell the LDSTQ to execute this instruction (if it is a load).
1290            if (inst->isLoad()) {
1291                // Loads will mark themselves as executed, and their writeback
1292                // event adds the instruction to the queue to commit
1293                fault = ldstQueue.executeLoad(inst);
1294            } else if (inst->isStore()) {
1295                fault = ldstQueue.executeStore(inst);
1296
1297                // If the store had a fault then it may not have a mem req
1298                if (!inst->isStoreConditional() && fault == NoFault) {
1299                    inst->setExecuted();
1300
1301                    instToCommit(inst);
1302                } else if (fault != NoFault) {
1303                    // If the instruction faulted, then we need to send it along to commit
1304                    // without the instruction completing.
1305
1306                    // Send this instruction to commit, also make sure iew stage
1307                    // realizes there is activity.
1308                    inst->setExecuted();
1309
1310                    instToCommit(inst);
1311                    activityThisCycle();
1312                }
1313
1314                // Store conditionals will mark themselves as
1315                // executed, and their writeback event will add the
1316                // instruction to the queue to commit.
1317            } else {
1318                panic("Unexpected memory type!\n");
1319            }
1320
1321        } else {
1322            inst->execute();
1323
1324            inst->setExecuted();
1325
1326            instToCommit(inst);
1327        }
1328
1329        updateExeInstStats(inst);
1330
1331        // Check if branch prediction was correct, if not then we need
1332        // to tell commit to squash in flight instructions.  Only
1333        // handle this if there hasn't already been something that
1334        // redirects fetch in this group of instructions.
1335
1336        // This probably needs to prioritize the redirects if a different
1337        // scheduler is used.  Currently the scheduler schedules the oldest
1338        // instruction first, so the branch resolution order will be correct.
1339        unsigned tid = inst->threadNumber;
1340
1341        if (!fetchRedirect[tid]) {
1342
1343            if (inst->mispredicted()) {
1344                fetchRedirect[tid] = true;
1345
1346                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1347#if ISA_HAS_DELAY_SLOT
1348                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1349                        inst->nextNPC);
1350#else
1351                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1352                        inst->nextPC);
1353#endif
1354                // If incorrect, then signal the ROB that it must be squashed.
1355                squashDueToBranch(inst, tid);
1356
1357                if (inst->predTaken()) {
1358                    predictedTakenIncorrect++;
1359                } else {
1360                    predictedNotTakenIncorrect++;
1361                }
1362            } else if (ldstQueue.violation(tid)) {
1363                fetchRedirect[tid] = true;
1364
1365                // If there was an ordering violation, then get the
1366                // DynInst that caused the violation.  Note that this
1367                // clears the violation signal.
1368                DynInstPtr violator;
1369                violator = ldstQueue.getMemDepViolator(tid);
1370
1371                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1372                        "%#x, inst PC: %#x.  Addr is: %#x.\n",
1373                        violator->readPC(), inst->readPC(), inst->physEffAddr);
1374
1375                // Tell the instruction queue that a violation has occured.
1376                instQueue.violation(inst, violator);
1377
1378                // Squash.
1379                squashDueToMemOrder(inst,tid);
1380
1381                ++memOrderViolationEvents;
1382            } else if (ldstQueue.loadBlocked(tid) &&
1383                       !ldstQueue.isLoadBlockedHandled(tid)) {
1384                fetchRedirect[tid] = true;
1385
1386                DPRINTF(IEW, "Load operation couldn't execute because the "
1387                        "memory system is blocked.  PC: %#x [sn:%lli]\n",
1388                        inst->readPC(), inst->seqNum);
1389
1390                squashDueToMemBlocked(inst, tid);
1391            }
1392        }
1393    }
1394
1395    // Update and record activity if we processed any instructions.
1396    if (inst_num) {
1397        if (exeStatus == Idle) {
1398            exeStatus = Running;
1399        }
1400
1401        updatedQueues = true;
1402
1403        cpu->activityThisCycle();
1404    }
1405
1406    // Need to reset this in case a writeback event needs to write into the
1407    // iew queue.  That way the writeback event will write into the correct
1408    // spot in the queue.
1409    wbNumInst = 0;
1410}
1411
1412template <class Impl>
1413void
1414DefaultIEW<Impl>::writebackInsts()
1415{
1416    // Loop through the head of the time buffer and wake any
1417    // dependents.  These instructions are about to write back.  Also
1418    // mark scoreboard that this instruction is finally complete.
1419    // Either have IEW have direct access to scoreboard, or have this
1420    // as part of backwards communication.
1421    for (int inst_num = 0; inst_num < issueWidth &&
1422             toCommit->insts[inst_num]; inst_num++) {
1423        DynInstPtr inst = toCommit->insts[inst_num];
1424        int tid = inst->threadNumber;
1425
1426        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1427                inst->seqNum, inst->readPC());
1428
1429        iewInstsToCommit[tid]++;
1430
1431        // Some instructions will be sent to commit without having
1432        // executed because they need commit to handle them.
1433        // E.g. Uncached loads have not actually executed when they
1434        // are first sent to commit.  Instead commit must tell the LSQ
1435        // when it's ready to execute the uncached load.
1436        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1437            int dependents = instQueue.wakeDependents(inst);
1438
1439            for (int i = 0; i < inst->numDestRegs(); i++) {
1440                //mark as Ready
1441                DPRINTF(IEW,"Setting Destination Register %i\n",
1442                        inst->renamedDestRegIdx(i));
1443                scoreboard->setReg(inst->renamedDestRegIdx(i));
1444            }
1445
1446            if (dependents) {
1447                producerInst[tid]++;
1448                consumerInst[tid]+= dependents;
1449            }
1450            writebackCount[tid]++;
1451        }
1452
1453        decrWb(inst->seqNum);
1454    }
1455}
1456
1457template<class Impl>
1458void
1459DefaultIEW<Impl>::tick()
1460{
1461    wbNumInst = 0;
1462    wbCycle = 0;
1463
1464    wroteToTimeBuffer = false;
1465    updatedQueues = false;
1466
1467    sortInsts();
1468
1469    // Free function units marked as being freed this cycle.
1470    fuPool->processFreeUnits();
1471
1472    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1473
1474    // Check stall and squash signals, dispatch any instructions.
1475    while (threads != (*activeThreads).end()) {
1476           unsigned tid = *threads++;
1477
1478        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1479
1480        checkSignalsAndUpdate(tid);
1481        dispatch(tid);
1482    }
1483
1484    if (exeStatus != Squashing) {
1485        executeInsts();
1486
1487        writebackInsts();
1488
1489        // Have the instruction queue try to schedule any ready instructions.
1490        // (In actuality, this scheduling is for instructions that will
1491        // be executed next cycle.)
1492        instQueue.scheduleReadyInsts();
1493
1494        // Also should advance its own time buffers if the stage ran.
1495        // Not the best place for it, but this works (hopefully).
1496        issueToExecQueue.advance();
1497    }
1498
1499    bool broadcast_free_entries = false;
1500
1501    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1502        exeStatus = Idle;
1503        updateLSQNextCycle = false;
1504
1505        broadcast_free_entries = true;
1506    }
1507
1508    // Writeback any stores using any leftover bandwidth.
1509    ldstQueue.writebackStores();
1510
1511    // Check the committed load/store signals to see if there's a load
1512    // or store to commit.  Also check if it's being told to execute a
1513    // nonspeculative instruction.
1514    // This is pretty inefficient...
1515
1516    threads = (*activeThreads).begin();
1517    while (threads != (*activeThreads).end()) {
1518        unsigned tid = (*threads++);
1519
1520        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1521
1522        // Update structures based on instructions committed.
1523        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1524            !fromCommit->commitInfo[tid].squash &&
1525            !fromCommit->commitInfo[tid].robSquashing) {
1526
1527            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1528
1529            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1530
1531            updateLSQNextCycle = true;
1532            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1533        }
1534
1535        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1536
1537            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1538            if (fromCommit->commitInfo[tid].uncached) {
1539                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1540            } else {
1541                instQueue.scheduleNonSpec(
1542                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1543            }
1544        }
1545
1546        if (broadcast_free_entries) {
1547            toFetch->iewInfo[tid].iqCount =
1548                instQueue.getCount(tid);
1549            toFetch->iewInfo[tid].ldstqCount =
1550                ldstQueue.getCount(tid);
1551
1552            toRename->iewInfo[tid].usedIQ = true;
1553            toRename->iewInfo[tid].freeIQEntries =
1554                instQueue.numFreeEntries();
1555            toRename->iewInfo[tid].usedLSQ = true;
1556            toRename->iewInfo[tid].freeLSQEntries =
1557                ldstQueue.numFreeEntries(tid);
1558
1559            wroteToTimeBuffer = true;
1560        }
1561
1562        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1563                tid, toRename->iewInfo[tid].dispatched);
1564    }
1565
1566    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1567            "LSQ has %i free entries.\n",
1568            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1569            ldstQueue.numFreeEntries());
1570
1571    updateStatus();
1572
1573    if (wroteToTimeBuffer) {
1574        DPRINTF(Activity, "Activity this cycle.\n");
1575        cpu->activityThisCycle();
1576    }
1577}
1578
1579template <class Impl>
1580void
1581DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1582{
1583    int thread_number = inst->threadNumber;
1584
1585    //
1586    //  Pick off the software prefetches
1587    //
1588#ifdef TARGET_ALPHA
1589    if (inst->isDataPrefetch())
1590        iewExecutedSwp[thread_number]++;
1591    else
1592        iewIewExecutedcutedInsts++;
1593#else
1594    iewExecutedInsts++;
1595#endif
1596
1597    //
1598    //  Control operations
1599    //
1600    if (inst->isControl())
1601        iewExecutedBranches[thread_number]++;
1602
1603    //
1604    //  Memory operations
1605    //
1606    if (inst->isMemRef()) {
1607        iewExecutedRefs[thread_number]++;
1608
1609        if (inst->isLoad()) {
1610            iewExecLoadInsts[thread_number]++;
1611        }
1612    }
1613}
1614