iew_impl.hh revision 2935:d1223a6c9156 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew.  There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41using namespace std;
42
43template<class Impl>
44DefaultIEW<Impl>::DefaultIEW(Params *params)
45    : issueToExecQueue(params->backComSize, params->forwardComSize),
46      instQueue(params),
47      ldstQueue(params),
48      fuPool(params->fuPool),
49      commitToIEWDelay(params->commitToIEWDelay),
50      renameToIEWDelay(params->renameToIEWDelay),
51      issueToExecuteDelay(params->issueToExecuteDelay),
52      dispatchWidth(params->dispatchWidth),
53      issueWidth(params->issueWidth),
54      wbOutstanding(0),
55      wbWidth(params->wbWidth),
56      numThreads(params->numberOfThreads),
57      switchedOut(false)
58{
59    _status = Active;
60    exeStatus = Running;
61    wbStatus = Idle;
62
63    // Setup wire to read instructions coming from issue.
64    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
65
66    // Instruction queue needs the queue between issue and execute.
67    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
68
69    instQueue.setIEW(this);
70    ldstQueue.setIEW(this);
71
72    for (int i=0; i < numThreads; i++) {
73        dispatchStatus[i] = Running;
74        stalls[i].commit = false;
75        fetchRedirect[i] = false;
76        bdelayDoneSeqNum[i] = 0;
77    }
78
79    wbMax = wbWidth * params->wbDepth;
80
81    updateLSQNextCycle = false;
82
83    ableToIssue = true;
84
85    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
86}
87
88template <class Impl>
89std::string
90DefaultIEW<Impl>::name() const
91{
92    return cpu->name() + ".iew";
93}
94
95template <class Impl>
96void
97DefaultIEW<Impl>::regStats()
98{
99    using namespace Stats;
100
101    instQueue.regStats();
102    ldstQueue.regStats();
103
104    iewIdleCycles
105        .name(name() + ".iewIdleCycles")
106        .desc("Number of cycles IEW is idle");
107
108    iewSquashCycles
109        .name(name() + ".iewSquashCycles")
110        .desc("Number of cycles IEW is squashing");
111
112    iewBlockCycles
113        .name(name() + ".iewBlockCycles")
114        .desc("Number of cycles IEW is blocking");
115
116    iewUnblockCycles
117        .name(name() + ".iewUnblockCycles")
118        .desc("Number of cycles IEW is unblocking");
119
120    iewDispatchedInsts
121        .name(name() + ".iewDispatchedInsts")
122        .desc("Number of instructions dispatched to IQ");
123
124    iewDispSquashedInsts
125        .name(name() + ".iewDispSquashedInsts")
126        .desc("Number of squashed instructions skipped by dispatch");
127
128    iewDispLoadInsts
129        .name(name() + ".iewDispLoadInsts")
130        .desc("Number of dispatched load instructions");
131
132    iewDispStoreInsts
133        .name(name() + ".iewDispStoreInsts")
134        .desc("Number of dispatched store instructions");
135
136    iewDispNonSpecInsts
137        .name(name() + ".iewDispNonSpecInsts")
138        .desc("Number of dispatched non-speculative instructions");
139
140    iewIQFullEvents
141        .name(name() + ".iewIQFullEvents")
142        .desc("Number of times the IQ has become full, causing a stall");
143
144    iewLSQFullEvents
145        .name(name() + ".iewLSQFullEvents")
146        .desc("Number of times the LSQ has become full, causing a stall");
147
148    memOrderViolationEvents
149        .name(name() + ".memOrderViolationEvents")
150        .desc("Number of memory order violations");
151
152    predictedTakenIncorrect
153        .name(name() + ".predictedTakenIncorrect")
154        .desc("Number of branches that were predicted taken incorrectly");
155
156    predictedNotTakenIncorrect
157        .name(name() + ".predictedNotTakenIncorrect")
158        .desc("Number of branches that were predicted not taken incorrectly");
159
160    branchMispredicts
161        .name(name() + ".branchMispredicts")
162        .desc("Number of branch mispredicts detected at execute");
163
164    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
165
166    iewExecutedInsts
167        .name(name() + ".EXEC:insts")
168        .desc("Number of executed instructions");
169
170    iewExecLoadInsts
171        .init(cpu->number_of_threads)
172        .name(name() + ".EXEC:loads")
173        .desc("Number of load instructions executed")
174        .flags(total);
175
176    iewExecSquashedInsts
177        .name(name() + ".EXEC:squashedInsts")
178        .desc("Number of squashed instructions skipped in execute");
179
180    iewExecutedSwp
181        .init(cpu->number_of_threads)
182        .name(name() + ".EXEC:swp")
183        .desc("number of swp insts executed")
184        .flags(total);
185
186    iewExecutedNop
187        .init(cpu->number_of_threads)
188        .name(name() + ".EXEC:nop")
189        .desc("number of nop insts executed")
190        .flags(total);
191
192    iewExecutedRefs
193        .init(cpu->number_of_threads)
194        .name(name() + ".EXEC:refs")
195        .desc("number of memory reference insts executed")
196        .flags(total);
197
198    iewExecutedBranches
199        .init(cpu->number_of_threads)
200        .name(name() + ".EXEC:branches")
201        .desc("Number of branches executed")
202        .flags(total);
203
204    iewExecStoreInsts
205        .name(name() + ".EXEC:stores")
206        .desc("Number of stores executed")
207        .flags(total);
208    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
209
210    iewExecRate
211        .name(name() + ".EXEC:rate")
212        .desc("Inst execution rate")
213        .flags(total);
214
215    iewExecRate = iewExecutedInsts / cpu->numCycles;
216
217    iewInstsToCommit
218        .init(cpu->number_of_threads)
219        .name(name() + ".WB:sent")
220        .desc("cumulative count of insts sent to commit")
221        .flags(total);
222
223    writebackCount
224        .init(cpu->number_of_threads)
225        .name(name() + ".WB:count")
226        .desc("cumulative count of insts written-back")
227        .flags(total);
228
229    producerInst
230        .init(cpu->number_of_threads)
231        .name(name() + ".WB:producers")
232        .desc("num instructions producing a value")
233        .flags(total);
234
235    consumerInst
236        .init(cpu->number_of_threads)
237        .name(name() + ".WB:consumers")
238        .desc("num instructions consuming a value")
239        .flags(total);
240
241    wbPenalized
242        .init(cpu->number_of_threads)
243        .name(name() + ".WB:penalized")
244        .desc("number of instrctions required to write to 'other' IQ")
245        .flags(total);
246
247    wbPenalizedRate
248        .name(name() + ".WB:penalized_rate")
249        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
250        .flags(total);
251
252    wbPenalizedRate = wbPenalized / writebackCount;
253
254    wbFanout
255        .name(name() + ".WB:fanout")
256        .desc("average fanout of values written-back")
257        .flags(total);
258
259    wbFanout = producerInst / consumerInst;
260
261    wbRate
262        .name(name() + ".WB:rate")
263        .desc("insts written-back per cycle")
264        .flags(total);
265    wbRate = writebackCount / cpu->numCycles;
266}
267
268template<class Impl>
269void
270DefaultIEW<Impl>::initStage()
271{
272    for (int tid=0; tid < numThreads; tid++) {
273        toRename->iewInfo[tid].usedIQ = true;
274        toRename->iewInfo[tid].freeIQEntries =
275            instQueue.numFreeEntries(tid);
276
277        toRename->iewInfo[tid].usedLSQ = true;
278        toRename->iewInfo[tid].freeLSQEntries =
279            ldstQueue.numFreeEntries(tid);
280    }
281}
282
283template<class Impl>
284void
285DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
286{
287    DPRINTF(IEW, "Setting CPU pointer.\n");
288    cpu = cpu_ptr;
289
290    instQueue.setCPU(cpu_ptr);
291    ldstQueue.setCPU(cpu_ptr);
292
293    cpu->activateStage(O3CPU::IEWIdx);
294}
295
296template<class Impl>
297void
298DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
299{
300    DPRINTF(IEW, "Setting time buffer pointer.\n");
301    timeBuffer = tb_ptr;
302
303    // Setup wire to read information from time buffer, from commit.
304    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
305
306    // Setup wire to write information back to previous stages.
307    toRename = timeBuffer->getWire(0);
308
309    toFetch = timeBuffer->getWire(0);
310
311    // Instruction queue also needs main time buffer.
312    instQueue.setTimeBuffer(tb_ptr);
313}
314
315template<class Impl>
316void
317DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
318{
319    DPRINTF(IEW, "Setting rename queue pointer.\n");
320    renameQueue = rq_ptr;
321
322    // Setup wire to read information from rename queue.
323    fromRename = renameQueue->getWire(-renameToIEWDelay);
324}
325
326template<class Impl>
327void
328DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
329{
330    DPRINTF(IEW, "Setting IEW queue pointer.\n");
331    iewQueue = iq_ptr;
332
333    // Setup wire to write instructions to commit.
334    toCommit = iewQueue->getWire(0);
335}
336
337template<class Impl>
338void
339DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
340{
341    DPRINTF(IEW, "Setting active threads list pointer.\n");
342    activeThreads = at_ptr;
343
344    ldstQueue.setActiveThreads(at_ptr);
345    instQueue.setActiveThreads(at_ptr);
346}
347
348template<class Impl>
349void
350DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
351{
352    DPRINTF(IEW, "Setting scoreboard pointer.\n");
353    scoreboard = sb_ptr;
354}
355
356template <class Impl>
357bool
358DefaultIEW<Impl>::drain()
359{
360    // IEW is ready to drain at any time.
361    cpu->signalDrained();
362    return true;
363}
364
365template <class Impl>
366void
367DefaultIEW<Impl>::resume()
368{
369}
370
371template <class Impl>
372void
373DefaultIEW<Impl>::switchOut()
374{
375    // Clear any state.
376    switchedOut = true;
377
378    instQueue.switchOut();
379    ldstQueue.switchOut();
380    fuPool->switchOut();
381
382    for (int i = 0; i < numThreads; i++) {
383        while (!insts[i].empty())
384            insts[i].pop();
385        while (!skidBuffer[i].empty())
386            skidBuffer[i].pop();
387    }
388}
389
390template <class Impl>
391void
392DefaultIEW<Impl>::takeOverFrom()
393{
394    // Reset all state.
395    _status = Active;
396    exeStatus = Running;
397    wbStatus = Idle;
398    switchedOut = false;
399
400    instQueue.takeOverFrom();
401    ldstQueue.takeOverFrom();
402    fuPool->takeOverFrom();
403
404    initStage();
405    cpu->activityThisCycle();
406
407    for (int i=0; i < numThreads; i++) {
408        dispatchStatus[i] = Running;
409        stalls[i].commit = false;
410        fetchRedirect[i] = false;
411    }
412
413    updateLSQNextCycle = false;
414
415    // @todo: Fix hardcoded number
416    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
417        issueToExecQueue.advance();
418    }
419}
420
421template<class Impl>
422void
423DefaultIEW<Impl>::squash(unsigned tid)
424{
425    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
426            tid);
427
428    // Tell the IQ to start squashing.
429    instQueue.squash(tid);
430
431    // Tell the LDSTQ to start squashing.
432#if THE_ISA == ALPHA_ISA
433    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
434#else
435    ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
436#endif
437    updatedQueues = true;
438
439    // Clear the skid buffer in case it has any data in it.
440    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
441            tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
442
443    while (!skidBuffer[tid].empty()) {
444#if THE_ISA != ALPHA_ISA
445        if (skidBuffer[tid].front()->seqNum <=
446            fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
447            DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
448                    "that occur before delay slot [sn:%i].\n",
449                    fromCommit->commitInfo[tid].bdelayDoneSeqNum,
450                    tid);
451            break;
452        } else {
453            DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
454                    "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
455        }
456#endif
457        if (skidBuffer[tid].front()->isLoad() ||
458            skidBuffer[tid].front()->isStore() ) {
459            toRename->iewInfo[tid].dispatchedToLSQ++;
460        }
461
462        toRename->iewInfo[tid].dispatched++;
463
464        skidBuffer[tid].pop();
465    }
466
467    bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
468
469    emptyRenameInsts(tid);
470}
471
472template<class Impl>
473void
474DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
475{
476    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
477            "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
478
479    toCommit->squash[tid] = true;
480    toCommit->squashedSeqNum[tid] = inst->seqNum;
481    toCommit->mispredPC[tid] = inst->readPC();
482    toCommit->branchMispredict[tid] = true;
483
484#if THE_ISA == ALPHA_ISA
485    toCommit->branchTaken[tid] = inst->readNextPC() !=
486        (inst->readPC() + sizeof(TheISA::MachInst));
487    toCommit->nextPC[tid] = inst->readNextPC();
488#else
489    bool branch_taken = inst->readNextNPC() !=
490        (inst->readNextPC() + sizeof(TheISA::MachInst));
491
492    toCommit->branchTaken[tid] = branch_taken;
493
494    toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
495
496    if (inst->isCondDelaySlot() && branch_taken) {
497        toCommit->nextPC[tid] = inst->readNextPC();
498    } else {
499        toCommit->nextPC[tid] = inst->readNextNPC();
500    }
501#endif
502
503    toCommit->includeSquashInst[tid] = false;
504
505    wroteToTimeBuffer = true;
506}
507
508template<class Impl>
509void
510DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
511{
512    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
513            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
514
515    toCommit->squash[tid] = true;
516    toCommit->squashedSeqNum[tid] = inst->seqNum;
517    toCommit->nextPC[tid] = inst->readNextPC();
518
519    toCommit->includeSquashInst[tid] = false;
520
521    wroteToTimeBuffer = true;
522}
523
524template<class Impl>
525void
526DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
527{
528    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
529            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
530
531    toCommit->squash[tid] = true;
532    toCommit->squashedSeqNum[tid] = inst->seqNum;
533    toCommit->nextPC[tid] = inst->readPC();
534
535    // Must include the broadcasted SN in the squash.
536    toCommit->includeSquashInst[tid] = true;
537
538    ldstQueue.setLoadBlockedHandled(tid);
539
540    wroteToTimeBuffer = true;
541}
542
543template<class Impl>
544void
545DefaultIEW<Impl>::block(unsigned tid)
546{
547    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
548
549    if (dispatchStatus[tid] != Blocked &&
550        dispatchStatus[tid] != Unblocking) {
551        toRename->iewBlock[tid] = true;
552        wroteToTimeBuffer = true;
553    }
554
555    // Add the current inputs to the skid buffer so they can be
556    // reprocessed when this stage unblocks.
557    skidInsert(tid);
558
559    dispatchStatus[tid] = Blocked;
560}
561
562template<class Impl>
563void
564DefaultIEW<Impl>::unblock(unsigned tid)
565{
566    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
567            "buffer %u.\n",tid, tid);
568
569    // If the skid bufffer is empty, signal back to previous stages to unblock.
570    // Also switch status to running.
571    if (skidBuffer[tid].empty()) {
572        toRename->iewUnblock[tid] = true;
573        wroteToTimeBuffer = true;
574        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
575        dispatchStatus[tid] = Running;
576    }
577}
578
579template<class Impl>
580void
581DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
582{
583    instQueue.wakeDependents(inst);
584}
585
586template<class Impl>
587void
588DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
589{
590    instQueue.rescheduleMemInst(inst);
591}
592
593template<class Impl>
594void
595DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
596{
597    instQueue.replayMemInst(inst);
598}
599
600template<class Impl>
601void
602DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
603{
604    // First check the time slot that this instruction will write
605    // to.  If there are free write ports at the time, then go ahead
606    // and write the instruction to that time.  If there are not,
607    // keep looking back to see where's the first time there's a
608    // free slot.
609    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
610        ++wbNumInst;
611        if (wbNumInst == wbWidth) {
612            ++wbCycle;
613            wbNumInst = 0;
614        }
615
616        assert((wbCycle * wbWidth + wbNumInst) < wbMax);
617    }
618
619    // Add finished instruction to queue to commit.
620    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
621    (*iewQueue)[wbCycle].size++;
622}
623
624template <class Impl>
625unsigned
626DefaultIEW<Impl>::validInstsFromRename()
627{
628    unsigned inst_count = 0;
629
630    for (int i=0; i<fromRename->size; i++) {
631        if (!fromRename->insts[i]->isSquashed())
632            inst_count++;
633    }
634
635    return inst_count;
636}
637
638template<class Impl>
639void
640DefaultIEW<Impl>::skidInsert(unsigned tid)
641{
642    DynInstPtr inst = NULL;
643
644    while (!insts[tid].empty()) {
645        inst = insts[tid].front();
646
647        insts[tid].pop();
648
649        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
650                "dispatch skidBuffer %i\n",tid, inst->seqNum,
651                inst->readPC(),tid);
652
653        skidBuffer[tid].push(inst);
654    }
655
656    assert(skidBuffer[tid].size() <= skidBufferMax &&
657           "Skidbuffer Exceeded Max Size");
658}
659
660template<class Impl>
661int
662DefaultIEW<Impl>::skidCount()
663{
664    int max=0;
665
666    list<unsigned>::iterator threads = (*activeThreads).begin();
667
668    while (threads != (*activeThreads).end()) {
669        unsigned thread_count = skidBuffer[*threads++].size();
670        if (max < thread_count)
671            max = thread_count;
672    }
673
674    return max;
675}
676
677template<class Impl>
678bool
679DefaultIEW<Impl>::skidsEmpty()
680{
681    list<unsigned>::iterator threads = (*activeThreads).begin();
682
683    while (threads != (*activeThreads).end()) {
684        if (!skidBuffer[*threads++].empty())
685            return false;
686    }
687
688    return true;
689}
690
691template <class Impl>
692void
693DefaultIEW<Impl>::updateStatus()
694{
695    bool any_unblocking = false;
696
697    list<unsigned>::iterator threads = (*activeThreads).begin();
698
699    threads = (*activeThreads).begin();
700
701    while (threads != (*activeThreads).end()) {
702        unsigned tid = *threads++;
703
704        if (dispatchStatus[tid] == Unblocking) {
705            any_unblocking = true;
706            break;
707        }
708    }
709
710    // If there are no ready instructions waiting to be scheduled by the IQ,
711    // and there's no stores waiting to write back, and dispatch is not
712    // unblocking, then there is no internal activity for the IEW stage.
713    if (_status == Active && !instQueue.hasReadyInsts() &&
714        !ldstQueue.willWB() && !any_unblocking) {
715        DPRINTF(IEW, "IEW switching to idle\n");
716
717        deactivateStage();
718
719        _status = Inactive;
720    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
721                                       ldstQueue.willWB() ||
722                                       any_unblocking)) {
723        // Otherwise there is internal activity.  Set to active.
724        DPRINTF(IEW, "IEW switching to active\n");
725
726        activateStage();
727
728        _status = Active;
729    }
730}
731
732template <class Impl>
733void
734DefaultIEW<Impl>::resetEntries()
735{
736    instQueue.resetEntries();
737    ldstQueue.resetEntries();
738}
739
740template <class Impl>
741void
742DefaultIEW<Impl>::readStallSignals(unsigned tid)
743{
744    if (fromCommit->commitBlock[tid]) {
745        stalls[tid].commit = true;
746    }
747
748    if (fromCommit->commitUnblock[tid]) {
749        assert(stalls[tid].commit);
750        stalls[tid].commit = false;
751    }
752}
753
754template <class Impl>
755bool
756DefaultIEW<Impl>::checkStall(unsigned tid)
757{
758    bool ret_val(false);
759
760    if (stalls[tid].commit) {
761        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
762        ret_val = true;
763    } else if (instQueue.isFull(tid)) {
764        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
765        ret_val = true;
766    } else if (ldstQueue.isFull(tid)) {
767        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
768
769        if (ldstQueue.numLoads(tid) > 0 ) {
770
771            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
772                    tid,ldstQueue.getLoadHeadSeqNum(tid));
773        }
774
775        if (ldstQueue.numStores(tid) > 0) {
776
777            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
778                    tid,ldstQueue.getStoreHeadSeqNum(tid));
779        }
780
781        ret_val = true;
782    } else if (ldstQueue.isStalled(tid)) {
783        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
784        ret_val = true;
785    }
786
787    return ret_val;
788}
789
790template <class Impl>
791void
792DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
793{
794    // Check if there's a squash signal, squash if there is
795    // Check stall signals, block if there is.
796    // If status was Blocked
797    //     if so then go to unblocking
798    // If status was Squashing
799    //     check if squashing is not high.  Switch to running this cycle.
800
801    readStallSignals(tid);
802
803    if (fromCommit->commitInfo[tid].squash) {
804        squash(tid);
805
806        if (dispatchStatus[tid] == Blocked ||
807            dispatchStatus[tid] == Unblocking) {
808            toRename->iewUnblock[tid] = true;
809            wroteToTimeBuffer = true;
810        }
811
812        dispatchStatus[tid] = Squashing;
813
814        fetchRedirect[tid] = false;
815        return;
816    }
817
818    if (fromCommit->commitInfo[tid].robSquashing) {
819        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
820
821        dispatchStatus[tid] = Squashing;
822
823        emptyRenameInsts(tid);
824        wroteToTimeBuffer = true;
825        return;
826    }
827
828    if (checkStall(tid)) {
829        block(tid);
830        dispatchStatus[tid] = Blocked;
831        return;
832    }
833
834    if (dispatchStatus[tid] == Blocked) {
835        // Status from previous cycle was blocked, but there are no more stall
836        // conditions.  Switch over to unblocking.
837        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
838                tid);
839
840        dispatchStatus[tid] = Unblocking;
841
842        unblock(tid);
843
844        return;
845    }
846
847    if (dispatchStatus[tid] == Squashing) {
848        // Switch status to running if rename isn't being told to block or
849        // squash this cycle.
850        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
851                tid);
852
853        dispatchStatus[tid] = Running;
854
855        return;
856    }
857}
858
859template <class Impl>
860void
861DefaultIEW<Impl>::sortInsts()
862{
863    int insts_from_rename = fromRename->size;
864#ifdef DEBUG
865#if THE_ISA == ALPHA_ISA
866    for (int i = 0; i < numThreads; i++)
867        assert(insts[i].empty());
868#endif
869#endif
870    for (int i = 0; i < insts_from_rename; ++i) {
871        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
872    }
873}
874
875template <class Impl>
876void
877DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
878{
879    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
880            "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
881
882    while (!insts[tid].empty()) {
883
884#if THE_ISA != ALPHA_ISA
885        if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
886            DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
887                    " that occurs at or before delay slot [sn:%i].\n",
888                    tid, bdelayDoneSeqNum[tid]);
889            break;
890        } else {
891            DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
892                    "[sn:%i].\n", tid, insts[tid].front()->seqNum);
893        }
894#endif
895
896        if (insts[tid].front()->isLoad() ||
897            insts[tid].front()->isStore() ) {
898            toRename->iewInfo[tid].dispatchedToLSQ++;
899        }
900
901        toRename->iewInfo[tid].dispatched++;
902
903        insts[tid].pop();
904    }
905}
906
907template <class Impl>
908void
909DefaultIEW<Impl>::wakeCPU()
910{
911    cpu->wakeCPU();
912}
913
914template <class Impl>
915void
916DefaultIEW<Impl>::activityThisCycle()
917{
918    DPRINTF(Activity, "Activity this cycle.\n");
919    cpu->activityThisCycle();
920}
921
922template <class Impl>
923inline void
924DefaultIEW<Impl>::activateStage()
925{
926    DPRINTF(Activity, "Activating stage.\n");
927    cpu->activateStage(O3CPU::IEWIdx);
928}
929
930template <class Impl>
931inline void
932DefaultIEW<Impl>::deactivateStage()
933{
934    DPRINTF(Activity, "Deactivating stage.\n");
935    cpu->deactivateStage(O3CPU::IEWIdx);
936}
937
938template<class Impl>
939void
940DefaultIEW<Impl>::dispatch(unsigned tid)
941{
942    // If status is Running or idle,
943    //     call dispatchInsts()
944    // If status is Unblocking,
945    //     buffer any instructions coming from rename
946    //     continue trying to empty skid buffer
947    //     check if stall conditions have passed
948
949    if (dispatchStatus[tid] == Blocked) {
950        ++iewBlockCycles;
951
952    } else if (dispatchStatus[tid] == Squashing) {
953        ++iewSquashCycles;
954    }
955
956    // Dispatch should try to dispatch as many instructions as its bandwidth
957    // will allow, as long as it is not currently blocked.
958    if (dispatchStatus[tid] == Running ||
959        dispatchStatus[tid] == Idle) {
960        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
961                "dispatch.\n", tid);
962
963        dispatchInsts(tid);
964    } else if (dispatchStatus[tid] == Unblocking) {
965        // Make sure that the skid buffer has something in it if the
966        // status is unblocking.
967        assert(!skidsEmpty());
968
969        // If the status was unblocking, then instructions from the skid
970        // buffer were used.  Remove those instructions and handle
971        // the rest of unblocking.
972        dispatchInsts(tid);
973
974        ++iewUnblockCycles;
975
976        if (validInstsFromRename() && dispatchedAllInsts) {
977            // Add the current inputs to the skid buffer so they can be
978            // reprocessed when this stage unblocks.
979            skidInsert(tid);
980        }
981
982        unblock(tid);
983    }
984}
985
986template <class Impl>
987void
988DefaultIEW<Impl>::dispatchInsts(unsigned tid)
989{
990    dispatchedAllInsts = true;
991
992    // Obtain instructions from skid buffer if unblocking, or queue from rename
993    // otherwise.
994    std::queue<DynInstPtr> &insts_to_dispatch =
995        dispatchStatus[tid] == Unblocking ?
996        skidBuffer[tid] : insts[tid];
997
998    int insts_to_add = insts_to_dispatch.size();
999
1000    DynInstPtr inst;
1001    bool add_to_iq = false;
1002    int dis_num_inst = 0;
1003
1004    // Loop through the instructions, putting them in the instruction
1005    // queue.
1006    for ( ; dis_num_inst < insts_to_add &&
1007              dis_num_inst < dispatchWidth;
1008          ++dis_num_inst)
1009    {
1010        inst = insts_to_dispatch.front();
1011
1012        if (dispatchStatus[tid] == Unblocking) {
1013            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1014                    "buffer\n", tid);
1015        }
1016
1017        // Make sure there's a valid instruction there.
1018        assert(inst);
1019
1020        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1021                "IQ.\n",
1022                tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1023
1024        // Be sure to mark these instructions as ready so that the
1025        // commit stage can go ahead and execute them, and mark
1026        // them as issued so the IQ doesn't reprocess them.
1027
1028        // Check for squashed instructions.
1029        if (inst->isSquashed()) {
1030            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1031                    "not adding to IQ.\n", tid);
1032
1033            ++iewDispSquashedInsts;
1034
1035            insts_to_dispatch.pop();
1036
1037            //Tell Rename That An Instruction has been processed
1038            if (inst->isLoad() || inst->isStore()) {
1039                toRename->iewInfo[tid].dispatchedToLSQ++;
1040            }
1041            toRename->iewInfo[tid].dispatched++;
1042
1043            continue;
1044        }
1045
1046        // Check for full conditions.
1047        if (instQueue.isFull(tid)) {
1048            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1049
1050            // Call function to start blocking.
1051            block(tid);
1052
1053            // Set unblock to false. Special case where we are using
1054            // skidbuffer (unblocking) instructions but then we still
1055            // get full in the IQ.
1056            toRename->iewUnblock[tid] = false;
1057
1058            dispatchedAllInsts = false;
1059
1060            ++iewIQFullEvents;
1061            break;
1062        } else if (ldstQueue.isFull(tid)) {
1063            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1064
1065            // Call function to start blocking.
1066            block(tid);
1067
1068            // Set unblock to false. Special case where we are using
1069            // skidbuffer (unblocking) instructions but then we still
1070            // get full in the IQ.
1071            toRename->iewUnblock[tid] = false;
1072
1073            dispatchedAllInsts = false;
1074
1075            ++iewLSQFullEvents;
1076            break;
1077        }
1078
1079        // Otherwise issue the instruction just fine.
1080        if (inst->isLoad()) {
1081            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1082                    "encountered, adding to LSQ.\n", tid);
1083
1084            // Reserve a spot in the load store queue for this
1085            // memory access.
1086            ldstQueue.insertLoad(inst);
1087
1088            ++iewDispLoadInsts;
1089
1090            add_to_iq = true;
1091
1092            toRename->iewInfo[tid].dispatchedToLSQ++;
1093        } else if (inst->isStore()) {
1094            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1095                    "encountered, adding to LSQ.\n", tid);
1096
1097            ldstQueue.insertStore(inst);
1098
1099            ++iewDispStoreInsts;
1100
1101            if (inst->isStoreConditional()) {
1102                // Store conditionals need to be set as "canCommit()"
1103                // so that commit can process them when they reach the
1104                // head of commit.
1105                // @todo: This is somewhat specific to Alpha.
1106                inst->setCanCommit();
1107                instQueue.insertNonSpec(inst);
1108                add_to_iq = false;
1109
1110                ++iewDispNonSpecInsts;
1111            } else {
1112                add_to_iq = true;
1113            }
1114
1115            toRename->iewInfo[tid].dispatchedToLSQ++;
1116#if FULL_SYSTEM
1117        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1118            // Same as non-speculative stores.
1119            inst->setCanCommit();
1120            instQueue.insertBarrier(inst);
1121            add_to_iq = false;
1122#endif
1123        } else if (inst->isNonSpeculative()) {
1124            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1125                    "encountered, skipping.\n", tid);
1126
1127            // Same as non-speculative stores.
1128            inst->setCanCommit();
1129
1130            // Specifically insert it as nonspeculative.
1131            instQueue.insertNonSpec(inst);
1132
1133            ++iewDispNonSpecInsts;
1134
1135            add_to_iq = false;
1136        } else if (inst->isNop()) {
1137            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1138                    "skipping.\n", tid);
1139
1140            inst->setIssued();
1141            inst->setExecuted();
1142            inst->setCanCommit();
1143
1144            instQueue.recordProducer(inst);
1145
1146            iewExecutedNop[tid]++;
1147
1148            add_to_iq = false;
1149        } else if (inst->isExecuted()) {
1150            assert(0 && "Instruction shouldn't be executed.\n");
1151            DPRINTF(IEW, "Issue: Executed branch encountered, "
1152                    "skipping.\n");
1153
1154            inst->setIssued();
1155            inst->setCanCommit();
1156
1157            instQueue.recordProducer(inst);
1158
1159            add_to_iq = false;
1160        } else {
1161            add_to_iq = true;
1162        }
1163
1164        // If the instruction queue is not full, then add the
1165        // instruction.
1166        if (add_to_iq) {
1167            instQueue.insert(inst);
1168        }
1169
1170        insts_to_dispatch.pop();
1171
1172        toRename->iewInfo[tid].dispatched++;
1173
1174        ++iewDispatchedInsts;
1175    }
1176
1177    if (!insts_to_dispatch.empty()) {
1178        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1179        block(tid);
1180        toRename->iewUnblock[tid] = false;
1181    }
1182
1183    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1184        dispatchStatus[tid] = Running;
1185
1186        updatedQueues = true;
1187    }
1188
1189    dis_num_inst = 0;
1190}
1191
1192template <class Impl>
1193void
1194DefaultIEW<Impl>::printAvailableInsts()
1195{
1196    int inst = 0;
1197
1198    cout << "Available Instructions: ";
1199
1200    while (fromIssue->insts[inst]) {
1201
1202        if (inst%3==0) cout << "\n\t";
1203
1204        cout << "PC: " << fromIssue->insts[inst]->readPC()
1205             << " TN: " << fromIssue->insts[inst]->threadNumber
1206             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1207
1208        inst++;
1209
1210    }
1211
1212    cout << "\n";
1213}
1214
1215template <class Impl>
1216void
1217DefaultIEW<Impl>::executeInsts()
1218{
1219    wbNumInst = 0;
1220    wbCycle = 0;
1221
1222    list<unsigned>::iterator threads = (*activeThreads).begin();
1223
1224    while (threads != (*activeThreads).end()) {
1225        unsigned tid = *threads++;
1226        fetchRedirect[tid] = false;
1227    }
1228
1229    // Uncomment this if you want to see all available instructions.
1230//    printAvailableInsts();
1231
1232    // Execute/writeback any instructions that are available.
1233    int insts_to_execute = fromIssue->size;
1234    int inst_num = 0;
1235    for (; inst_num < insts_to_execute;
1236          ++inst_num) {
1237
1238        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1239
1240        DynInstPtr inst = instQueue.getInstToExecute();
1241
1242        DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1243                inst->readPC(), inst->threadNumber,inst->seqNum);
1244
1245        // Check if the instruction is squashed; if so then skip it
1246        if (inst->isSquashed()) {
1247            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1248
1249            // Consider this instruction executed so that commit can go
1250            // ahead and retire the instruction.
1251            inst->setExecuted();
1252
1253            // Not sure if I should set this here or just let commit try to
1254            // commit any squashed instructions.  I like the latter a bit more.
1255            inst->setCanCommit();
1256
1257            ++iewExecSquashedInsts;
1258
1259            decrWb(inst->seqNum);
1260            continue;
1261        }
1262
1263        Fault fault = NoFault;
1264
1265        // Execute instruction.
1266        // Note that if the instruction faults, it will be handled
1267        // at the commit stage.
1268        if (inst->isMemRef() &&
1269            (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1270            DPRINTF(IEW, "Execute: Calculating address for memory "
1271                    "reference.\n");
1272
1273            // Tell the LDSTQ to execute this instruction (if it is a load).
1274            if (inst->isLoad()) {
1275                // Loads will mark themselves as executed, and their writeback
1276                // event adds the instruction to the queue to commit
1277                fault = ldstQueue.executeLoad(inst);
1278            } else if (inst->isStore()) {
1279                ldstQueue.executeStore(inst);
1280
1281                // If the store had a fault then it may not have a mem req
1282                if (inst->req && !(inst->req->getFlags() & LOCKED)) {
1283                    inst->setExecuted();
1284
1285                    instToCommit(inst);
1286                }
1287
1288                // Store conditionals will mark themselves as
1289                // executed, and their writeback event will add the
1290                // instruction to the queue to commit.
1291            } else {
1292                panic("Unexpected memory type!\n");
1293            }
1294
1295        } else {
1296            inst->execute();
1297
1298            inst->setExecuted();
1299
1300            instToCommit(inst);
1301        }
1302
1303        updateExeInstStats(inst);
1304
1305        // Check if branch prediction was correct, if not then we need
1306        // to tell commit to squash in flight instructions.  Only
1307        // handle this if there hasn't already been something that
1308        // redirects fetch in this group of instructions.
1309
1310        // This probably needs to prioritize the redirects if a different
1311        // scheduler is used.  Currently the scheduler schedules the oldest
1312        // instruction first, so the branch resolution order will be correct.
1313        unsigned tid = inst->threadNumber;
1314
1315        if (!fetchRedirect[tid]) {
1316
1317            if (inst->mispredicted()) {
1318                fetchRedirect[tid] = true;
1319
1320                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1321#if THE_ISA == ALPHA_ISA
1322                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1323                        inst->nextPC);
1324#else
1325                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1326                        inst->nextNPC);
1327#endif
1328                // If incorrect, then signal the ROB that it must be squashed.
1329                squashDueToBranch(inst, tid);
1330
1331                if (inst->predTaken()) {
1332                    predictedTakenIncorrect++;
1333                } else {
1334                    predictedNotTakenIncorrect++;
1335                }
1336            } else if (ldstQueue.violation(tid)) {
1337                fetchRedirect[tid] = true;
1338
1339                // If there was an ordering violation, then get the
1340                // DynInst that caused the violation.  Note that this
1341                // clears the violation signal.
1342                DynInstPtr violator;
1343                violator = ldstQueue.getMemDepViolator(tid);
1344
1345                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1346                        "%#x, inst PC: %#x.  Addr is: %#x.\n",
1347                        violator->readPC(), inst->readPC(), inst->physEffAddr);
1348
1349                // Tell the instruction queue that a violation has occured.
1350                instQueue.violation(inst, violator);
1351
1352                // Squash.
1353                squashDueToMemOrder(inst,tid);
1354
1355                ++memOrderViolationEvents;
1356            } else if (ldstQueue.loadBlocked(tid) &&
1357                       !ldstQueue.isLoadBlockedHandled(tid)) {
1358                fetchRedirect[tid] = true;
1359
1360                DPRINTF(IEW, "Load operation couldn't execute because the "
1361                        "memory system is blocked.  PC: %#x [sn:%lli]\n",
1362                        inst->readPC(), inst->seqNum);
1363
1364                squashDueToMemBlocked(inst, tid);
1365            }
1366        }
1367    }
1368
1369    // Update and record activity if we processed any instructions.
1370    if (inst_num) {
1371        if (exeStatus == Idle) {
1372            exeStatus = Running;
1373        }
1374
1375        updatedQueues = true;
1376
1377        cpu->activityThisCycle();
1378    }
1379
1380    // Need to reset this in case a writeback event needs to write into the
1381    // iew queue.  That way the writeback event will write into the correct
1382    // spot in the queue.
1383    wbNumInst = 0;
1384}
1385
1386template <class Impl>
1387void
1388DefaultIEW<Impl>::writebackInsts()
1389{
1390    // Loop through the head of the time buffer and wake any
1391    // dependents.  These instructions are about to write back.  Also
1392    // mark scoreboard that this instruction is finally complete.
1393    // Either have IEW have direct access to scoreboard, or have this
1394    // as part of backwards communication.
1395    for (int inst_num = 0; inst_num < issueWidth &&
1396             toCommit->insts[inst_num]; inst_num++) {
1397        DynInstPtr inst = toCommit->insts[inst_num];
1398        int tid = inst->threadNumber;
1399
1400        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1401                inst->seqNum, inst->readPC());
1402
1403        iewInstsToCommit[tid]++;
1404
1405        // Some instructions will be sent to commit without having
1406        // executed because they need commit to handle them.
1407        // E.g. Uncached loads have not actually executed when they
1408        // are first sent to commit.  Instead commit must tell the LSQ
1409        // when it's ready to execute the uncached load.
1410        if (!inst->isSquashed() && inst->isExecuted()) {
1411            int dependents = instQueue.wakeDependents(inst);
1412
1413            for (int i = 0; i < inst->numDestRegs(); i++) {
1414                //mark as Ready
1415                DPRINTF(IEW,"Setting Destination Register %i\n",
1416                        inst->renamedDestRegIdx(i));
1417                scoreboard->setReg(inst->renamedDestRegIdx(i));
1418            }
1419
1420            if (dependents) {
1421                producerInst[tid]++;
1422                consumerInst[tid]+= dependents;
1423            }
1424            writebackCount[tid]++;
1425        }
1426
1427        decrWb(inst->seqNum);
1428    }
1429}
1430
1431template<class Impl>
1432void
1433DefaultIEW<Impl>::tick()
1434{
1435    wbNumInst = 0;
1436    wbCycle = 0;
1437
1438    wroteToTimeBuffer = false;
1439    updatedQueues = false;
1440
1441    sortInsts();
1442
1443    // Free function units marked as being freed this cycle.
1444    fuPool->processFreeUnits();
1445
1446    list<unsigned>::iterator threads = (*activeThreads).begin();
1447
1448    // Check stall and squash signals, dispatch any instructions.
1449    while (threads != (*activeThreads).end()) {
1450           unsigned tid = *threads++;
1451
1452        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1453
1454        checkSignalsAndUpdate(tid);
1455        dispatch(tid);
1456    }
1457
1458    if (exeStatus != Squashing) {
1459        executeInsts();
1460
1461        writebackInsts();
1462
1463        // Have the instruction queue try to schedule any ready instructions.
1464        // (In actuality, this scheduling is for instructions that will
1465        // be executed next cycle.)
1466        instQueue.scheduleReadyInsts();
1467
1468        // Also should advance its own time buffers if the stage ran.
1469        // Not the best place for it, but this works (hopefully).
1470        issueToExecQueue.advance();
1471    }
1472
1473    bool broadcast_free_entries = false;
1474
1475    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1476        exeStatus = Idle;
1477        updateLSQNextCycle = false;
1478
1479        broadcast_free_entries = true;
1480    }
1481
1482    // Writeback any stores using any leftover bandwidth.
1483    ldstQueue.writebackStores();
1484
1485    // Check the committed load/store signals to see if there's a load
1486    // or store to commit.  Also check if it's being told to execute a
1487    // nonspeculative instruction.
1488    // This is pretty inefficient...
1489
1490    threads = (*activeThreads).begin();
1491    while (threads != (*activeThreads).end()) {
1492        unsigned tid = (*threads++);
1493
1494        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1495
1496        // Update structures based on instructions committed.
1497        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1498            !fromCommit->commitInfo[tid].squash &&
1499            !fromCommit->commitInfo[tid].robSquashing) {
1500
1501            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1502
1503            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1504
1505            updateLSQNextCycle = true;
1506            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1507        }
1508
1509        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1510
1511            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1512            if (fromCommit->commitInfo[tid].uncached) {
1513                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1514            } else {
1515                instQueue.scheduleNonSpec(
1516                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1517            }
1518        }
1519
1520        if (broadcast_free_entries) {
1521            toFetch->iewInfo[tid].iqCount =
1522                instQueue.getCount(tid);
1523            toFetch->iewInfo[tid].ldstqCount =
1524                ldstQueue.getCount(tid);
1525
1526            toRename->iewInfo[tid].usedIQ = true;
1527            toRename->iewInfo[tid].freeIQEntries =
1528                instQueue.numFreeEntries();
1529            toRename->iewInfo[tid].usedLSQ = true;
1530            toRename->iewInfo[tid].freeLSQEntries =
1531                ldstQueue.numFreeEntries(tid);
1532
1533            wroteToTimeBuffer = true;
1534        }
1535
1536        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1537                tid, toRename->iewInfo[tid].dispatched);
1538    }
1539
1540    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1541            "LSQ has %i free entries.\n",
1542            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1543            ldstQueue.numFreeEntries());
1544
1545    updateStatus();
1546
1547    if (wroteToTimeBuffer) {
1548        DPRINTF(Activity, "Activity this cycle.\n");
1549        cpu->activityThisCycle();
1550    }
1551}
1552
1553template <class Impl>
1554void
1555DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1556{
1557    int thread_number = inst->threadNumber;
1558
1559    //
1560    //  Pick off the software prefetches
1561    //
1562#ifdef TARGET_ALPHA
1563    if (inst->isDataPrefetch())
1564        iewExecutedSwp[thread_number]++;
1565    else
1566        iewIewExecutedcutedInsts++;
1567#else
1568    iewExecutedInsts++;
1569#endif
1570
1571    //
1572    //  Control operations
1573    //
1574    if (inst->isControl())
1575        iewExecutedBranches[thread_number]++;
1576
1577    //
1578    //  Memory operations
1579    //
1580    if (inst->isMemRef()) {
1581        iewExecutedRefs[thread_number]++;
1582
1583        if (inst->isLoad()) {
1584            iewExecLoadInsts[thread_number]++;
1585        }
1586    }
1587}
1588