iew_impl.hh revision 2670:9107b8bd08cd 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew.  There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41using namespace std;
42
43template<class Impl>
44DefaultIEW<Impl>::DefaultIEW(Params *params)
45    : // @todo: Make this into a parameter.
46      issueToExecQueue(5, 5),
47      instQueue(params),
48      ldstQueue(params),
49      fuPool(params->fuPool),
50      commitToIEWDelay(params->commitToIEWDelay),
51      renameToIEWDelay(params->renameToIEWDelay),
52      issueToExecuteDelay(params->issueToExecuteDelay),
53      issueReadWidth(params->issueWidth),
54      issueWidth(params->issueWidth),
55      executeWidth(params->executeWidth),
56      numThreads(params->numberOfThreads),
57      switchedOut(false)
58{
59    _status = Active;
60    exeStatus = Running;
61    wbStatus = Idle;
62
63    // Setup wire to read instructions coming from issue.
64    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
65
66    // Instruction queue needs the queue between issue and execute.
67    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
68
69    instQueue.setIEW(this);
70    ldstQueue.setIEW(this);
71
72    for (int i=0; i < numThreads; i++) {
73        dispatchStatus[i] = Running;
74        stalls[i].commit = false;
75        fetchRedirect[i] = false;
76    }
77
78    updateLSQNextCycle = false;
79
80    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
81}
82
83template <class Impl>
84std::string
85DefaultIEW<Impl>::name() const
86{
87    return cpu->name() + ".iew";
88}
89
90template <class Impl>
91void
92DefaultIEW<Impl>::regStats()
93{
94    using namespace Stats;
95
96    instQueue.regStats();
97
98    iewIdleCycles
99        .name(name() + ".iewIdleCycles")
100        .desc("Number of cycles IEW is idle");
101
102    iewSquashCycles
103        .name(name() + ".iewSquashCycles")
104        .desc("Number of cycles IEW is squashing");
105
106    iewBlockCycles
107        .name(name() + ".iewBlockCycles")
108        .desc("Number of cycles IEW is blocking");
109
110    iewUnblockCycles
111        .name(name() + ".iewUnblockCycles")
112        .desc("Number of cycles IEW is unblocking");
113
114    iewDispatchedInsts
115        .name(name() + ".iewDispatchedInsts")
116        .desc("Number of instructions dispatched to IQ");
117
118    iewDispSquashedInsts
119        .name(name() + ".iewDispSquashedInsts")
120        .desc("Number of squashed instructions skipped by dispatch");
121
122    iewDispLoadInsts
123        .name(name() + ".iewDispLoadInsts")
124        .desc("Number of dispatched load instructions");
125
126    iewDispStoreInsts
127        .name(name() + ".iewDispStoreInsts")
128        .desc("Number of dispatched store instructions");
129
130    iewDispNonSpecInsts
131        .name(name() + ".iewDispNonSpecInsts")
132        .desc("Number of dispatched non-speculative instructions");
133
134    iewIQFullEvents
135        .name(name() + ".iewIQFullEvents")
136        .desc("Number of times the IQ has become full, causing a stall");
137
138    iewLSQFullEvents
139        .name(name() + ".iewLSQFullEvents")
140        .desc("Number of times the LSQ has become full, causing a stall");
141
142    iewExecutedInsts
143        .name(name() + ".iewExecutedInsts")
144        .desc("Number of executed instructions");
145
146    iewExecLoadInsts
147        .init(cpu->number_of_threads)
148        .name(name() + ".iewExecLoadInsts")
149        .desc("Number of load instructions executed")
150        .flags(total);
151
152    iewExecSquashedInsts
153        .name(name() + ".iewExecSquashedInsts")
154        .desc("Number of squashed instructions skipped in execute");
155
156    memOrderViolationEvents
157        .name(name() + ".memOrderViolationEvents")
158        .desc("Number of memory order violations");
159
160    predictedTakenIncorrect
161        .name(name() + ".predictedTakenIncorrect")
162        .desc("Number of branches that were predicted taken incorrectly");
163
164    predictedNotTakenIncorrect
165        .name(name() + ".predictedNotTakenIncorrect")
166        .desc("Number of branches that were predicted not taken incorrectly");
167
168    branchMispredicts
169        .name(name() + ".branchMispredicts")
170        .desc("Number of branch mispredicts detected at execute");
171
172    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
173
174    exeSwp
175        .init(cpu->number_of_threads)
176        .name(name() + ".EXEC:swp")
177        .desc("number of swp insts executed")
178        .flags(total)
179        ;
180
181    exeNop
182        .init(cpu->number_of_threads)
183        .name(name() + ".EXEC:nop")
184        .desc("number of nop insts executed")
185        .flags(total)
186        ;
187
188    exeRefs
189        .init(cpu->number_of_threads)
190        .name(name() + ".EXEC:refs")
191        .desc("number of memory reference insts executed")
192        .flags(total)
193        ;
194
195    exeBranches
196        .init(cpu->number_of_threads)
197        .name(name() + ".EXEC:branches")
198        .desc("Number of branches executed")
199        .flags(total)
200        ;
201
202    issueRate
203        .name(name() + ".EXEC:rate")
204        .desc("Inst execution rate")
205        .flags(total)
206        ;
207    issueRate = iewExecutedInsts / cpu->numCycles;
208
209    iewExecStoreInsts
210        .name(name() + ".EXEC:stores")
211        .desc("Number of stores executed")
212        .flags(total)
213        ;
214    iewExecStoreInsts = exeRefs - iewExecLoadInsts;
215/*
216    for (int i=0; i<Num_OpClasses; ++i) {
217        stringstream subname;
218        subname << opClassStrings[i] << "_delay";
219        issue_delay_dist.subname(i, subname.str());
220    }
221*/
222    //
223    //  Other stats
224    //
225
226    iewInstsToCommit
227        .init(cpu->number_of_threads)
228        .name(name() + ".WB:sent")
229        .desc("cumulative count of insts sent to commit")
230        .flags(total)
231        ;
232
233    writebackCount
234        .init(cpu->number_of_threads)
235        .name(name() + ".WB:count")
236        .desc("cumulative count of insts written-back")
237        .flags(total)
238        ;
239
240    producerInst
241        .init(cpu->number_of_threads)
242        .name(name() + ".WB:producers")
243        .desc("num instructions producing a value")
244        .flags(total)
245        ;
246
247    consumerInst
248        .init(cpu->number_of_threads)
249        .name(name() + ".WB:consumers")
250        .desc("num instructions consuming a value")
251        .flags(total)
252        ;
253
254    wbPenalized
255        .init(cpu->number_of_threads)
256        .name(name() + ".WB:penalized")
257        .desc("number of instrctions required to write to 'other' IQ")
258        .flags(total)
259        ;
260
261    wbPenalizedRate
262        .name(name() + ".WB:penalized_rate")
263        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
264        .flags(total)
265        ;
266
267    wbPenalizedRate = wbPenalized / writebackCount;
268
269    wbFanout
270        .name(name() + ".WB:fanout")
271        .desc("average fanout of values written-back")
272        .flags(total)
273        ;
274
275    wbFanout = producerInst / consumerInst;
276
277    wbRate
278        .name(name() + ".WB:rate")
279        .desc("insts written-back per cycle")
280        .flags(total)
281        ;
282    wbRate = writebackCount / cpu->numCycles;
283}
284
285template<class Impl>
286void
287DefaultIEW<Impl>::initStage()
288{
289    for (int tid=0; tid < numThreads; tid++) {
290        toRename->iewInfo[tid].usedIQ = true;
291        toRename->iewInfo[tid].freeIQEntries =
292            instQueue.numFreeEntries(tid);
293
294        toRename->iewInfo[tid].usedLSQ = true;
295        toRename->iewInfo[tid].freeLSQEntries =
296            ldstQueue.numFreeEntries(tid);
297    }
298}
299
300template<class Impl>
301void
302DefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr)
303{
304    DPRINTF(IEW, "Setting CPU pointer.\n");
305    cpu = cpu_ptr;
306
307    instQueue.setCPU(cpu_ptr);
308    ldstQueue.setCPU(cpu_ptr);
309
310    cpu->activateStage(FullCPU::IEWIdx);
311}
312
313template<class Impl>
314void
315DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
316{
317    DPRINTF(IEW, "Setting time buffer pointer.\n");
318    timeBuffer = tb_ptr;
319
320    // Setup wire to read information from time buffer, from commit.
321    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
322
323    // Setup wire to write information back to previous stages.
324    toRename = timeBuffer->getWire(0);
325
326    toFetch = timeBuffer->getWire(0);
327
328    // Instruction queue also needs main time buffer.
329    instQueue.setTimeBuffer(tb_ptr);
330}
331
332template<class Impl>
333void
334DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
335{
336    DPRINTF(IEW, "Setting rename queue pointer.\n");
337    renameQueue = rq_ptr;
338
339    // Setup wire to read information from rename queue.
340    fromRename = renameQueue->getWire(-renameToIEWDelay);
341}
342
343template<class Impl>
344void
345DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
346{
347    DPRINTF(IEW, "Setting IEW queue pointer.\n");
348    iewQueue = iq_ptr;
349
350    // Setup wire to write instructions to commit.
351    toCommit = iewQueue->getWire(0);
352}
353
354template<class Impl>
355void
356DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
357{
358    DPRINTF(IEW, "Setting active threads list pointer.\n");
359    activeThreads = at_ptr;
360
361    ldstQueue.setActiveThreads(at_ptr);
362    instQueue.setActiveThreads(at_ptr);
363}
364
365template<class Impl>
366void
367DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
368{
369    DPRINTF(IEW, "Setting scoreboard pointer.\n");
370    scoreboard = sb_ptr;
371}
372
373#if 0
374template<class Impl>
375void
376DefaultIEW<Impl>::setPageTable(PageTable *pt_ptr)
377{
378    ldstQueue.setPageTable(pt_ptr);
379}
380#endif
381
382template <class Impl>
383void
384DefaultIEW<Impl>::switchOut()
385{
386    cpu->signalSwitched();
387}
388
389template <class Impl>
390void
391DefaultIEW<Impl>::doSwitchOut()
392{
393    switchedOut = true;
394
395    instQueue.switchOut();
396    ldstQueue.switchOut();
397    fuPool->switchOut();
398
399    for (int i = 0; i < numThreads; i++) {
400        while (!insts[i].empty())
401            insts[i].pop();
402        while (!skidBuffer[i].empty())
403            skidBuffer[i].pop();
404    }
405}
406
407template <class Impl>
408void
409DefaultIEW<Impl>::takeOverFrom()
410{
411    _status = Active;
412    exeStatus = Running;
413    wbStatus = Idle;
414    switchedOut = false;
415
416    instQueue.takeOverFrom();
417    ldstQueue.takeOverFrom();
418    fuPool->takeOverFrom();
419
420    initStage();
421    cpu->activityThisCycle();
422
423    for (int i=0; i < numThreads; i++) {
424        dispatchStatus[i] = Running;
425        stalls[i].commit = false;
426        fetchRedirect[i] = false;
427    }
428
429    updateLSQNextCycle = false;
430
431    // @todo: Fix hardcoded number
432    for (int i = 0; i < 6; ++i) {
433        issueToExecQueue.advance();
434    }
435}
436
437template<class Impl>
438void
439DefaultIEW<Impl>::squash(unsigned tid)
440{
441    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
442            tid);
443
444    // Tell the IQ to start squashing.
445    instQueue.squash(tid);
446
447    // Tell the LDSTQ to start squashing.
448    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
449
450    updatedQueues = true;
451
452    // Clear the skid buffer in case it has any data in it.
453    while (!skidBuffer[tid].empty()) {
454
455        if (skidBuffer[tid].front()->isLoad() ||
456            skidBuffer[tid].front()->isStore() ) {
457            toRename->iewInfo[tid].dispatchedToLSQ++;
458        }
459
460        toRename->iewInfo[tid].dispatched++;
461
462        skidBuffer[tid].pop();
463    }
464
465    while (!insts[tid].empty()) {
466        if (insts[tid].front()->isLoad() ||
467            insts[tid].front()->isStore() ) {
468            toRename->iewInfo[tid].dispatchedToLSQ++;
469        }
470
471        toRename->iewInfo[tid].dispatched++;
472
473        insts[tid].pop();
474    }
475}
476
477template<class Impl>
478void
479DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
480{
481    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
482            "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
483
484    toCommit->squash[tid] = true;
485    toCommit->squashedSeqNum[tid] = inst->seqNum;
486    toCommit->mispredPC[tid] = inst->readPC();
487    toCommit->nextPC[tid] = inst->readNextPC();
488    toCommit->branchMispredict[tid] = true;
489    toCommit->branchTaken[tid] = inst->readNextPC() !=
490        (inst->readPC() + sizeof(TheISA::MachInst));
491
492    toCommit->includeSquashInst[tid] = false;
493
494    wroteToTimeBuffer = true;
495}
496
497template<class Impl>
498void
499DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
500{
501    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
502            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
503
504    toCommit->squash[tid] = true;
505    toCommit->squashedSeqNum[tid] = inst->seqNum;
506    toCommit->nextPC[tid] = inst->readNextPC();
507
508    toCommit->includeSquashInst[tid] = false;
509
510    wroteToTimeBuffer = true;
511}
512
513template<class Impl>
514void
515DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
516{
517    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
518            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
519
520    toCommit->squash[tid] = true;
521    toCommit->squashedSeqNum[tid] = inst->seqNum;
522    toCommit->nextPC[tid] = inst->readPC();
523
524    toCommit->includeSquashInst[tid] = true;
525
526    ldstQueue.setLoadBlockedHandled(tid);
527
528    wroteToTimeBuffer = true;
529}
530
531template<class Impl>
532void
533DefaultIEW<Impl>::block(unsigned tid)
534{
535    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
536
537    if (dispatchStatus[tid] != Blocked &&
538        dispatchStatus[tid] != Unblocking) {
539        toRename->iewBlock[tid] = true;
540        wroteToTimeBuffer = true;
541    }
542
543    // Add the current inputs to the skid buffer so they can be
544    // reprocessed when this stage unblocks.
545    skidInsert(tid);
546
547    dispatchStatus[tid] = Blocked;
548}
549
550template<class Impl>
551void
552DefaultIEW<Impl>::unblock(unsigned tid)
553{
554    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
555            "buffer %u.\n",tid, tid);
556
557    // If the skid bufffer is empty, signal back to previous stages to unblock.
558    // Also switch status to running.
559    if (skidBuffer[tid].empty()) {
560        toRename->iewUnblock[tid] = true;
561        wroteToTimeBuffer = true;
562        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
563        dispatchStatus[tid] = Running;
564    }
565}
566
567template<class Impl>
568void
569DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
570{
571    instQueue.wakeDependents(inst);
572}
573
574template<class Impl>
575void
576DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
577{
578    instQueue.rescheduleMemInst(inst);
579}
580
581template<class Impl>
582void
583DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
584{
585    instQueue.replayMemInst(inst);
586}
587
588template<class Impl>
589void
590DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
591{
592    // First check the time slot that this instruction will write
593    // to.  If there are free write ports at the time, then go ahead
594    // and write the instruction to that time.  If there are not,
595    // keep looking back to see where's the first time there's a
596    // free slot.
597    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
598        ++wbNumInst;
599        if (wbNumInst == issueWidth) {
600            ++wbCycle;
601            wbNumInst = 0;
602        }
603
604        assert(wbCycle < 5);
605    }
606
607    // Add finished instruction to queue to commit.
608    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
609    (*iewQueue)[wbCycle].size++;
610}
611
612template <class Impl>
613unsigned
614DefaultIEW<Impl>::validInstsFromRename()
615{
616    unsigned inst_count = 0;
617
618    for (int i=0; i<fromRename->size; i++) {
619        if (!fromRename->insts[i]->squashed)
620            inst_count++;
621    }
622
623    return inst_count;
624}
625
626template<class Impl>
627void
628DefaultIEW<Impl>::skidInsert(unsigned tid)
629{
630    DynInstPtr inst = NULL;
631
632    while (!insts[tid].empty()) {
633        inst = insts[tid].front();
634
635        insts[tid].pop();
636
637        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
638                "dispatch skidBuffer %i\n",tid, inst->seqNum,
639                inst->readPC(),tid);
640
641        skidBuffer[tid].push(inst);
642    }
643
644    assert(skidBuffer[tid].size() <= skidBufferMax &&
645           "Skidbuffer Exceeded Max Size");
646}
647
648template<class Impl>
649int
650DefaultIEW<Impl>::skidCount()
651{
652    int max=0;
653
654    list<unsigned>::iterator threads = (*activeThreads).begin();
655
656    while (threads != (*activeThreads).end()) {
657        unsigned thread_count = skidBuffer[*threads++].size();
658        if (max < thread_count)
659            max = thread_count;
660    }
661
662    return max;
663}
664
665template<class Impl>
666bool
667DefaultIEW<Impl>::skidsEmpty()
668{
669    list<unsigned>::iterator threads = (*activeThreads).begin();
670
671    while (threads != (*activeThreads).end()) {
672        if (!skidBuffer[*threads++].empty())
673            return false;
674    }
675
676    return true;
677}
678
679template <class Impl>
680void
681DefaultIEW<Impl>::updateStatus()
682{
683    bool any_unblocking = false;
684
685    list<unsigned>::iterator threads = (*activeThreads).begin();
686
687    threads = (*activeThreads).begin();
688
689    while (threads != (*activeThreads).end()) {
690        unsigned tid = *threads++;
691
692        if (dispatchStatus[tid] == Unblocking) {
693            any_unblocking = true;
694            break;
695        }
696    }
697
698    // If there are no ready instructions waiting to be scheduled by the IQ,
699    // and there's no stores waiting to write back, and dispatch is not
700    // unblocking, then there is no internal activity for the IEW stage.
701    if (_status == Active && !instQueue.hasReadyInsts() &&
702        !ldstQueue.willWB() && !any_unblocking) {
703        DPRINTF(IEW, "IEW switching to idle\n");
704
705        deactivateStage();
706
707        _status = Inactive;
708    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
709                                       ldstQueue.willWB() ||
710                                       any_unblocking)) {
711        // Otherwise there is internal activity.  Set to active.
712        DPRINTF(IEW, "IEW switching to active\n");
713
714        activateStage();
715
716        _status = Active;
717    }
718}
719
720template <class Impl>
721void
722DefaultIEW<Impl>::resetEntries()
723{
724    instQueue.resetEntries();
725    ldstQueue.resetEntries();
726}
727
728template <class Impl>
729void
730DefaultIEW<Impl>::readStallSignals(unsigned tid)
731{
732    if (fromCommit->commitBlock[tid]) {
733        stalls[tid].commit = true;
734    }
735
736    if (fromCommit->commitUnblock[tid]) {
737        assert(stalls[tid].commit);
738        stalls[tid].commit = false;
739    }
740}
741
742template <class Impl>
743bool
744DefaultIEW<Impl>::checkStall(unsigned tid)
745{
746    bool ret_val(false);
747
748    if (stalls[tid].commit) {
749        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
750        ret_val = true;
751    } else if (instQueue.isFull(tid)) {
752        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
753        ret_val = true;
754    } else if (ldstQueue.isFull(tid)) {
755        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
756
757        if (ldstQueue.numLoads(tid) > 0 ) {
758
759            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
760                    tid,ldstQueue.getLoadHeadSeqNum(tid));
761        }
762
763        if (ldstQueue.numStores(tid) > 0) {
764
765            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
766                    tid,ldstQueue.getStoreHeadSeqNum(tid));
767        }
768
769        ret_val = true;
770    } else if (ldstQueue.isStalled(tid)) {
771        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
772        ret_val = true;
773    }
774
775    return ret_val;
776}
777
778template <class Impl>
779void
780DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
781{
782    // Check if there's a squash signal, squash if there is
783    // Check stall signals, block if there is.
784    // If status was Blocked
785    //     if so then go to unblocking
786    // If status was Squashing
787    //     check if squashing is not high.  Switch to running this cycle.
788
789    readStallSignals(tid);
790
791    if (fromCommit->commitInfo[tid].squash) {
792        squash(tid);
793
794        if (dispatchStatus[tid] == Blocked ||
795            dispatchStatus[tid] == Unblocking) {
796            toRename->iewUnblock[tid] = true;
797            wroteToTimeBuffer = true;
798        }
799
800        dispatchStatus[tid] = Squashing;
801
802        fetchRedirect[tid] = false;
803        return;
804    }
805
806    if (fromCommit->commitInfo[tid].robSquashing) {
807        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n");
808
809        dispatchStatus[tid] = Squashing;
810
811        return;
812    }
813
814    if (checkStall(tid)) {
815        block(tid);
816        dispatchStatus[tid] = Blocked;
817        return;
818    }
819
820    if (dispatchStatus[tid] == Blocked) {
821        // Status from previous cycle was blocked, but there are no more stall
822        // conditions.  Switch over to unblocking.
823        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
824                tid);
825
826        dispatchStatus[tid] = Unblocking;
827
828        unblock(tid);
829
830        return;
831    }
832
833    if (dispatchStatus[tid] == Squashing) {
834        // Switch status to running if rename isn't being told to block or
835        // squash this cycle.
836        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
837                tid);
838
839        dispatchStatus[tid] = Running;
840
841        return;
842    }
843}
844
845template <class Impl>
846void
847DefaultIEW<Impl>::sortInsts()
848{
849    int insts_from_rename = fromRename->size;
850#ifdef DEBUG
851    for (int i = 0; i < numThreads; i++)
852        assert(insts[i].empty());
853#endif
854    for (int i = 0; i < insts_from_rename; ++i) {
855        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
856    }
857}
858
859template <class Impl>
860void
861DefaultIEW<Impl>::wakeCPU()
862{
863    cpu->wakeCPU();
864}
865
866template <class Impl>
867void
868DefaultIEW<Impl>::activityThisCycle()
869{
870    DPRINTF(Activity, "Activity this cycle.\n");
871    cpu->activityThisCycle();
872}
873
874template <class Impl>
875inline void
876DefaultIEW<Impl>::activateStage()
877{
878    DPRINTF(Activity, "Activating stage.\n");
879    cpu->activateStage(FullCPU::IEWIdx);
880}
881
882template <class Impl>
883inline void
884DefaultIEW<Impl>::deactivateStage()
885{
886    DPRINTF(Activity, "Deactivating stage.\n");
887    cpu->deactivateStage(FullCPU::IEWIdx);
888}
889
890template<class Impl>
891void
892DefaultIEW<Impl>::dispatch(unsigned tid)
893{
894    // If status is Running or idle,
895    //     call dispatchInsts()
896    // If status is Unblocking,
897    //     buffer any instructions coming from rename
898    //     continue trying to empty skid buffer
899    //     check if stall conditions have passed
900
901    if (dispatchStatus[tid] == Blocked) {
902        ++iewBlockCycles;
903
904    } else if (dispatchStatus[tid] == Squashing) {
905        ++iewSquashCycles;
906    }
907
908    // Dispatch should try to dispatch as many instructions as its bandwidth
909    // will allow, as long as it is not currently blocked.
910    if (dispatchStatus[tid] == Running ||
911        dispatchStatus[tid] == Idle) {
912        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
913                "dispatch.\n", tid);
914
915        dispatchInsts(tid);
916    } else if (dispatchStatus[tid] == Unblocking) {
917        // Make sure that the skid buffer has something in it if the
918        // status is unblocking.
919        assert(!skidsEmpty());
920
921        // If the status was unblocking, then instructions from the skid
922        // buffer were used.  Remove those instructions and handle
923        // the rest of unblocking.
924        dispatchInsts(tid);
925
926        ++iewUnblockCycles;
927
928        if (validInstsFromRename() && dispatchedAllInsts) {
929            // Add the current inputs to the skid buffer so they can be
930            // reprocessed when this stage unblocks.
931            skidInsert(tid);
932        }
933
934        unblock(tid);
935    }
936}
937
938template <class Impl>
939void
940DefaultIEW<Impl>::dispatchInsts(unsigned tid)
941{
942    dispatchedAllInsts = true;
943
944    // Obtain instructions from skid buffer if unblocking, or queue from rename
945    // otherwise.
946    std::queue<DynInstPtr> &insts_to_dispatch =
947        dispatchStatus[tid] == Unblocking ?
948        skidBuffer[tid] : insts[tid];
949
950    int insts_to_add = insts_to_dispatch.size();
951
952    DynInstPtr inst;
953    bool add_to_iq = false;
954    int dis_num_inst = 0;
955
956    // Loop through the instructions, putting them in the instruction
957    // queue.
958    for ( ; dis_num_inst < insts_to_add &&
959              dis_num_inst < issueReadWidth;
960          ++dis_num_inst)
961    {
962        inst = insts_to_dispatch.front();
963
964        if (dispatchStatus[tid] == Unblocking) {
965            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
966                    "buffer\n", tid);
967        }
968
969        // Make sure there's a valid instruction there.
970        assert(inst);
971
972        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
973                "IQ.\n",
974                tid, inst->readPC(), inst->seqNum, inst->threadNumber);
975
976        // Be sure to mark these instructions as ready so that the
977        // commit stage can go ahead and execute them, and mark
978        // them as issued so the IQ doesn't reprocess them.
979
980        // Check for squashed instructions.
981        if (inst->isSquashed()) {
982            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
983                    "not adding to IQ.\n", tid);
984
985            ++iewDispSquashedInsts;
986
987            insts_to_dispatch.pop();
988
989            //Tell Rename That An Instruction has been processed
990            if (inst->isLoad() || inst->isStore()) {
991                toRename->iewInfo[tid].dispatchedToLSQ++;
992            }
993            toRename->iewInfo[tid].dispatched++;
994
995            continue;
996        }
997
998        // Check for full conditions.
999        if (instQueue.isFull(tid)) {
1000            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1001
1002            // Call function to start blocking.
1003            block(tid);
1004
1005            // Set unblock to false. Special case where we are using
1006            // skidbuffer (unblocking) instructions but then we still
1007            // get full in the IQ.
1008            toRename->iewUnblock[tid] = false;
1009
1010            dispatchedAllInsts = false;
1011
1012            ++iewIQFullEvents;
1013            break;
1014        } else if (ldstQueue.isFull(tid)) {
1015            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1016
1017            // Call function to start blocking.
1018            block(tid);
1019
1020            // Set unblock to false. Special case where we are using
1021            // skidbuffer (unblocking) instructions but then we still
1022            // get full in the IQ.
1023            toRename->iewUnblock[tid] = false;
1024
1025            dispatchedAllInsts = false;
1026
1027            ++iewLSQFullEvents;
1028            break;
1029        }
1030
1031        // Otherwise issue the instruction just fine.
1032        if (inst->isLoad()) {
1033            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1034                    "encountered, adding to LSQ.\n", tid);
1035
1036            // Reserve a spot in the load store queue for this
1037            // memory access.
1038            ldstQueue.insertLoad(inst);
1039
1040            ++iewDispLoadInsts;
1041
1042            add_to_iq = true;
1043
1044            toRename->iewInfo[tid].dispatchedToLSQ++;
1045        } else if (inst->isStore()) {
1046            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1047                    "encountered, adding to LSQ.\n", tid);
1048
1049            ldstQueue.insertStore(inst);
1050
1051            ++iewDispStoreInsts;
1052
1053            if (inst->isStoreConditional()) {
1054                // Store conditionals need to be set as "canCommit()"
1055                // so that commit can process them when they reach the
1056                // head of commit.
1057                inst->setCanCommit();
1058                instQueue.insertNonSpec(inst);
1059                add_to_iq = false;
1060
1061                ++iewDispNonSpecInsts;
1062            } else {
1063                add_to_iq = true;
1064            }
1065
1066            toRename->iewInfo[tid].dispatchedToLSQ++;
1067#if FULL_SYSTEM
1068        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1069            // Same as non-speculative stores.
1070            inst->setCanCommit();
1071            instQueue.insertBarrier(inst);
1072            add_to_iq = false;
1073#endif
1074        } else if (inst->isNonSpeculative()) {
1075            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1076                    "encountered, skipping.\n", tid);
1077
1078            // Same as non-speculative stores.
1079            inst->setCanCommit();
1080
1081            // Specifically insert it as nonspeculative.
1082            instQueue.insertNonSpec(inst);
1083
1084            ++iewDispNonSpecInsts;
1085
1086            add_to_iq = false;
1087        } else if (inst->isNop()) {
1088            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1089                    "skipping.\n", tid);
1090
1091            inst->setIssued();
1092            inst->setExecuted();
1093            inst->setCanCommit();
1094
1095            instQueue.recordProducer(inst);
1096
1097            exeNop[tid]++;
1098
1099            add_to_iq = false;
1100        } else if (inst->isExecuted()) {
1101            assert(0 && "Instruction shouldn't be executed.\n");
1102            DPRINTF(IEW, "Issue: Executed branch encountered, "
1103                    "skipping.\n");
1104
1105            inst->setIssued();
1106            inst->setCanCommit();
1107
1108            instQueue.recordProducer(inst);
1109
1110            add_to_iq = false;
1111        } else {
1112            add_to_iq = true;
1113        }
1114
1115        // If the instruction queue is not full, then add the
1116        // instruction.
1117        if (add_to_iq) {
1118            instQueue.insert(inst);
1119        }
1120
1121        insts_to_dispatch.pop();
1122
1123        toRename->iewInfo[tid].dispatched++;
1124
1125        ++iewDispatchedInsts;
1126    }
1127
1128    if (!insts_to_dispatch.empty()) {
1129        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
1130        block(tid);
1131        toRename->iewUnblock[tid] = false;
1132    }
1133
1134    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1135        dispatchStatus[tid] = Running;
1136
1137        updatedQueues = true;
1138    }
1139
1140    dis_num_inst = 0;
1141}
1142
1143template <class Impl>
1144void
1145DefaultIEW<Impl>::printAvailableInsts()
1146{
1147    int inst = 0;
1148
1149    cout << "Available Instructions: ";
1150
1151    while (fromIssue->insts[inst]) {
1152
1153        if (inst%3==0) cout << "\n\t";
1154
1155        cout << "PC: " << fromIssue->insts[inst]->readPC()
1156             << " TN: " << fromIssue->insts[inst]->threadNumber
1157             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1158
1159        inst++;
1160
1161    }
1162
1163    cout << "\n";
1164}
1165
1166template <class Impl>
1167void
1168DefaultIEW<Impl>::executeInsts()
1169{
1170    wbNumInst = 0;
1171    wbCycle = 0;
1172
1173    list<unsigned>::iterator threads = (*activeThreads).begin();
1174
1175    while (threads != (*activeThreads).end()) {
1176        unsigned tid = *threads++;
1177        fetchRedirect[tid] = false;
1178    }
1179
1180#if 0
1181    printAvailableInsts();
1182#endif
1183
1184    // Execute/writeback any instructions that are available.
1185    int insts_to_execute = fromIssue->size;
1186    int inst_num = 0;
1187    for (; inst_num < insts_to_execute;
1188          ++inst_num) {
1189
1190        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1191
1192        DynInstPtr inst = instQueue.getInstToExecute();
1193
1194        DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1195                inst->readPC(), inst->threadNumber,inst->seqNum);
1196
1197        // Check if the instruction is squashed; if so then skip it
1198        if (inst->isSquashed()) {
1199            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1200
1201            // Consider this instruction executed so that commit can go
1202            // ahead and retire the instruction.
1203            inst->setExecuted();
1204
1205            // Not sure if I should set this here or just let commit try to
1206            // commit any squashed instructions.  I like the latter a bit more.
1207            inst->setCanCommit();
1208
1209            ++iewExecSquashedInsts;
1210
1211            continue;
1212        }
1213
1214        Fault fault = NoFault;
1215
1216        // Execute instruction.
1217        // Note that if the instruction faults, it will be handled
1218        // at the commit stage.
1219        if (inst->isMemRef() &&
1220            (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1221            DPRINTF(IEW, "Execute: Calculating address for memory "
1222                    "reference.\n");
1223
1224            // Tell the LDSTQ to execute this instruction (if it is a load).
1225            if (inst->isLoad()) {
1226                // Loads will mark themselves as executed, and their writeback
1227                // event adds the instruction to the queue to commit
1228                fault = ldstQueue.executeLoad(inst);
1229            } else if (inst->isStore()) {
1230                ldstQueue.executeStore(inst);
1231
1232                // If the store had a fault then it may not have a mem req
1233                if (inst->req && !(inst->req->getFlags() & LOCKED)) {
1234                    inst->setExecuted();
1235
1236                    instToCommit(inst);
1237                }
1238
1239                // Store conditionals will mark themselves as
1240                // executed, and their writeback event will add the
1241                // instruction to the queue to commit.
1242            } else {
1243                panic("Unexpected memory type!\n");
1244            }
1245
1246        } else {
1247            inst->execute();
1248
1249            inst->setExecuted();
1250
1251            instToCommit(inst);
1252        }
1253
1254        updateExeInstStats(inst);
1255
1256        // Check if branch prediction was correct, if not then we need
1257        // to tell commit to squash in flight instructions.  Only
1258        // handle this if there hasn't already been something that
1259        // redirects fetch in this group of instructions.
1260
1261        // This probably needs to prioritize the redirects if a different
1262        // scheduler is used.  Currently the scheduler schedules the oldest
1263        // instruction first, so the branch resolution order will be correct.
1264        unsigned tid = inst->threadNumber;
1265
1266        if (!fetchRedirect[tid]) {
1267
1268            if (inst->mispredicted()) {
1269                fetchRedirect[tid] = true;
1270
1271                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1272                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1273                        inst->nextPC);
1274
1275                // If incorrect, then signal the ROB that it must be squashed.
1276                squashDueToBranch(inst, tid);
1277
1278                if (inst->predTaken()) {
1279                    predictedTakenIncorrect++;
1280                } else {
1281                    predictedNotTakenIncorrect++;
1282                }
1283            } else if (ldstQueue.violation(tid)) {
1284                fetchRedirect[tid] = true;
1285
1286                // If there was an ordering violation, then get the
1287                // DynInst that caused the violation.  Note that this
1288                // clears the violation signal.
1289                DynInstPtr violator;
1290                violator = ldstQueue.getMemDepViolator(tid);
1291
1292                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1293                        "%#x, inst PC: %#x.  Addr is: %#x.\n",
1294                        violator->readPC(), inst->readPC(), inst->physEffAddr);
1295
1296                // Tell the instruction queue that a violation has occured.
1297                instQueue.violation(inst, violator);
1298
1299                // Squash.
1300                squashDueToMemOrder(inst,tid);
1301
1302                ++memOrderViolationEvents;
1303            } else if (ldstQueue.loadBlocked(tid) &&
1304                       !ldstQueue.isLoadBlockedHandled(tid)) {
1305                fetchRedirect[tid] = true;
1306
1307                DPRINTF(IEW, "Load operation couldn't execute because the "
1308                        "memory system is blocked.  PC: %#x [sn:%lli]\n",
1309                        inst->readPC(), inst->seqNum);
1310
1311                squashDueToMemBlocked(inst, tid);
1312            }
1313        }
1314    }
1315
1316    if (inst_num) {
1317        if (exeStatus == Idle) {
1318            exeStatus = Running;
1319        }
1320
1321        updatedQueues = true;
1322
1323        cpu->activityThisCycle();
1324    }
1325
1326    // Need to reset this in case a writeback event needs to write into the
1327    // iew queue.  That way the writeback event will write into the correct
1328    // spot in the queue.
1329    wbNumInst = 0;
1330}
1331
1332template <class Impl>
1333void
1334DefaultIEW<Impl>::writebackInsts()
1335{
1336    // Loop through the head of the time buffer and wake any
1337    // dependents.  These instructions are about to write back.  Also
1338    // mark scoreboard that this instruction is finally complete.
1339    // Either have IEW have direct access to scoreboard, or have this
1340    // as part of backwards communication.
1341    for (int inst_num = 0; inst_num < issueWidth &&
1342             toCommit->insts[inst_num]; inst_num++) {
1343        DynInstPtr inst = toCommit->insts[inst_num];
1344        int tid = inst->threadNumber;
1345
1346        DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n",
1347                inst->readPC());
1348
1349        iewInstsToCommit[tid]++;
1350
1351        // Some instructions will be sent to commit without having
1352        // executed because they need commit to handle them.
1353        // E.g. Uncached loads have not actually executed when they
1354        // are first sent to commit.  Instead commit must tell the LSQ
1355        // when it's ready to execute the uncached load.
1356        if (!inst->isSquashed() && inst->isExecuted()) {
1357            int dependents = instQueue.wakeDependents(inst);
1358
1359            for (int i = 0; i < inst->numDestRegs(); i++) {
1360                //mark as Ready
1361                DPRINTF(IEW,"Setting Destination Register %i\n",
1362                        inst->renamedDestRegIdx(i));
1363                scoreboard->setReg(inst->renamedDestRegIdx(i));
1364            }
1365
1366            producerInst[tid]++;
1367            consumerInst[tid]+= dependents;
1368            writebackCount[tid]++;
1369        }
1370    }
1371}
1372
1373template<class Impl>
1374void
1375DefaultIEW<Impl>::tick()
1376{
1377    wbNumInst = 0;
1378    wbCycle = 0;
1379
1380    wroteToTimeBuffer = false;
1381    updatedQueues = false;
1382
1383    sortInsts();
1384
1385    // Free function units marked as being freed this cycle.
1386    fuPool->processFreeUnits();
1387
1388    list<unsigned>::iterator threads = (*activeThreads).begin();
1389
1390    // Check stall and squash signals, dispatch any instructions.
1391    while (threads != (*activeThreads).end()) {
1392           unsigned tid = *threads++;
1393
1394        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1395
1396        checkSignalsAndUpdate(tid);
1397        dispatch(tid);
1398    }
1399
1400    if (exeStatus != Squashing) {
1401        executeInsts();
1402
1403        writebackInsts();
1404
1405        // Have the instruction queue try to schedule any ready instructions.
1406        // (In actuality, this scheduling is for instructions that will
1407        // be executed next cycle.)
1408        instQueue.scheduleReadyInsts();
1409
1410        // Also should advance its own time buffers if the stage ran.
1411        // Not the best place for it, but this works (hopefully).
1412        issueToExecQueue.advance();
1413    }
1414
1415    bool broadcast_free_entries = false;
1416
1417    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1418        exeStatus = Idle;
1419        updateLSQNextCycle = false;
1420
1421        broadcast_free_entries = true;
1422    }
1423
1424    // Writeback any stores using any leftover bandwidth.
1425    ldstQueue.writebackStores();
1426
1427    // Check the committed load/store signals to see if there's a load
1428    // or store to commit.  Also check if it's being told to execute a
1429    // nonspeculative instruction.
1430    // This is pretty inefficient...
1431
1432    threads = (*activeThreads).begin();
1433    while (threads != (*activeThreads).end()) {
1434        unsigned tid = (*threads++);
1435
1436        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1437
1438        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1439            !fromCommit->commitInfo[tid].squash &&
1440            !fromCommit->commitInfo[tid].robSquashing) {
1441
1442            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1443
1444            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1445
1446            updateLSQNextCycle = true;
1447            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1448        }
1449
1450        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1451
1452            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1453            if (fromCommit->commitInfo[tid].uncached) {
1454                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1455            } else {
1456                instQueue.scheduleNonSpec(
1457                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1458            }
1459        }
1460
1461        if (broadcast_free_entries) {
1462            toFetch->iewInfo[tid].iqCount =
1463                instQueue.getCount(tid);
1464            toFetch->iewInfo[tid].ldstqCount =
1465                ldstQueue.getCount(tid);
1466
1467            toRename->iewInfo[tid].usedIQ = true;
1468            toRename->iewInfo[tid].freeIQEntries =
1469                instQueue.numFreeEntries();
1470            toRename->iewInfo[tid].usedLSQ = true;
1471            toRename->iewInfo[tid].freeLSQEntries =
1472                ldstQueue.numFreeEntries(tid);
1473
1474            wroteToTimeBuffer = true;
1475        }
1476
1477        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1478                tid, toRename->iewInfo[tid].dispatched);
1479    }
1480
1481    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1482            "LSQ has %i free entries.\n",
1483            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1484            ldstQueue.numFreeEntries());
1485
1486    updateStatus();
1487
1488    if (wroteToTimeBuffer) {
1489        DPRINTF(Activity, "Activity this cycle.\n");
1490        cpu->activityThisCycle();
1491    }
1492}
1493
1494template <class Impl>
1495void
1496DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1497{
1498    int thread_number = inst->threadNumber;
1499
1500    //
1501    //  Pick off the software prefetches
1502    //
1503#ifdef TARGET_ALPHA
1504    if (inst->isDataPrefetch())
1505        exeSwp[thread_number]++;
1506    else
1507        iewExecutedInsts++;
1508#else
1509    iewExecutedInsts++;
1510#endif
1511
1512    //
1513    //  Control operations
1514    //
1515    if (inst->isControl())
1516        exeBranches[thread_number]++;
1517
1518    //
1519    //  Memory operations
1520    //
1521    if (inst->isMemRef()) {
1522        exeRefs[thread_number]++;
1523
1524        if (inst->isLoad()) {
1525            iewExecLoadInsts[thread_number]++;
1526        }
1527    }
1528}
1529